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? 2015-2016 microchip technology inc. ds60001320d-page 1 pic32mz embedded connectivity with floating poin t unit (ef) family operating conditions 2.1v to 3.6v, -40oc to +85oc, dc to 252 mhz 2.1v to 3.6v, -40oc to +125oc, dc to 180 mhz core: 252 mhz (up to 415 dmips) m-class 16 kb i-cache, 4 kb d-cache fpu for 32-bit and 64-bit floating point math mmu for optimum embedded os execution micromips? mode for up to 35% smaller code size dsp-enhanced core: - four 64-bit accumulators - single-cycle mac, saturating, and fractional math - ieee 754-compliant code-efficient (c and assembly) architecture clock management programmable plls and oscillator clock sources fail-safe clock monitor (fscm) independent watchdog timers (wdt) and deadman timer (dmt) fast wake-up and start-up power management low-power modes (sleep and idle) integrated power-on reset (por) and brown-out reset (bor) memory interfaces 50 mhz external bus interface (ebi) 50 mhz serial quad interface (sqi) audio and graphics interfaces graphics interfaces: ebi or pmp audio data communication: i 2 s, lj, and rj audio control interfaces: spi and i 2 c audio master clock: fractional clock frequencies with usb synchronization high-speed (hs) communication interfaces ? (with dedicated dma) usb 2.0-compliant hi-speed on-the-go (otg) controller 10/100 mbps ethernet mac with mii and rmii interface security features crypto engine with rng for data encryption/decryption and authentication (aes, 3des, sha, md5, and hmac) advanced memory protection: - peripheral and memory region access control direct memory access (dma) eight channels with automatic data size detection programmable cyclic redundancy check (crc) advanced analog features 12-bit adc module: - 18 msps with up to six sample and hold (s&h) circuits (five dedicated and one shared) - up to 48 analog inputs - can operate during sleep and idle modes - multiple trigger sources - six digital comparators and six digital filters two comparators with 32 programmable voltage references temperature sensor with 2oc accuracy communication interfaces two can modules (with dedicated dma channels): - 2.0b active with devicenet? addressing support six uart modules (25 mbps): - supports up to lin 2.1 and irda ? protocols six 4-wire spi modules (up to 50 mhz) sqi configurable as an additional spi module (50 mhz) five i 2 c modules (up to 1 mbaud) with smbus support parallel master port (pmp) peripheral pin select (pps) to enable function remap timers/output compare/input capture nine 16-bit or up to four 32-bit timers/counters nine output compare (oc) modules nine input capture (ic) modules real-time clock and calendar (rtcc) module input/output 5v-tolerant pins with up to 32 ma source/sink selectable open drain, pull-ups, pull-downs, and slew rate controls external interrupts on all i/o pins pps to enable function remap qualification and class b support aec-q100 revh (grade 1 -40oc to +125oc) class b safety library, iec 60730 (planned) back-up internal oscillator debugger development support in-circuit and in-application programming 4-wire mips ? enhanced jtag interface unlimited software and 12 complex breakpoints ieee 1149.2-compatible (jtag) boundary scan non-intrusive hardware-based instruction trace software and tools support c/c++ compiler with native dsp/fractional and fpu support mplab ? harmony integrated software framework tcp/ip, usb, graphics, and mtouch? middleware mfi, android?, and bluetooth ? audio frameworks rtos kernels: express logic threadx, freertos?, openrtos ? , micrim ? c/os?, and segger embos ? packages type qfn tqfp tfbga (1) vtla lqfp pin count 64 64 100 144 100 144 124 144 i/o pins (up to) 53 53 78 120 78 120 98 120 contact/lead pitch 0.50 mm 0.50 mm 0.40 mm 0.50 mm 0.40 mm 0.65 mm 0.50 mm 0.50 mm 0.50 mm dimensions 9x9x0.9 mm 10x10x1 mm 12x12x1 mm 14x14x1 mm 16x16x1 mm 7x7x1.2 mm 7x7x1.2 mm 9x9x0.9 mm 20x20x1.40 mm note 1: contact your local microchip sales office for information on the availability of device s in the 100-pin and 144-pin tfbga packa ges 32-bit mcus (up to 2 mb live-updat e flash and 512 kb sram) with fpu, audio and graphics interfaces, hs usb, ethernet, an d advanced analog
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 2 ? 2015-2016 microchip technology inc. table 1: pic32mz ef family features device program memory (kb) data memory (kb) pins packages boot flash memory (kb) remappable peripherals crypto rng dma channels (programmable/ dedicated) adc (channels) analog comparators usb 2.0 hs otg i 2 c pmp ebi sqi rtcc ethernet i/o pins jtag trace remappable pins timers/ capture/ compare (1) uart spi/i 2 s external interrupts (2) can 2.0b PIC32MZ0512EFE064 512 128 64 tqfp, qfn 160 34 9/9/9 6 4 5 0ny8 / 1 2 24 2 y 4 y n y y y 46 y y pic32mz0512eff064 2ny8 / 1 6 pic32mz0512efk064 2yy8 / 1 8 pic32mz1024efe064 1024 0ny8 / 1 2 pic32mz1024eff064 256 2 n y 8/16 pic32mz1024efk064 2yy8 / 1 8 pic32mz0512efe100 512 128 100 tqfp 160 51 9/9/9 6 6 5 0ny8 / 1 2 40 2 y 5 y y y y y 78 y y pic32mz0512eff100 2ny8 / 1 6 pic32mz0512efk100 2yy8 / 1 8 pic32mz1024efe100 1024 0ny8 / 1 2 pic32mz1024eff100 256 2 n y 8/16 pic32mz1024efk100 2yy8 / 1 8 pic32mz0512efe124 512 128 124 vtla 160 53 9/9/9 6 6 5 0ny8 / 1 2 48 2 y 5 y y y y y 97 y y pic32mz0512eff124 2ny8 / 1 6 pic32mz0512efk124 2yy8 / 1 8 pic32mz1024efe124 1024 0ny8 / 1 2 pic32mz1024eff124 256 2 n y 8/16 pic32mz1024efk124 2yy8 / 1 8 pic32mz0512efe144 512 128 144 lqfp, tqfp 160 53 9/9/9 6 6 5 0ny8 / 1 2 48 2 y 5 y y y y y 120 y y pic32mz0512eff144 2ny8 / 1 6 pic32mz0512efk144 2yy8 / 1 8 pic32mz1024efe144 1024 256 0ny8 / 1 2 pic32mz1024eff144 2ny8 / 1 6 pic32mz1024efk144 2yy8 / 1 8 note 1: eight out of nine timers are remappable. 2: four out of five external interrupts are remappable. 3: this device is available with a 252 mhz speed rating.
? 2015-2016 microchip technology inc. ds60001320d-page 3 pic32mz embedded connectivity with floating point unit (ef) family pic32mz1024efg064 1024 512 64 tqfp, qfn 160 34 9/9/9 6 4 5 0ny8 / 1 2 24 2 y 4 y n y y y 46 y y pic32mz1024efh064 2ny8 / 1 6 pic32mz1024efm064 2yy8 / 1 8 pic32mz2048efg064 2048 0ny8 / 1 2 pic32mz2048efh064 (3) 2ny8 / 1 6 pic32mz2048efm064 2yy8 / 1 8 pic32mz1024efg100 1024 512 100 tqfp 160 51 9/9/9 6 6 5 0ny8 / 1 2 40 2 y 5 y y y y y 78 y y pic32mz1024efh100 2ny8 / 1 6 pic32mz1024efm100 2yy8 / 1 8 pic32mz2048efg100 2048 0ny8 / 1 2 pic32mz2048efh100 (3) 2ny8 / 1 6 pic32mz2048efm100 2yy8 / 1 8 pic32mz1024efg124 1024 512 124 vtla 160 53 9/9/9 6 6 5 0ny8 / 1 2 48 2 y 5 y y y y y 97 y y pic32mz1024efh124 2ny8 / 1 6 pic32mz1024efm124 2yy8 / 1 8 pic32mz2048efg124 2048 0ny8 / 1 2 pic32mz2048efh124 2ny8 / 1 6 pic32mz2048efm124 2yy8 / 1 8 pic32mz1024efg144 1024 512 144 lqfp, tqfp 160 53 9/9/9 6 6 5 0ny8 / 1 2 48 2 y 5 y y y y y 120 y y pic32mz1024efh144 2ny8 / 1 6 pic32mz1024efm144 2yy8 / 1 8 pic32mz2048efg144 2048 0ny8 / 1 2 pic32mz2048efh144 (3) 2ny8 / 1 6 pic32mz2048efm144 2yy8 / 1 8 table 1: pic32mz ef family features (continued) device program memory (kb) data memory (kb) pins packages boot flash memory (kb) remappable peripherals crypto rng dma channels (programmable/ dedicated) adc (channels) analog comparators usb 2.0 hs otg i 2 c pmp ebi sqi rtcc ethernet i/o pins jtag trace remappable pins timers/ capture/ compare (1) uart spi/i 2 s external interrupts (2) can 2.0b note 1: eight out of nine timers are remappable. 2: four out of five external interrupts are remappable. 3: this device is available with a 252 mhz speed rating.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 4 ? 2015-2016 microchip technology inc. device pin tables table 2: pin names for 64-pin devices pin # full pin name pin # full pin name 1 an17/etxen/rpe5/pmd5/re5 33 v bus 2 an16/etxd0/pmd6/re6 34 v usb 3 v 3 3 an15/etxd1/pmd7/re7 35 v ss 4 an14/c1ind/rpg6/sck2/pma5/rg6 36 d- 5 an13/c1inc/rpg7/sda4/pma4/rg7 37 d+ 6 an12/c2ind/rpg8/scl4/pma3/rg8 38 rpf3/usbid/rf3 7v ss 39 v dd 8v dd 40 v ss 9mclr 41 rpf4/sda5/pma9/rf4 10 an11/c2inc/rpg9/pma2/rg9 42 rpf5/scl5/pma8/rf5 11 an45/c1ina/rpb5/rb5 43 aerxd0/etxd2/rpd9/sda1/pmcs2/pma15/rd9 12 an4/c1inb/rb4 44 ecol/rpd10/scl1/sck4/rd10 13 an3/c2ina/rpb3/rb3 45 aerxclk/aerefclk/ecrs/rpd11/pmcs1/pma14/rd11 14 an2/c2inb/rpb2/rb2 46 aerxd1/etxd3/rpd0/rtcc/int0/rd0 15 pgec1/v ref -/cv ref -/an1/rpb1/rb1 47 sosci/rpc13/rc13 16 pged1/v ref +/cv ref +/an0/rpb0/pma6/rb0 48 sosco/rpc14/t1ck/rc14 17 pgec2/an46/rpb6/rb6 49 emdio/aemdio/rpd1/sck1/rd1 18 pged2/an47/rpb7/rb7 50 etxerr/aetxen/rpd2/sda3/rd2 19 av dd 51 aerxerr/etxclk/rpd3/scl3/rd3 20 avss 52 sqics0 /rpd4/pmwr/rd4 21 an48/rpb8/pma10/rb8 53 sqics1 /rpd5/pmrd/rd5 22 an49/rpb9/pma7/rb9 54 v dd 23 tms/cv refout /an5/rpb10/pma13/rb10 55 v ss 24 tdo/an6/pma12/rb11 56 erxd3/aetxd1/rpf0/rf0 25 v ss 57 trclk/sqiclk/erxd2/aetxd0/rpf1/rf1 26 v dd 58 trd0/sqid0/erxd1/pmd0/re0 27 tck/an7/pma11/rb12 59 v ss 28 tdi/an8/rb13 60 v dd 29 an9/rpb14/sck3/pma1/rb14 61 trd1/sqid1/erxd0/pmd1/re1 30 an10/emdc/aemdc/rpb15/ocfb/pma0/rb15 62 trd2/sqid2/erxdv/ecrs dv/aecrsdv/pmd2/re2 31 osc1/clki/rc12 63 trd3/sqid3/erxclk/erefclk/rpe3/pmd3/re3 32 osc2/clko/rc15 64 an18/erxerr/pmd4/re4 note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.4 peripheral pin select (pps) for restrictions. 2: every i/o port pin (rbx-rgx) can be used as a change notification pin (cnbx-cngx). s ee section 12.0 i/o ports for more information. 3: shaded pins are 5v tolerant. 4: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. 1 64 64-pin qfn (4) and tqfp (top view) pic32mz0512ef(e/f/k)064 pic32mz1024ef(g/h/m)064 pic32mz2048ef(g/h/m)064 tqfp qfn (4) pic32mz1024ef(e/f/k)064 1 64
? 2015-2016 microchip technology inc. ds60001320d-page 5 pic32mz embedded connectivity with floating point unit (ef) family table 3: pin names for 100-pin devices pin # full pin name pin # full pin name 1 an23/aerxerr/rg15 36 v ss 2 ebia5/an34/pma5/ra5 37 v dd 3 ebid5/an17/rpe5/pmd5/re5 38 tck/ebia19/an29/ra1 4 ebid6/an16/pmd6/re6 39 tdi/ebia18/an30/rpf13/sck5/rf13 5 ebid7/an15/pmd7/re7 40 tdo/ebia17/an31/rpf12/rf12 6 ebia6/an22/rpc1/pma6/rc1 41 ebia11/an7/erxd0/aecrs/pma11/rb12 7 ebia12/an21/rpc2/pma12/rc2 42 an8/erxd1/aecol/rb13 8 ebiwe /an20/rpc3/pmwr/rc3 43 ebia1/an9/erx d2/aetxd3/rpb14/sck3/pma1/rb14 9 ebioe /an19/rpc4/pmrd/rc4 44 ebia0/an10/erxd3/aetxd2/rpb15/ocfb/pma0/rb15 10 an14/c1ind/ecol/rpg6/sck2/rg6 45 v ss 11 ebia4/an13/c1inc/ecrs/rpg7/sda4/pma4/rg7 46 v dd 12 ebia3/an12/c2ind/erxdv/ecrsdv/aerxdv/ aecrsdv/rpg8/scl4/pma3/rg8 47 an32/aetxd0/rpd14/rd14 13 v ss 48 an33/aetxd1/rpd15/sck6/rd15 14 v dd 49 osc1/clki/rc12 15 mclr 50 osc2/clko/rc15 16 ebia2/an11/c2inc/erxclk/erefclk/aerxclk/ aerefclk/rpg9/pma2/rg9 51 v bus 17 tms/ebia16/an24/ra0 52 v usb 3 v 3 18 an25/aerxd0/rpe8/re8 53 v ss 19 an26/aerxd1/rpe9/re9 54 d- 20 an45/c1ina/rpb5/rb5 55 d+ 21 an4/c1inb/rb4 56 rpf3/usbid/rf3 22 an3/c2ina/rpb3/rb3 57 ebirdy3/rpf2/sda3/rf2 23 an2/c2inb/rpb2/rb2 58 ebirdy2/rpf8/scl3/rf8 24 pgec1/an1/rpb1/rb1 59 ebics0 /scl2/ra2 25 pged1/an0/rpb0/rb0 60 ebirdy1/sda2/ra3 26 pgec2/an46/rpb6/rb6 61 ebia14/pmcs1/pma14/ra4 27 pged2/an47/rpb7/rb7 62 v dd 28 v ref -/cv ref -/an27/aerxd2/ra9 63 v ss 29 v ref +/cv ref +/an28/aerxd3/ra10 64 ebia9/rpf4/sda5/pma9/rf4 30 av dd 65 ebia8/rpf5/scl5/pma8/rf5 31 av ss 66 aetxclk/rpa14/scl1/ra14 32 ebia10/an48/rpb8/pma10/rb8 67 aetxen/rpa15/sda1/ra15 33 ebia7/an49/rpb9/pma7/rb9 68 ebia15/rpd9/pmcs2/pma15/rd9 34 ebia13/cv refout /an5/rpb10/pma13/rb10 69 rpd10/sck4/rd10 35 an6/erxerr/aetxerr/rb11 70 emdc/aemdc/rpd11/rd11 note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.4 peripheral pin select (pps) for restrictions. 2: every i/o port pin (rax-rgx) can be used as a change notification pin (cnax-cngx). see section 12.0 i/o ports for more information. 3: shaded pins are 5v tolerant. 1 100 100-pin tqfp (top view) pic32mz0512ef(e/f/k)100 pic32mz1024ef(g/h/m)100 pic32mz2048ef(g/h/m)100 pic32mz1024ef(e/f/k)100
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 6 ? 2015-2016 microchip technology inc. 71 emdio/aemdio/rpd0/rtcc/int0/rd0 86 ebid10/etxd0/rpf1/pmd10/rf1 72 sosci/rpc13/rc13 87 ebid9/etxerr/rpg1/pmd9/rg1 73 sosco/rpc14/t1ck/rc14 88 ebid8/rpg0/pmd8/rg0 74 v dd 89 trclk/sqiclk/ra6 75 v ss 90 trd3/sqid3/ra7 76 rpd1/sck1/rd1 91 ebid0/pmd0/re0 77 ebid14/etxen/rpd2/pmd14/rd2 92 v ss 78 ebid15/etxclk/rpd3/pmd15/rd3 93 v dd 79 ebid12/etxd2/rpd12/pmd12/rd12 94 ebid1/pmd1/re1 80 ebid13/etxd3/pmd13/rd13 95 trd2/sqid2/rg14 81 sqics0 /rpd4/rd4 96 trd1/sqid1/rg12 82 sqics1 /rpd5/rd5 97 trd0/sqid0/rg13 83 v dd 98 ebid2/pmd2/re2 84 v ss 99 ebid3/rpe3/pmd3/re3 85 ebid11/etxd1/rpf0/pmd11/rf0 100 ebid4/an18/pmd4/re4 table 3: pin names for 100-pin devices (continued) pin # full pin name pin # full pin name note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.4 peripheral pin select (pps) for restrictions. 2: every i/o port pin (rax-rgx) can be used as a change notification pin (cnax-cngx). see section 12.0 i/o ports for more information. 3: shaded pins are 5v tolerant. 1 100 100-pin tqfp (top view) pic32mz0512ef(e/f/k)100 pic32mz1024ef(g/h/m)100 pic32mz2048ef(g/h/m)100 pic32mz1024ef(e/f/k)100
? 2015-2016 microchip technology inc. ds60001320d-page 7 pic32mz embedded connectivity with floating point unit (ef) family table 4: pin names for 124-pin devices package pin # full pin name package pin # full pin name a1 no connect a35 v bus a2 an23/rg15 a36 v usb 3 v 3 a3 ebid5/an17/rpe5/pmd5/re5 a37 d- a4 ebid7/an15/pmd7/re7 a38 rpf3/usbid/rf3 a5 an35/etxd0/rj8 a39 ebirdy2/rpf8/scl3/rf8 a6 ebia12/an21/rpc2/pma12/rc2 a40 erxd3/rh9 a7 ebioe /an19/rpc4/pmrd/rc4 a41 ebics0 /scl2/ra2 a8 ebia4/an13/c1inc/rpg7/sda4/pma4/rg7 a42 ebia14/pmcs1/pma14/ra4 a9 v ss a43 v ss a10 mclr a44 ebia8/rpf5/scl5/pma8/rf5 a11 tms/ebia16/an24/ra0 a45 rpa15/sda1/ra15 a12 an26/rpe9/re9 a46 rpd10/sck4/rd10 a13 an4/c1inb/rb4 a47 ecrs/rh12 a14 an3/c2ina/rpb3/rb3 a48 rpd0/rtcc/int0/rd0 a15 v dd a49 sosco/rpc14/t1ck/rc14 a16 an2/c2inb/rpb2/rb2 a50 v dd a17 pgec1/an1/rpb1/rb1 a51 v ss a18 pged1/an0/rpb0/rb0 a52 rpd1/sck1/rd1 a19 pged2/an47/rpb7/rb7 a53 ebid15/rpd3/pmd15/rd3 a20 vref+/cv ref +/an28/ra10 a54 ebid13/pmd13/rd13 a21 av ss a55 emdio/rj1 a22 an39/etxd3/rh1 a56 sqics0 /rpd4/rd4 a23 ebia7/an49/rpb9/pma7/rb9 a57 etxen/rpd6/rd6 a24 an6/rb11 a58 v dd a25 v dd a59 ebid11/rpf0/pmd11/rf0 a26 tdi/ebia18/an30/rpf13/sck5/rf13 a60 ebid9/rpg1/pmd9/rg1 a27 ebia11/an7/pma11/rb12 a61 trclk/sqiclk/ra6 a28 ebia1/an9/rpb14/sck3/pma1/rb14 a62 rj4 a29 v ss a63 v ss a30 an40/erxerr/rh4 a64 ebid1/pmd1/re1 a31 an42/erxd2/rh6 a65 trd1/sqid1/rg12 a32 an33/rpd15/sck6/rd15 a66 ebid2/sqid2/pmd2/re2 a33 osc2/clko/rc15 a67 ebid4/an18/pmd4/re4 a34 no connect a68 no connect note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.4 peripheral pin select (pps) for restrictions. 2: every i/o port pin (rax-rjx) can be used as a change notification pin (cnax-cnjx). s ee section 12.0 i/o ports for more information. 3: shaded pins are 5v tolerant. 4: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. a1 a68 a17 b29 b13 b41 b1 a34 a51 b56 124-pin vtla (bottom view) polarity indicator pic32mz0512ef(e/f/k)124 pic32mz1024ef(g/h/m)124 pic32mz2048ef(g/h/m)124 pic32mz1024ef(e/f/k)124
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 8 ? 2015-2016 microchip technology inc. b1 ebia5/an34/pma5/ra5 b29 v ss b2 ebid6/an16/pmd6/re6 b30 d+ b3 ebia6/an22/rpc1/pma6/rc1 b31 rpf2/sda3/rf2 b4 an36/etxd1/rj9 b32 erxd0/rh8 b5 ebiwe /an20/rpc3/pmwr/rc3 b33 ecol/rh10 b6 an14/c1ind/rpg6/sck2/rg6 b34 ebirdy1/sda2/ra3 b7 ebia3/an12/c2ind/rpg8/scl4/pma3/rg8 b35 v dd b8 v dd b36 ebia9/rpf4/sda5/pma9/rf4 b9 ebia2/an11/c2inc/rpg9/pma2/rg9 b37 rpa14/scl1/ra14 b10 an25/rpe8/re8 b38 ebia15/rpd9/pmcs2/pma15/rd9 b11 an45/c1ina/rpb5/rb5 b39 emdc/rpd11/rd11 b12 an37/erxclk/erefclk/rj11 b40 erxdv/ecrsdv/rh13 b13 v ss b41 sosci/rpc13/rc13 b14 pgec2/an46/rpb6/rb6 b42 ebid14/rpd2/pmd14/rd2 b15 v ref -/cv ref -/an27/ra9 b43 ebid12/rpd12/pmd12/rd12 b16 av dd b44 etxerr/rj0 b17 an38/etxd2/rh0 b45 ebirdy3/rj2 b18 ebia10/an48/rpb8/pma10/rb8 b46 sqics1 /rpd5/rd5 b19 ebia13/cv refout /an5/rpb10/pma13/rb10 b47 etxclk/rpd7/rd7 b20 v ss b48 v ss b21 tck/ebia19/an29/ra1 b49 ebid10/rpf1/pmd10/rf1 b22 tdo/ebia17/an31/rpf12/rf12 b50 ebid8/rpg0/pmd8/rg0 b23 an8/rb13 b51 trd3/sqid3/ra7 b24 ebia0/an10/rpb15/ocfb/pma0/rb15 b52 ebid0/pmd0/re0 b25 v dd b53 v dd b26 an41/erxd1/rh5 b54 trd2/sqid2/rg14 b27 an32/aetxd0/rpd14/rd14 b55 trd0/sqid0/rg13 b28 osc1/clki/rc12 b56 ebid3/rpe3/pmd3/re3 table 4: pin names for 124-pin devices (continued) package pin # full pin name package pin # full pin name note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.4 peripheral pin select (pps) for restrictions. 2: every i/o port pin (rax-rjx) can be used as a change notification pin (cnax-cnjx). see section 12.0 i/o ports for more information. 3: shaded pins are 5v tolerant. 4: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. a1 a68 a17 b29 b13 b41 b1 a34 a51 b56 124-pin vtla (bottom view) polarity indicator pic32mz0512ef(e/f/k)124 pic32mz1024ef(g/h/m)124 pic32mz2048ef(g/h/m)124 pic32mz1024ef(e/f/k)124
? 2015-2016 microchip technology inc. ds60001320d-page 9 pic32mz embedded connectivity with floating point unit (ef) family table 5: pin names for 144-pin devices pin number full pin name pin number full pin name 1 an23/rg15 37 pgec2/an46/rpb6/rb6 2 ebia5/an34/pma5/ra5 38 pged2/an47/rpb7/rb7 3 ebid5/an17/rpe5/pmd5/re5 39 v ref -/cv ref -/an27/ra9 4 ebid6/an16/pmd6/re6 40 v ref +/cv ref +/an28/ra10 5 ebid7/an15/pmd7/re7 41 av dd 6 ebia6/an22/rpc1/pma6/rc1 42 av ss 7 an35/etxd0/rj8 43 an38/etxd2/rh0 8 an36/etxd1/rj9 44 an39/etxd3/rh1 9 ebibs0 /rj12 45 ebirp /rh2 10 ebibs1 /rj10 46 rh3 11 ebia12/an21/rpc2/pma12/rc2 47 ebia10/an48/rpb8/pma10/rb8 12 ebiwe /an20/rpc3/pmwr/rc3 48 ebia7/an49/rpb9/pma7/rb9 13 ebioe /an19/rpc4/pmrd/rc4 49 cv refout /an5/rpb10/rb10 14 an14/c1ind/rpg6/sck2/rg6 50 an6/rb11 15 an13/c1inc/rpg7/sda4/rg7 51 ebia1/pma1/rk1 16 an12/c2ind/rpg8/scl4/rg8 52 ebia3/pma3/rk2 17 v ss 53 ebia17/rk3 18 v dd 54 v ss 19 ebia16/rk0 55 v dd 20 mclr 56 tck/an29/ra1 21 ebia2/an11/c2inc/rpg9/pma2/rg9 57 tdi/an30/rpf13/sck5/rf13 22 tms/an24/ra0 58 tdo/an31/rpf12/rf12 23 an25/rpe8/re8 59 an7/rb12 24 an26/rpe9/re9 60 an8/rb13 25 an45/c1ina/rpb5/rb5 61 an9/rpb14/sck3/rb14 26 an4/c1inb/rb4 62 an10/rpb15/ocfb/rb15 27 an37/erxclk/erefclk/rj11 63 v ss 28 ebia13/pma13/rj13 64 v dd 29 ebia11/pma11/rj14 65 an40/erxerr/rh4 30 ebia0/pma0/rj15 66 an41/erxd1/rh5 31 an3/c2ina/rpb3/rb3 67 an42/erxd2/rh6 32 v ss 68 ebia4/pma4/rh7 33 v dd 69 an32/rpd14/rd14 34 an2/c2inb/rpb2/rb2 70 an33/rpd15/sck6/rd15 35 pgec1/an1/rpb1/rb1 71 osc1/clki/rc12 36 pged1/an0/rpb0/rb0 72 osc2/clko/rc15 note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.4 peripheral pin select (pps) for restrictions. 2: every i/o port pin (rax-rkx) can be used as a change notification pin (cn ax-cnkx). see section 12.0 i/o ports for more information. 3: shaded pins are 5v tolerant. 1 144 144-pin lqfp and tqfp (top view) pic32mz0512ef(e/f/k)144 pic32mz1024ef(g/h/m)144 pic32mz2048ef(g/h/m)144 pic32mz1024ef(e/f/k)144
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 10 ? 2015-2016 microchip technology inc. 73 v bus 109 rpd1/sck1/rd1 74 v usb 3 v 3 110 ebid14/rpd2/pmd14/rd2 75 v ss 111 ebid15/rpd3/pmd15/rd3 76 d- 112 ebid12/rpd12/pmd12/rd12 77 d+ 113 ebid13/pmd13/rd13 78 rpf3/usbid/rf3 114 etxerr/rj0 79 sda3/rpf2/rf2 115 emdio/rj1 80 scl3/rpf8/rf8 116 ebirdy3/rj2 81 erxd0/rh8 117 ebia22/rj3 82 erxd3/rh9 118 sqics0 /rpd4/rd4 83 ecol/rh10 119 sqics1 /rpd5/rd5 84 ebirdy2/rh11 120 etxen/rpd6/rd6 85 scl2/ra2 121 etxclk/rpd7/rd7 86 ebirdy1/sda2/ra3 122 v dd 87 ebia14/pmcs1/pma14/ra4 123 v ss 88 v dd 124 ebid11/rpf0/pmd11/rf0 89 v ss 125 ebid10/rpf1/pmd10/rf1 90 ebia9/rpf4/sda5/pma9/rf4 126 ebia21/rk7 91 ebia8/rpf5/scl5/pma8/rf5 127 ebid9/rpg1/pmd9/rg1 92 ebia18/rk4 128 ebid8/rpg0/pmd8/rg0 93 ebia19/rk5 129 trclk/sqiclk/ra6 94 ebia20/rk6 130 trd3/sqid3/ra7 95 rpa14/scl1/ra14 131 ebics0 /rj4 96 rpa15/sda1/ra15 132 ebics1 /rj5 97 ebia15/rpd9/pmcs2/pma15/rd9 133 ebics2 /rj6 98 rpd10/sck4/rd10 134 ebics3 /rj7 99 emdc/rpd11/rd11 135 ebid0/pmd0/re0 100 ecrs/rh12 136 v ss 101 erxdv/ecrsdv/rh13 137 v dd 102 rh14 138 ebid1/pmd1/re1 103 ebia23/rh15 139 trd2/sqid2/rg14 104 rpd0/rtcc/int0/rd0 140 trd1/sqid1/rg12 105 sosci/rpc13/rc13 141 trd0/sqid0/rg13 106 sosco/rpc14/t1ck/rc14 142 ebid2/pmd2/re2 107 v dd 143 ebid3/rpe3/pmd3/re3 108 v ss 144 ebid4/an18/pmd4/re4 table 5: pin names for 144-pin devices (continued) pin number full pin name pin number full pin name note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.4 peripheral pin select (pps) for restrictions. 2: every i/o port pin (rax-rkx) can be used as a change notification pin (cn ax-cnkx). see section 12.0 i/o ports for more information. 3: shaded pins are 5v tolerant. 1 144 144-pin lqfp and tqfp (top view) pic32mz0512ef(e/f/k)144 pic32mz1024ef(g/h/m)144 pic32mz2048ef(g/h/m)144 pic32mz1024ef(e/f/k)144
? 2015-2016 microchip technology inc. ds60001320d-page 11 pic32mz embedded connectivity with floating point unit (ef) family table of contents 1.0 device overview ............................................................................ ............................................................................................ 15 2.0 guidelines for getting started with 32-bit microcontrollers .... ............................................................. ....................................... 37 3.0 cpu.............................................................................................. .............................................................................................. 43 4.0 memory organization .......................................... ................................................... ............ ........................................................ 61 5.0 flash program memory............................................................ ............................................ ...................................................... 99 6.0 resets .......................................................................................... ............................................................................................ 109 7.0 cpu exceptions and interrupt controller ........................... .......................................................... ............................................ 115 8.0 oscillator configuration ..................................... ........................................................................................................... ............ 153 9.0 prefetch module .......................................... ................................................... ................ .......................................................... 169 10.0 direct memory access (dma) controller ............................. ......................................................... ........................................... 173 11.0 hi-speed usb with on-the-go (otg) .............................. ................................................... ......... .......................................... 197 12.0 i/o ports ....................................................................................... ........................... ................................................................. 247 13.0 timer1 ......................................................................... ........................................................................................................... .. 283 14.0 timer2/3, timer4/5, timer6/7, and timer8/9.......................... ................................................... .... ........................................... 287 15.0 deadman timer (dmt) ......................................... ................................................... ............ .................................................... 293 16.0 watchdog timer (wdt) ........................................ ................................................... ............ .................................................... 301 17.0 input capture............................................ ................................................... ............... .............................................................. 305 18.0 output compare......................................................................... .................................... .......................................................... 309 19.0 serial peripheral interface (spi) and inter-ic sound (i 2 s)..................................................................................................... .. 315 20.0 serial quad interface (sqi).................................................... ............................................ ...................................................... 325 21.0 inter-integrated circuit (i 2 c) ....................................................................................................... .............................................. 353 22.0 universal asynchronous receiver transmitter (uart) ............................... .......................................... .................................. 361 23.0 parallel master port (pmp)................................................. ................................................ ...................................................... 369 24.0 external bus interface (ebi)................................................... ............................................ ...................................................... 383 25.0 real-time clock and calendar (rtcc)...................................... .................................................. ........................................... 391 26.0 crypto engine........................................................................... ................................................................................................ 401 27.0 random number generator (rng) .................................... ................................................... ....... ........................................... 421 28.0 12-bit high-speed successive appr oximation register (sar) analog-to-digital c onverter (adc)................................ ......... 427 29.0 controller area network (can) ............................... ............................................................... .................................................. 485 30.0 ethernet controller .................................................. ...................................................... ........................................................... 523 31.0 comparator .............................................................................. ................................................................................................ 567 32.0 comparator voltage reference (c v ref ) ........................................................................................................ ...................... ... 571 33.0 power-saving features ......................................................... ............................................ ...................................................... 575 34.0 special features ................................................... ........................................................ ........................................................... 581 35.0 instruction set ...................................................................... .................................................................................................... 60 5 36.0 development support............................................ ................................................... ......... ....................................................... 607 37.0 electrical characteristics ...................................................... ........................................... ......................................................... 611 38.0 extended temperature electrical characteristics ............................................. ............................... ........................................ 663 39.0 252 mh z electrical characteristics............................................................ ....................................... ........................................ 669 40.0 ac and dc characteristics graphs..................................... ................................................... ... ............................................... 675 41.0 packaging information.............................................................. ........................................ ........................................................ 677 the microchip web site ......................................................................... ................................ ............................................................ 733 customer change notification service ....................................... ................................................... . ................................................... 733 customer support ............................................... ................................................... ............. ............................................................... 733 product identification system ............................................. ..................................................... .......................................................... 734
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 12 ? 2015-2016 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is ve rsion a of document ds30000000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation i ssues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2015-2016 microchip technology inc. ds60001320d-page 13 pic32mz embedded connectivity with floating point unit (ef) family referenced sources this device data sheet is based on the following individual sections of the ?pic32 family reference manual? . these documents should be considered as the general reference for the operation of a particular module or device feature. section 1. introduction (ds60001127) section 7. resets (ds60001118) section 8. interrupt controller (ds60001108) section 9. watchdog, deadman, and power-up timers (ds60001114) section 10. power-saving features (ds60001130) section 12. i/o ports (ds60001120) section 13. parallel master port (pmp) (ds60001128) section 14. timers (ds60001105) section 15. input capture (ds60001122) section 16. output compare (ds60001111) section 19. comparator (ds60001110) section 20. comparator voltage reference (cv ref ) (ds60001109) section 21. universal asynchronous receiver transmitter (uart) (ds60001107) section 22. 12-bit high-speed successive approximation register (sar) analog-to-digital converter (adc) (ds60001344) section 23. serial peripheral interface (spi) (ds60001106) section 24. inter-integrated circuit (i 2 c) (ds60001116) section 29. real-time clock and calendar (rtcc) (ds60001125) section 31. direct memory access (dma) controller (ds60001117) section 32. configuration (ds60001124) section 33. programming and diagnostics (ds60001129) section 34. controller area network (can) (ds60001154) section 35. ethernet controller (ds60001155) section 41. prefetch module for devices with l1 cpu cache (ds60001183) section 42. oscillators with enhanced pll (ds60001250) section 46. serial quad interface (sqi) (ds60001244) section 47. external bus interface (ebi) (ds60001245) section 48. memory organization and permissions (ds60001214) section 49. crypto engine (ce) and random number generator (rng) (ds60001246) section 50. cpu for devices with mips32 ? microaptiv? and m-class cores (ds60001192) section 51. hi-speed usb with on-the-go (otg) (ds60001326) section 52. flash program memory with support for live update (ds60001193) note: to access the following documents, browse the documentation section of the microchip web site ( www.microchip.com ).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 14 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 15 pic32mz embedded connectivity with floating point unit (ef) family 1.0 device overview this data sheet contains device-specific information for pic32mz ef devices. figure 1-1 illustrates a general block diagram of the core and peripheral modules in the pic32mz ef family of devices. table 1-21 through tab l e 1-22 list the pinout i/o descriptions for the pins shown in the device pin tables (see tab l e 2 through ta bl e 5 ). figure 1-1: pic32mz ef family block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive refer - ence source. to complement the informa - tion in this data sheet, refer to the ?pic32 family reference manual? , which is avail - able from the microchip web site ( www.microchip.com/pic32 ). note: not all features are available on all devices. refer to table 1: pic32mz ef family features for the list of features by device. i9 i3, system bus i10 t1 t2 uart1-6 comparator portd portf porth portk portb mips32 ? ejtag int 128 140-bit wide i1, i12, dual panel portc pmp i2c1-5 spi1-6 ic1-9 data jtag bscan i5, flash portj portg porte timer1-9 t3 flash memory prefetch cache i13 dmac i11 cfg oc1-9 t4 i-cache d-cache system bus i/f sqi can2 can1 evic data ebi 128 i8 6 s&h sar adc pfm flash wrapper ethernet pps icd wdt rtcc porta flash controller i7 hs usb t6 t8 t5 t7 dmt cv ref t9 peripheral bus 1 i14 crypto t13 rng peripheral osc1/clki osc2/clko v dd , timing generation v ss mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset precision reference band gap frc/lprc oscillators regulator voltage p osc /s osc oscillators pll dividers pbclkx pll-usb sysclk bus 5 peripheral bus 4 peripheral bus 3 peripheral bus 2 ram bank 1 ram bank 2 controller 6 m-class core 1-2 and ecc t11 t10 i6 i4 i2 t12
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 16 ? 2015-2016 microchip technology inc. table 1-1: adc pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp an0 16 25 a18 36 i analog analog input channels an1 15 24 a17 35 i analog an2 14 23 a16 34 i analog an3 13 22 a14 31 i analog an4 12 21 a13 26 i analog an5 23 34 b19 49 i analog an6 24 35 a24 50 i analog an7 27 41 a27 59 i analog an8 28 42 b23 60 i analog an9 29 43 a28 61 i analog an10 30 44 b24 62 i analog an11 10 16 b9 21 i analog an12 6 12 b7 16 i analog an13 5 11 a8 15 i analog an14 4 10 b6 14 i analog an15 3 5 a4 5 i analog an16 2 4 b2 4 i analog an17 1 3 a3 3 i analog an18 64 100 a67 144 i analog an19 9 a7 13 i analog an20 8 b5 12 i analog an21 7 a6 11 i analog an22 6 b3 6 i analog an23 1 a2 1 i analog an24 17 a11 22 i analog an25 18 b10 23 i analog an26 19 a12 24 i analog an27 28 b15 39 i analog an28 29 a20 40 i analog an29 38 b21 56 i analog an30 39 a26 57 i analog an31 40 b22 58 i analog an32 47 b27 69 i analog an33 48 a32 70 i analog an34 2 b1 2 i analog an35 a5 7 i analog legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
? 2015-2016 microchip technology inc. ds60001320d-page 17 pic32mz embedded connectivity with floating point unit (ef) family an36 b4 8 i analog analog input channels an37 b12 27 i analog an38 b17 43 i analog an39 a22 44 i analog an40 a30 65 i analog an41 b26 66 i analog an42 a31 67 i analog an45 11 20 b11 25 i analog an46 17 26 b14 37 i analog an47 18 27 a19 38 i analog an48 21 32 b18 47 i analog an49 22 33 a23 48 i analog table 1-1: adc pinout i/o descriptions (continued) pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 18 ? 2015-2016 microchip technology inc. table 1-2: oscillator pino ut i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp clki 31 49 b28 71 i st/cmos external clock source input. always associated with osc1 pin function. clko 32 50 a33 72 o oscillator crystal output. connects to crystal or reso- nator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with osc2 pin function. osc1 31 49 b28 71 i st/cmos oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. osc2 32 50 a33 72 o oscillator crystal output. connects to crystal or reso- nator in crystal oscillator mode. optionally functions as clko in rc and ec modes. sosci 47 72 b41 105 i st/cmos 32.768 khz low-power oscillator crystal input; cmos otherwise. sosco 48 73 a49 106 o 32.768 low-power oscillator crystal output. refclki1 pps pps pps pps i reference clock generator inputs 1-4 refclki3 pps pps pps pps i refclki4 pps pps pps pps i refclko1 pps pps pps pps o reference clock generator outputs 1-4 refclko3 pps pps pps pps o refclko4 pps pps pps pps o legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select table 1-3: ic1 through ic9 pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp input capture ic1 pps pps pps pps i st input capture inputs 1-9 ic2 pps pps pps pps i st ic3 pps pps pps pps i st ic4 pps pps pps pps i st ic5 pps pps pps pps i st ic6 pps pps pps pps i st ic7 pps pps pps pps i st ic8 pps pps pps pps i st ic9 pps pps pps pps i st legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
? 2015-2016 microchip technology inc. ds60001320d-page 19 pic32mz embedded connectivity with floating point unit (ef) family table 1-4: oc1 through oc9 pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp output compare oc1 pps pps pps pps o output compare outputs 1-9 oc2 pps pps pps pps o oc3 pps pps pps pps o oc4 pps pps pps pps o oc5 pps pps pps pps o oc6 pps pps pps pps o oc7 pps pps pps pps o oc8 pps pps pps pps o oc9 pps pps pps pps o ocfa pps pps pps pps i st output compare fault a input ocfb 30 44 b24 62 i st output compare fault b input legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select table 1-5: external interrupts pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp external interrupts int0 46 71 a48 104 i st external interrupt 0 int1 pps pps pps pps i st external interrupt 1 int2 pps pps pps pps i st external interrupt 2 int3 pps pps pps pps i st external interrupt 3 int4 pps pps pps pps i st external interrupt 4 legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 20 ? 2015-2016 microchip technology inc. table 1-6: porta through port k pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp porta ra0 17 a11 22 i/o st porta is a bidirectional i/o port ra1 38 b21 56 i/o st ra2 59 a41 85 i/o st ra3 60 b34 86 i/o st ra4 61 a42 87 i/o st ra5 2 b1 2 i/o st ra6 89 a61 129 i/o st ra7 90 b51 130 i/o st ra9 28 b15 39 i/o st ra10 29 a20 40 i/o st ra14 66 b37 95 i/o st ra15 67 a45 96 i/o st portb rb0 16 25 a18 36 i/o st portb is a bidirectional i/o port rb1 15 24 a17 35 i/o st rb2 14 23 a16 34 i/o st rb3 13 22 a14 31 i/o st rb4 12 21 a13 26 i/o st rb5 11 20 b11 25 i/o st rb6 17 26 b14 37 i/o st rb7 18 27 a19 38 i/o st rb8 21 32 b18 47 i/o st rb9 22 33 a23 48 i/o st rb10 23 34 b19 49 i/o st rb11 24 35 a24 50 i/o st rb12 27 41 a27 59 i/o st rb13 28 42 b23 60 i/o st rb14 29 43 a28 61 i/o st rb15 30 44 b24 62 i/o st portc rc1 6 b3 6 i/o st portc is a bidirectional i/o port rc2 7 a6 11 i/o st rc3 8 b5 12 i/o st rc4 9 a7 13 i/o st rc12 31 49 b28 71 i/o st rc13 47 72 b41 105 i/o st rc14 48 73 a49 106 i/o st rc15 32 50 a33 72 i/o st legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
? 2015-2016 microchip technology inc. ds60001320d-page 21 pic32mz embedded connectivity with floating point unit (ef) family portd rd0 46 71 a48 104 i/o st portd is a bidirectional i/o port rd1 49 76 a52 109 i/o st rd2 50 77 b42 110 i/o st rd3 51 78 a53 111 i/o st rd4 52 81 a56 118 i/o st rd5 53 82 b46 119 i/o st rd6 a57 120 i/o st rd7 b47 121 i/o st rd9 43 68 b38 97 i/o st rd10 44 69 a46 98 i/o st rd11 45 70 b39 99 i/o st rd12 79 b43 112 i/o st rd13 80 a54 113 i/o st rd14 47 b27 69 i/o st rd15 48 a32 70 i/o st porte re0 58 91 b52 135 i/o st porte is a bidirectional i/o port re1 61 94 a64 138 i/o st re2 62 98 a66 142 i/o st re3 63 99 b56 143 i/o st re4 64 100 a67 144 i/o st re5 1 3 a3 3 i/o st re6 2 4 b2 4 i/o st re7 3 5 a4 5 i/o st re8 18 b10 23 i/o st re9 19 a12 24 i/o st portf rf0 56 85 a59 124 i/o st portf is a bidirectional i/o port rf1 57 86 b49 125 i/o st rf2 57 b31 79 i/o st rf3 38 56 a38 78 i/o st rf4 41 64 b36 90 i/o st rf5 42 65 a44 91 i/o st rf8 58 a39 80 i/o st rf12 40 b22 58 i/o st rf13 39 a26 57 i/o st table 1-6: porta throug h portk pinout i/o descriptions (continued) pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 22 ? 2015-2016 microchip technology inc. portg rg0 88 b50 128 i/o st portg is a bidirectional i/o port rg1 87 a60 127 i/o st rg6 4 10 b6 14 i/o st rg7 5 11 a8 15 i/o st rg8 6 12 b7 16 i/o st rg9 10 16 b9 21 i/o st rg12 96 a65 140 i/o st rg13 97 b55 141 i/o st rg14 95 b54 139 i/o st rg15 1 a2 1 i/o st porth rh0 b17 43 i/o st porth is a bidirectional i/o port rh1 a22 44 i/o st rh2 45 i/o st rh3 46 i/o st rh4 a30 65 i/o st rh5 b26 66 i/o st rh6 a31 67 i/o st rh7 68 i/o st rh8 b32 81 i/o st rh9 a40 82 i/o st rh10 b33 83 i/o st rh11 84 i/o st rh12 a47 100 i/o st rh13 b40 101 i/o st rh14 102 i/o st rh15 103 i/o st portj rj0 b44 114 i/o st portj is a bidirectional i/o port rj1 a55 115 i/o st rj2 b45 116 i/o st rj3 117 i/o st rj4 a62 131 i/o st rj5 132 i/o st rj6 133 i/o st rj7 134 i/o st rj8 a5 7 i/o st rj9 b4 8 i/o st rj10 10 i/o st rj11 b12 27 i/o st rj12 9 i/o st rj13 28 i/o st rj14 29 i/o st rj15 30 i/o st table 1-6: porta throug h portk pinout i/o descriptions (continued) pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
? 2015-2016 microchip technology inc. ds60001320d-page 23 pic32mz embedded connectivity with floating point unit (ef) family portk rk0 19 i/o st portk is a bidirectional i/o port rk1 51 i/o st rk2 52 i/o st rk3 53 i/o st rk4 92 i/o st rk5 93 i/o st rk6 94 i/o st rk7 126 i/o st table 1-6: porta throug h portk pinout i/o descriptions (continued) pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 24 ? 2015-2016 microchip technology inc. table 1-7: timer1 through timer9 and rtcc pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp timer1 through timer9 t1ck 48 73 a49 106 i st timer1 external clock input t2ck pps pps pps pps i st timer2 external clock input t3ck pps pps pps pps i st timer3 external clock input t4ck pps pps pps pps i st timer4 external clock input t5ck pps pps pps pps i st timer5 external clock input t6ck pps pps pps pps i st timer6 external clock input t7ck pps pps pps pps i st timer7 external clock input t8ck pps pps pps pps i st timer8 external clock input t9ck pps pps pps pps i st timer9 external clock input real-time clock and calendar rtcc 46 71 a48 104 o real-time clock alarm/seconds output legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
? 2015-2016 microchip technology inc. ds60001320d-page 25 pic32mz embedded connectivity with floating point unit (ef) family table 1-8: uart1 through uart6 pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp universal asynchronous receiver transmitter 1 u1rx pps pps pps pps i st uart1 receive u1tx pps pps pps pps o uart1 transmit u1cts pps pps pps pps i st uart1 clear to send u1rts pps pps pps pps o uart1 ready to send universal asynchronous receiver transmitter 2 u2rx pps pps pps pps i st uart2 receive u2tx pps pps pps pps o uart2 transmit u2cts pps pps pps pps i st uart2 clear to send u2rts pps pps pps pps o uart2 ready to send universal asynchronous receiver transmitter 3 u3rx pps pps pps pps i st uart3 receive u3tx pps pps pps pps o uart3 transmit u3cts pps pps pps pps i st uart3 clear to send u3rts pps pps pps pps o uart3 ready to send universal asynchronous receiver transmitter 4 u4rx pps pps pps pps i st uart4 receive u4tx pps pps pps pps o uart4 transmit u4cts pps pps pps pps i st uart4 clear to send u4rts pps pps pps pps o uart4 ready to send universal asynchronous receiver transmitter 5 u5rx pps pps pps pps i st uart5 receive u5tx pps pps pps pps o uart5 transmit u5cts pps pps pps pps i st uart5 clear to send u5rts pps pps pps pps o uart5 ready to send universal asynchronous receiver transmitter 6 u6rx pps pps pps pps i st uart6 receive u6tx pps pps pps pps o uart6 transmit u6cts pps pps pps pps i st uart6 clear to send u6rts pps pps pps pps o uart6 ready to send legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 26 ? 2015-2016 microchip technology inc. table 1-9: spi1 through spi 6 pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp serial peripheral interface 1 sck1 49 76 a52 109 i/o st spi1 synchronous serial clock input/output sdi1 pps pps pps pps i st spi1 data in sdo1 pps pps pps pps o spi1 data out ss1 pps pps pps pps i/o st spi1 slave synchronization or frame pulse i/o serial peripheral interface 2 sck2 4 10 b6 14 i/o st spi2 synchronous serial clock input/output sdi2 pps pps pps pps i st spi2 data in sdo2 pps pps pps pps o spi2 data out ss2 pps pps pps pps i/o st spi2 slave synchronization or frame pulse i/o serial peripheral interface 3 sck3 29 43 a28 61 i/o st spi3 synchronous serial clock input/output sdi3 pps pps pps pps i st spi3 data in sdo3 pps pps pps pps o spi3 data out ss3 pps pps pps pps i/o st spi3 slave synchronization or frame pulse i/o serial peripheral interface 4 sck4 44 69 a46 98 i/o st spi4 synchronous serial clock input/output sdi4 pps pps pps pps i st spi4 data in sdo4 pps pps pps pps o spi4 data out ss4 pps pps pps pps i/o st spi4 slave synchronization or frame pulse i/o serial peripheral interface 5 sck5 39 a26 57 i/o st spi5 synchronous serial clock input/output sdi5 pps pps pps i st spi5 data in sdo5 pps pps pps o spi5 data out ss5 pps pps pps i/o st spi5 slave synchronization or frame pulse i/o serial peripheral interface 6 sck6 48 a32 70 i/o st spi6 synchronous serial clock input/output sdi6 pps pps pps i st spi6 data in sdo6 pps pps pps o spi6 data out ss6 pps pps pps i/o st spi6 slave synchronization or frame pulse i/o legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
? 2015-2016 microchip technology inc. ds60001320d-page 27 pic32mz embedded connectivity with floating point unit (ef) family table 1-10: i2c1 through i2c5 pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp inter-integrated circuit 1 scl1 44 66 b37 95 i/o st i2c1 synchronous serial clock input/output sda1 43 67 a45 96 i/o st i2c1 synchronous serial data input/output inter-integrated circuit 2 scl2 59 a41 85 i/o st i2c2 synchronous serial clock input/output sda2 60 b34 86 i/o st i2c2 synchronous serial data input/output inter-integrated circuit 3 scl3 51 58 a39 80 i/o st i2c3 synchronous serial clock input/output sda3 50 57 b31 79 i/o st i2c3 synchronous serial data input/output inter-integrated circuit 4 scl4 6 12 b7 16 i/o st i2c4 synchronous serial clock input/output sda4 5 11 a8 15 i/o st i2c4 synchronous serial data input/output inter-integrated circuit 5 scl5 42 65 a44 91 i/o st i2c5 synchronous serial clock input/output sda5 41 64 b36 90 i/o st i2c5 synchronous serial data input/output legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select table 1-11: comparator 1, comparator 2 and cv ref pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp comparator voltage reference cv ref + 16 29 a20 40 i analog comparator voltage reference (high) input cv ref - 15 28 b15 39 i analog comparator voltage reference (low) input cv refout 23 34 b19 49 o analog comparator voltage reference output comparator 1 c1ina 11 20 b11 25 i analog comparator 1 positive input c1inb 12 21 a13 26 i analog comparator 1 selectable negative input c1inc 5 11 a8 15 i analog c1ind 4 10 b6 14 i analog c1out pps pps pps pps o comparator 1 output comparator 2 c2ina 13 22 a14 31 i analog comparator 2 positive input c2inb 14 23 a16 34 i analog comparator 2 selectable negative input c2inc 10 16 b9 21 i analog c2ind 6 12 b7 16 i analog c2out pps pps pps pps o comparator 2 output legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 28 ? 2015-2016 microchip technology inc. table 1-12: pmp pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp pma0 30 44 b24 30 i/o ttl/st parallel master port address bit 0 input (buffered slave modes) and output (master modes) pma1 29 43 a28 51 i/o ttl/st parallel master port address bit 1 input (buffered slave modes) and output (master modes) pma2 10 16 b9 21 o parallel master port address (demultiplexed master modes) pma3 6 12 b7 52 o pma4 5 11 a8 68 o pma5 4 2 b1 2 o pma6 16 6 b3 6 o pma7 22 33 a23 48 o pma8 42 65 a44 91 o pma9 41 64 b36 90 o pma10 21 32 b18 47 o pma11 27 41 a27 29 o pma12 24 7 a6 11 o pma13 23 34 b19 28 o pma14 45 61 a42 87 o pma15 43 68 b38 97 o pmcs1 45 61 a42 87 o parallel master port chip select 1 strobe pmcs2 43 68 b38 97 o parallel master port chip select 2 strobe pmd0 58 91 b52 135 i/o ttl/st parallel master port data (demultiplexed master mode) or address/data (multiplexed master modes) pmd1 61 94 a64 138 i/o ttl/st pmd2 62 98 a66 142 i/o ttl/st pmd3 63 99 b56 143 i/o ttl/st pmd4 64 100 a67 144 i/o ttl/st pmd5 1 3 a3 3 i/o ttl/st pmd6 2 4 b2 4 i/o ttl/st pmd7 3 5 a4 5 i/o ttl/st pmd8 88 b50 128 i/o ttl/st pmd9 87 a60 127 i/o ttl/st pmd10 86 b49 125 i/o ttl/st pmd11 85 a59 124 i/o ttl/st pmd12 79 b43 112 i/o ttl/st pmd13 80 a54 113 i/o ttl/st pmd14 77 b42 110 i/o ttl/st pmd15 78 a53 111 i/o ttl/st pmall 30 44 b24 30 o parallel master port address latch enable low byte (multiplexed master modes) pmalh 29 43 a28 51 o parallel master port address latch enable high byte (multiplexed master modes) pmrd 53 9 a7 13 o parallel master port read strobe pmwr 52 8 b5 12 o parallel master port write strobe legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
? 2015-2016 microchip technology inc. ds60001320d-page 29 pic32mz embedded connectivity with floating point unit (ef) family table 1-13: ebi pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp ebia0 44 b24 30 o external bus interface address bus ebia1 43 a28 51 o ebia2 16 b9 21 o ebia3 12 b7 52 o ebia4 11 a8 68 o ebia5 2 b1 2 o ebia6 6 b3 6 o ebia7 33 a23 48 o ebia8 65 a44 91 o ebia9 64 b36 90 o ebia10 32 b18 47 o ebia11 41 a27 29 o ebia12 7 a6 11 o ebia13 34 b19 28 o ebia14 61 a42 87 o ebia15 68 b38 97 o ebia16 17 a11 19 o ebia17 40 b22 53 o ebia18 39 a26 92 o ebia19 38 b21 93 o ebia20 94 o ebia21 126 o ebia22 117 o ebia23 103 o ebid0 91 b52 135 i/o st external bus interface data i/o bus ebid1 94 a64 138 i/o st ebid2 98 a66 142 i/o st ebid3 99 b56 143 i/o st ebid4 100 a67 144 i/o st ebid5 3 a3 3 i/o st ebid6 4 b2 4 i/o st ebid7 5 a4 5 i/o st ebid8 88 b50 128 i/o st ebid9 87 a60 127 i/o st ebid10 86 b49 125 i/o st ebid11 85 a59 124 i/o st ebid12 79 b43 112 i/o st ebid13 80 a54 113 i/o st ebid14 77 b42 110 i/o st ebid15 78 a53 111 i/o st ebibs0 9 o external bus interface byte select ebibs1 1 0o ebics0 59 a41 131 o external bus interface chip select ebics1 132 o ebics2 133 o ebics3 134 o legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 30 ? 2015-2016 microchip technology inc. ebioe 9 a7 13 o external bus interface output enable ebirdy1 60 b34 86 i st external bus interface ready input ebirdy2 58 a39 84 i st ebirdy3 57 b45 116 i st ebirp 45 o external bus interface flash reset pin ebiwe 8 b5 12 o external bus interface write enable table 1-13: ebi pinout i/o descriptions (continued) pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
? 2015-2016 microchip technology inc. ds60001320d-page 31 pic32mz embedded connectivity with floating point unit (ef) family table 1-14: usb pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp v bus 33 51 a35 73 i analog usb bus power monitor v usb 3 v 3 34 52 a36 74 p usb internal transceiver supply. if the usb module is not used, this pin must be connected to v ss . when connected, the shared pin functions on usbid will not be available. d+ 37 55 b30 77 i/o analog usb d+ d- 36 54 a37 76 i/o analog usb d- usbid 38 56 a38 78 i st usb otg id detect legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select table 1-15: can1 and can2 pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp c1tx pps pps pps pps o can1 bus transmit pin c1rx pps pps pps pps i st can1 bus receive pin c2tx pps pps pps pps o can2 bus transmit pin c2rx pps pps pps pps i st can2 bus receive pin legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 32 ? 2015-2016 microchip technology inc. table 1-16: ethernet mii i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp erxd0 61 41 b32 81 i st ethernet receive data 0 erxd1 58 42 b26 66 i st ethernet receive data 1 erxd2 57 43 a31 67 i st ethernet receive data 2 erxd3 56 44 a40 82 i st ethernet receive data 3 erxerr 64 35 a30 65 i st ethernet receive error input erxdv 62 12 b40 101 i st ethernet receive data valid erxclk 63 16 b12 27 i st ethernet receive clock etxd0 2 86 a5 7 o ethernet transmit data 0 etxd1 3 85 b4 8 o ethernet transmit data 1 etxd2 43 79 b17 43 o ethernet transmit data 2 etxd3 46 80 a22 44 o ethernet transmit data 3 etxerr 50 87 b44 114 o ethernet transmit error etxen 1 77 a57 120 o ethernet transmit enable etxclk 51 78 b47 121 i st ethernet transmit clock ecol 44 10 b33 83 i st ethernet collision detect ecrs 45 11 a47 100 i st ethernet carrier sense emdc 30 70 b39 99 o ethernet management data clock emdio 49 71 a55 115 i/o ethernet management data legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select table 1-17: ethernet rmii pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp ethernet mii interface erxd0 61 41 b32 81 i st ethernet receive data 0 erxd1 58 42 b26 66 i st ethernet receive data 1 erxerr 64 35 a30 65 i st ethernet receive error input etxd0 2 86 a5 7 o ethernet transmit data 0 etxd1 3 85 b4 8 o ethernet transmit data 1 etxen 1 77 a57 120 o ethernet transmit enable emdc 30 70 b39 99 o ethernet management data clock emdio 49 71 a55 115 i/o ethernet management data erefclk 63 16 b12 27 i st ethernet reference clock ecrsdv 62 12 b40 101 i st ethernet carrier sense data valid legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
? 2015-2016 microchip technology inc. ds60001320d-page 33 pic32mz embedded connectivity with floating point unit (ef) family table 1-18: alternate ethernet mii pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp aerxd0 18 i st alternate ethernet receive data 0 aerxd1 19 i st alternate ethernet receive data 1 aerxd2 28 i st alternate ethernet receive data 2 aerxd3 29 i st alternate ethernet receive data 3 aerxerr 1 i st alternate ethernet receive error input aerxdv 12 i st alternate ethernet receive data valid aerxclk 16 i st alternate ethernet receive clock aetxd0 47 o alternate ethernet transmit data 0 aetxd1 48 o alternate ethernet transmit data 1 aetxd2 44 o alternate ethernet transmit data 2 aetxd3 43 o alternate ethernet transmit data 3 aetxerr 35 o alternate ethernet transmit error aecol 42 i st alternate ethernet collision detect aecrs 41 i st alternate ethernet carrier sense aetxclk 66 i st alternate ethernet transmit clock aemdc 70 o alternate ethernet management data clock aemdio 71 i/o alternate ethernet management data aetxen 67 o alternate ethernet transmit enable legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select table 1-19: alternate ethernet rmii pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp aerxd0 43 18 i st alternate ethernet receive data 0 aerxd1 46 19 i st alternate ethernet receive data 1 aerxerr 51 1 i st alternate ethernet receive error input aetxd0 57 47 o alternate ethernet transmit data 0 aetxd1 56 48 o alternate ethernet transmit data 1 aemdc 30 70 o alternate ethernet management data clock aemdio 49 71 i/o alternate ethernet management data aetxen 50 67 o alternate ethernet transmit enable aerefclk 45 16 i st alternate ethernet reference clock aecrsdv 62 12 i st alternate ethernet carrier sense data valid legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 34 ? 2015-2016 microchip technology inc. table 1-20: sqi1 pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp sqiclk 57 89 a61 129 o serial quad interface clock sqics0 52 81 a56 118 o serial quad interface chip select 0 sqics1 53 82 b46 119 o serial quad interface chip select 1 sqid0 58 97 b55 141 i/o st serial quad interface data 0 sqid1 61 96 a65 140 i/o st serial quad interface data 1 sqid2 62 95 b54 139 i/o st serial quad interface data 2 sqid3 63 90 b51 130 i/o st serial quad interface data 3 legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select table 1-21: power, ground, and voltage reference pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp power and ground av dd 19 30 b16 41 p p positive supply for analog modules. this pin must be connected at all times. av ss 20 31 a21 42 p p ground reference for analog modules. this pin must be connected at all times v dd 8, 26, 39, 54, 60 14, 37, 46, 62, 74, 83, 93 b8, a15, a25, b25, b35, a50, a58, b53 18, 33, 55, 64, 88, 107, 122, 137 p positive supply for peripheral logic and i/o pins. this pin must be connected at all times. v ss 7, 25, 35, 40, 55, 59 13, 36, 45, 53, 63, 75, 84, 92 a9, b13, b20, b29, a29, a43, a51, b48, a63 17, 32, 54, 63, 75, 89, 108, 123, 136 p ground reference for logic, i/o pins, and usb. this pin must be connected at all times. voltage reference v ref + 16 29 a20 40 i analog analog voltage reference (high) input v ref - 15 28 b15 39 i analog analog voltage reference (low) input legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
? 2015-2016 microchip technology inc. ds60001320d-page 35 pic32mz embedded connectivity with floating point unit (ef) family table 1-22: jtag, trace, and programming /debugging pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla 144-pin tqfp/ lqfp jtag tck 27 38 b21 56 i st jtag test clock input pin tdi 28 39 a26 57 i st jtag test data input pin tdo 24 40 b22 58 o jtag test data output pin tms 23 17 a11 22 i st jtag test mode select pin trace trclk 57 89 a61 129 o trace clock trd0 58 97 b55 141 o trace data bits 0-3 trd1 61 96 a65 140 o trd2 62 95 b54 139 o trd3 63 90 b51 130 o programming/debugging pged1 16 25 a18 36 i/o st data i/o pin for programming/debugging communication channel 1 pgec1 15 24 a17 35 i st clock input pin for programming/debugging communication channel 1 pged2 18 27 a19 38 i/o st data i/o pin for programming/debugging communication channel 2 pgec2 17 26 b14 37 i st clock input pin for programming/debugging communication channel 2 mclr 9 15 a10 20 i/p st master clear (reset) input. this pin is an active-low reset to the device. legend: cmos = cmos-compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = transistor-transistor logic input buffer pps = peripheral pin select
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 36 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 37 pic32mz embedded connectivity with floating point unit (ef) family 2.0 guidelines for getting started with 32-bit microcontrollers 2.1 basic connection requirements getting started with the pic32mz ef family of 32-bit microcontrollers (mcus) requires attention to a minimal set of device pin connections before proceeding with development. the following is a list of pin names, which must always be connected: all v dd and v ss pins (see 2.2 decoupling capacitors ) all av dd and av ss pins, even if the adc module is not used (see 2.2 decoupling capacitors ) mclr pin (see 2.3 master clear (mclr) pin ) pgecx/pgedx pins, used for in-circuit serial programming? (icsp?) and debugging pur - poses (see 2.4 icsp pins ) osc1 and osc2 pins, when external oscillator source is used (see 2.7 external oscillator pins ) the following pin(s) may be required as well: v ref +/v ref - pins, used when external voltage reference for the adc module is implemented . 2.2 decoupling capacitors the use of decoupling capacitors on power supply pins, such as v dd , v ss , av dd and av ss is required. see figure 2-1 . consider the following criteria when using decoupling capacitors: value and type of capacitor: a value of 0.1 f (100 nf), 10-20v is recommended. the capacitor should be a low equivalent series resistance (low- esr) capacitor and have resonance frequency in the range of 20 mhz and higher. it is further recommended that ceramic capacitors be used. placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended that the capacitors be placed on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. handling high frequency noise: if the board is experiencing high frequency noise, upward of tens of mhz, add a second ceramic-type capacitor in par - allel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 f to 0.001 f. place this second capacitor next to the primary decoupling capacitor. in high-speed circuit designs, consider implement - ing a decade pair of capacitances as close to the power and ground pins as possible. for example, 0.1 f in parallel with 0.001 f. maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decou - pling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing pcb track inductance. note 1: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). note: the av dd and av ss pins must be connected, regardless of adc use and the adc voltage reference source.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 38 ? 2015-2016 microchip technology inc. figure 2-1: recommended minimum connection 2.2.1 bulk capacitors the use of a bulk capacitor is recommended to improve power supply stability. typical values range from 4.7 f to 47 f. this capacitor should be located as close to the device as possible. 2.3 master clear ( mclr ) pin the mclr pin provides for two specific device functions: device reset device programming and debugging pulling the mclr pin low generates either a device reset or a por, depending on the setting of the smclr bit (devcfg0<15>). figure 2-2 illustrates a typical mclr circuit. during device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adversely affected. therefore, specific values of r and c will need to be adjusted based on the application and pcb requirements. for example, as illustrated in figure 2-2 , it is recommended that the capacitor c be isolated from the mclr pin during programming and debugging operations. place the components illustrated in figure 2-2 within one-quarter inch (6 mm) from the mclr pin. figure 2-2: example of mclr pin connections pic32 v dd v ss v dd v ss v dd v dd av dd av ss v dd v ss 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic c r v dd mclr 0.1 f ceramic l1 (2) r1 note 1: if the usb module is not used, this pin must be connected to v ss . 2: as an option, instead of a hard-wired connection, an inductor (l1) can be substituted between v dd and av dd to improve adc noise rejection. the inductor impedance should be less than 1 ? and the inductor capacity greater than 10 ma. ? ? where: f f cnv 2 ------------- - = f 1 2 ? lc ?? ----------------------- = l 1 2 ? fc ?? --------------------- - ?? ?? 2 = (i.e., adc conversion rate/2) connect (2) v usb 3 v 3 (1) v dd v ss v ss v dd v dd v ss v ss v ss note 1: 470 ? ?? r1 ? 1k ? will limit any current flowing into mclr from the external capacitor c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met without interfering with the debug/programmer tools. 2: the capacitor can be sized to prevent unintentional resets from brief glitches or to extend the device reset period during por. 3: no pull-ups or bypass capacitors are allowed on active debug/program pgecx/pgedx pins. r1 (1) 10k v dd mclr pic32 1 k ? 0.1 f (2) pgecx (3) pgedx (3) icsp? 15 4 2 3 6 v dd v ss nc r c
? 2015-2016 microchip technology inc. ds60001320d-page 39 pic32mz embedded connectivity with floating point unit (ef) family 2.4 icsp pins the pgecx and pgedx pins are used for icsp and debugging purposes. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the pgecx and pgedx pins are not recommended as they will interfere with the programmer/debugger communi - cations to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to the ac/dc characteristics and timing requirements information in the respective device flash programming specification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. ensure that the communication channel select (i.e., pgecx/pgedx pins) programmed into the device matches the physical connections for the icsp to mplab ? icd 3 or mplab real ice?. for more information on icd 3 and real ice connection requirements, refer to the following documents that are available from the microchip web site. ?using mplab ? icd 3? (poster) (ds50001765) ?mplab ? icd 3 design advisory? (ds50001764) ?mplab ? real ice? in-circuit debugger user?s guide? ( ds50001616) ?using mplab ? real ice? emulator? (poster) (ds50001749) 2.5 jtag the tms, tdo, tdi and tck pins are used for testing and debugging according to the joint test action group (jtag) standard. it is recommended to keep the trace length between the jtag connector and the jtag pins on the device as short as possible. if the jtag connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the tms, tdo, tdi and tck pins are not recommended as they will interfere with the programmer/debugger communications to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to the ac/dc characteristics and timing requirements information in the respective device flash programming specification for information on capacitive loading limits and pin input voltage high (v ih ) and input voltage low (v il ) requirements. 2.6 trace the trace pins can be connected to a hardware trace-enabled programmer to provide a compressed real-time instruction trace. when used for trace, the trd3, trd2, trd1, trd0 and trclk pins should be dedicated for this use. the trace hardware requires a 22 ohm series resistor between the trace pins and the trace connector. 2.7 external oscillator pins many mcus have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to section 8.0 oscillator configuration for details). the oscillator circuit should be placed on the same side of the board as the device. also, place the oscillator cir - cuit close to the respective oscillator pins, not exceed - ing one-half inch (12 mm) distance between them. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or power traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. a suggested layout is illustrated in figure 2-3 . figure 2-3: suggested oscillator circuit placement 2.8 unused i/os unused i/o pins should not be allowed to float as inputs. they can be configured as outputs and driven to a logic-low state. alternatively, inputs can be reserved by connecting the pin to v ss through a 1k to 10k resistor and configuring the pin as an input. main oscillator guard ring guard trace secondary oscillator
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 40 ? 2015-2016 microchip technology inc. 2.9 designing for high-speed peripherals the pic32mz ef family devices have peripherals that operate at frequencies much higher than typical for an embedded environment. ta b l e 2-1 lists the peripherals that produce high-speed signals on their external pins: table 2-1: peripherals that produce hs signals on external pins due to these high-speed signals, it is important to consider several factors when designing a product that uses these peripherals, as well as the pcb on which these components will be placed. adhering to these recommendations will help achieve the following goals: minimize the effects of electromagnetic interference to the proper operation of the product ensure signals arrive at their intended destination at the same time minimize crosstalk maintain signal integrity reduce system noise minimize ground bounce and power sag 2.9.1 system design 2.9.1.1 impedance matching when selecting parts to place on high-speed buses, particularly the sqi bus, if the impedance of the periph - eral device does not match the impedance of the pins on the pic32mz ef device to which it is connected, signal reflections could result, thereby degrading the quality of the signal. if it is not possible to select a product that matches impedance, place a series resistor at the load to create the matching impedance. see figure 2-4 for an example. figure 2-4: series resistor 2.9.1.2 pcb layout recommendations the following list contains recommendations that will help ensure the pcb layout will promote the goals previously listed. component placement - place bypass capacitors as close to their component power and ground pins as possible, and place them on the same side of the pcb - devices on the same bus that have larger setup times should be placed closer to the pic32mz ef device power and ground - multi-layer pcbs will allow separate power and ground planes - each ground pin should be connected to the ground plane individually - place bypass capacitor vias as close to the pad as possible (preferably inside the pad) - if power and ground planes are not used, maximize width for power and ground traces - use low-esr, surface-mount bypass capacitors clocks and oscillators - place crystals as close as possible to the pic32mz ef device osc/sosc pins - do not route high-speed signals near the clock or oscillator - avoid via usage and branches in clock lines (sqiclk) - place termination resistors at the end of clock lines traces - higher-priority signals should have the shortest traces - match trace lengths for parallel buses (ebiax, ebidx, sqidx) - avoid long run lengths on parallel traces to reduce coupling - make the clock traces as straight as possible - use rounded turns rather than right-angle turns - have traces on different layers intersect on right angles to minimize crosstalk - maximize the distance between traces, preferably no less than three times the trace width - power traces should be as short and as wide as possible - high-speed traces should be placed close to the ground plane peripheral high-speed signal pins maximum speed on signal pin ebi ebiax, ebidx 50 mhz sqi1 sqiclk, sqicsx , sqidx 50 mhz hs usb d+, d- 480 mhz pic32mz sqi flash device 50 ?
? 2015-2016 microchip technology inc. ds60001320d-page 41 pic32mz embedded connectivity with floating point unit (ef) family 2.9.1.3 emi/emc/eft (iec 61000-4-4 and iec 61000-4-2) suppression considerations the use of ldo regulators is preferred to reduce overall system noise and provide a cleaner power source. however, when utilizing switching buck/boost regulators as the local power source for pic32mz ef devices, as well as in electrically noisy environments or test conditions required for iec 61000-4-4 and iec 61000-4-2, users should evaluate the use of t-filters (i.e., l-c-l) on the power pins, as shown in figure 2-5 . in addition to a more stable power source, use of this type of t-filter can greatly reduce susceptibility to emi sources and events. figure 2-5: emi/emc/eft suppression circuit v ss v dd v ss v usb3v3 v ss v dd v ss v dd v dd v ss v ss v dd v ss v dd v ss v dd av dd av ss ferrite chips 0.01 f 0.01 f v dd v dd 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f ferrite chips ferrite chip smd dcr = 0.15 (max) 600 ma isat 300 @ 100 mhz pn#: 0.1 f pic32mz
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 42 ? 2015-2016 microchip technology inc. 2.10 typical application connection examples examples of typical application connections are shown in figure 2-6 and figure 2-7 . figure 2-6: audio playback application figure 2-7: low-cost co ntrollerless (lcc) graphi cs application with projected capacitive touch audio codec display pmp i 2 s spi usb usb pmd<7:0> 33 stereo headphones speaker pic32 host pmwr mmc sd 3 sdi refclko lcd display pic32 sram microchip microchip dma ebi adc projected capacitive touch overlay gfx library external frame buffer anx library mtouch? refresh render
? 2015-2016 microchip technology inc. ds60001320d-page 43 pic32mz embedded connectivity with floating point unit (ef) family 3.0 cpu the mips32 ? m-class core is the heart of the pic32mz ef family device processor. the cpu fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. key features include: 5-stage pipeline 32-bit address and data paths mips32 enhanced architecture (release 5): - multiply-accumulate and multiply-subtract instructions - targeted multiply instruction - zero/one detect instructions - wait instruction - conditional move instructions ( movn , movz ) - vectored interrupts - programmable exception vector base - atomic interrupt enable/disable - gpr shadow registers to minimize latency for interrupt handlers - bit field manipulation instructions - virtual memory support micromips? compatible instruction set: - improves code size density over mips32, while maintaining mips32 performance. - supports all mips32 instructions (except branch- likely instructions) - fifteen additional 32-bit instructions and 39 16-bit instructions corresponding to commonly-used mips32 instructions - stack pointer implicit in instruction - mips32 assembly and abi compatible mmu with translation lookaside buffer (tlb) mechanism: - 16 dual-entry fully associative joint tlb - 4-entry fully associative instruction and data tlb - 4 kb pages separate l1 data and instruction caches: - 16 kb 4-way instruction cache (i-cache) - 4 kb 4-way data cache (d-cache) autonomous multiply/divide unit (mdu): - maximum issue rate of one 32x32 multiply per clock - early-in iterative divide. minimum 12 and maximum 38 clock latency (dividend ( rs ) sign extension-dependent) power control: - minimum frequency: 0 mhz - low-power mode (triggered by wait instruction) - extensive use of local gated clocks ejtag debug and instruction trace: - support for single stepping - virtual instruction and data address/value breakpoints - hardware breakpoint supports both address match and address range triggering. - eight instruction and four data complex breakpoints iflowtrace ? version 2.0 support: - real-time instruction program counter - special events trace capability - two performance counters with 34 user- selectable countable events - disabled if the processor enters debug mode - program counter sampling four watch registers: - instruction, data read, data write options - address match masking options dsp ase extension: - native fractional format data type operations - register single instruction multiple data (simd) operations (add, subtract, multiply, shift) - gpr-based shift - bit manipulation - compare-pick - dsp control access - indexed-load -branch - multiplication of complex operands - variable bit insertion and extraction - virtual circular buffers - arithmetic saturation and overflow handling - zero-cycle overhead saturation and rounding operations floating point unit (fpu): - 1985 ieee-754 compliant floating point unit - supports single and double precision datatypes - 2008 ieee-754 compatibility control of nan handling and abs/neg instructions - runs at 1:1 core/fpu clock ratio note 1: this data sheet summarizes the fea - tures of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 50. cpu for devices with mips32 ? microaptiv? and m-class cores (ds60001192) of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: the series 5 warrior m-class cpu core resources are available at: www.imgtec.com .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 44 ? 2015-2016 microchip technology inc. a block diagram of the pic32mz ef family processor core is shown in figure 3-1 . figure 3-1: pic32mz ef family microprocessor core block diagram system bus execution unit alu/shift atomic/ldst dsp ase system coprocessor enhanced mdu (with dsp ase) gpr (8 sets) debug/profiling break points iflowtrace ? fast debug channel performance counters sampling secure debug micromips? i-cache controller mmu (tlb) d-cache controller power m-class microprocessor core system interface interrupt interface i-cache d-cache biu decode (mips32 ? /micromips?) ejtag 2-wire debug management pbclk7 fpu (single & double)
? 2015-2016 microchip technology inc. ds60001320d-page 45 pic32mz embedded connectivity with floating point unit (ef) family 3.1 architecture overview the mips32 m-class microprocessor core in pic32mz ef family devices contains several logic blocks working together in parallel, providing an efficient high-perfor - mance computing engine. the following blocks are included with the core: execution unit general purpose register (gpr) multiply/divide unit (mdu) system control coprocessor (cp0) floating point unit (fpu) memory management unit (mmu) instruction/data cache controllers power management instructions and data caches micromips support enhanced jtag (ejtag) controller 3.1.1 execution unit the processor core execution unit implements a load/ store architecture with single-cycle alu operations (logical, shift, add, subtract) and an autonomous multi - ply/divide unit. the core contains thirty-two 32-bit gen - eral purpose registers (gprs) used for integer operations and address calculation. seven additional register file shadow sets (containing thirty-two regis - ters) are added to minimize context switching overhead during interrupt/exception processing. the register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. the execution unit includes: 32-bit adder used for calculating the data address address unit for calculating the next instruction address logic for branch determination and branch target address calculation load aligner trap condition comparator bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results leading zero/one detect unit for implementing the clz and clo instructions arithmetic logic unit (alu) for performing arithmetic and bitwise logical operations shifter and store aligner dsp alu and logic block for performing dsp instructions, such as arithmetic/shift/compare operations 3.1.2 multiply/divide unit (mdu) the processor core includes a multiply/divide unit (mdu) that contains a separate pipeline for multiply and divide operations, and dsp ase multiply instruc - tions. this pipeline operates in parallel with the integer unit (iu) pipeline and does not stall when the iu pipe - line stalls. this allows mdu operations to be partially masked by system stalls and/or other integer unit instructions. the high-performance mdu consists of a 32x32 booth recoded multiplier, four pairs of result/accumulation registers (hi and lo), a divide state machine, and the necessary multiplexers and control logic. the first num - ber shown (32 of 32x32) represents the rs operand. the second number (32 of 32x32) represents the rt operand. the mdu supports execution of one multiply or multiply-accumulate operation every clock cycle. divide operations are implemented with a simple 1-bit- per-clock iterative algorithm. an early-in detection checks the sign extension of the dividend ( rs ) oper - and. if rs is 8 bits wide, 23 iterations are skipped. for a 16-bit wide rs , 15 iterations are skipped and for a 24-bit wide rs , 7 iterations are skipped. any attempt to issue a subsequent mdu instruction while a divide is still active causes an iu pipeline stall until the divide operation has completed. table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (num - ber of cycles until a result is available) for the processor core multiply and divide instructions. the approximate latency and repeat rates are listed in terms of pipeline clocks. table 3-1: mips32 ? m-class microprocessor co re high-perfo rmance integer multiply/divide unit latencies and repeat rates opcode operand size (mul rt ) (div rs ) latency repeat rate mult/multu, madd/maddu, msub/msubu (hi/lo destination) 16 bits 5 1 32 bits 5 1 mul (gpr destination) 16 bits 5 1 32 bits 5 1 div/divu 8 bits 12/14 12/14 16 bits 20/22 20/22 24 bits 28/30 28/30 32 bits 36/38 36/38
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 46 ? 2015-2016 microchip technology inc. the mips architecture defines that the result of a multiply or divide operation be placed in one of four pairs of hi and lo registers. using the move-from-hi ( mfhi ) and move-from-lo ( mflo ) instructions, these values can be transferred to the general purpose register file. in addition to the hi/lo targeted operations, the mips32 architecture also defines a multiply instruc - tion, mul , which places the least significant results in the primary register file instead of the hi/lo register pair. by avoiding the explicit mflo instruction required when using the lo register, and by support - ing multiple destination registers, the throughput of multiply-intensive operations is increased. two other instructions, multiply-add ( madd ) and multiply-subtract ( msub ), are used to perform the multiply-accumulate and multiply-subtract operations. the madd instruction multiplies two numbers and then adds the product to the current contents of the hi and lo registers. similarly, the msub instruction multiplies two operands and then subtracts the product from the hi and lo registers. the madd and msub operations are commonly used in dsp algorithms. the mdu also implements various shift instructions operating on the hi/lo register and multiply instruc - tions as defined in the dsp ase. the mdu supports all of the data types required for this purpose and includes three extra hi/lo registers as defined by the ase. table 3-2 lists the latencies and repeat rates for the dsp multiply and dot-product operations. the approxi - mate latencies and repeat rates are listed in terms of pipeline clocks. table 3-2: dsp-related latencies and repeat rates 3.1.3 system control ? coprocessor (cp0) in the mips architecture, cp0 is responsible for the virtual-to-physical address translation and cache proto - cols, the exception control system, the processors diagnostics capability, the operating modes (kernel, user and debug) and whether interrupts are enabled or disabled. configuration information, such as cache size and set associativity, and the presence of options like micromips is also available by accessing the cp0 registers, listed in tab l e 3-3 . op code latency repeat rate multiply and dot-product without saturation after accumulation 5 1 multiply and dot-product with saturation after accumulation 5 1 multiply without accumulation 5 1 table 3-3: coprocessor 0 registers register number register name function 0 index index into the tlb array (mpu only). 1 random randomly generated index into the tlb array (mpu only). 2 entrylo0 low-order portion of the tlb entry for even-numbered virtual pages (mpu only). 3 entrylo1 low-order portion of the tlb entry for odd-numbered virtual pages (mpu only). 4 context/ ? userlocal pointer to the page table entry in memory (mpu only). user information that can be written by privileged software and read via the rdhwr instruction. 5 pagemask/ ? pagegrain pagemask controls the variable page sizes in tlb entries. pagegrain enables support of 1 kb pages in the tlb (mpu only). 6 wired controls the number of fixed (i.e., wired) tlb entries (mpu only). 7 hwrena enables access via the rdhwr instruction to selected hardware registers in ? non-privileged mode. 8 badvaddr reports the address for the most recent address-related exception. badinstr reports the instruction that caused the most recent exception. badinstrp reports the branch instruction if a delay slot caused the most recent exception. 9 count processor cycle count. 10 entryhi high-order portion of the tlb entry (mpu only). 11 compare core timer interrupt control.
? 2015-2016 microchip technology inc. ds60001320d-page 47 pic32mz embedded connectivity with floating point unit (ef) family 12 status processor status and control. intctl interrupt control of vector spacing. srsctl shadow register set control. srsmap shadow register mapping control. view_ipl allows the priority level to be read/written without extracting or inserting that bit from/to the status register. srsmap2 contains two 4-bit fields that provide the mapping from a vector number to the shadow set number to use when servicing such an interrupt. 13 cause describes the cause of the last exception. nestedexc contains the error and exception level status bit values that existed prior to the current exception. view_ripl enables read access to the ripl bit that is available in the cause register. 14 epc program counter at last exception. nestedepc contains the exception program counter that existed prior to the current exception. 15 prid processor identification and revision ebase exception base address of exception vectors. cdmmbase common device memory map base. 16 config configuration register. config1 configuration register 1. config2 configuration register 2. config3 configuration register 3. config4 configuration register 4. config5 configuration register 5. config7 configuration register 7. 17 lladdr load link address (mpu only). 18 watchlo low-order watchpoint address (mpu only). 19 watchhi high-order watchpoint address (mpu only). 20-22 reserved reserved in the pic32 core. 23 debug ejtag debug register. tracecontrol ejtag trace control. tracecontrol2 ejtag trace control 2. usertracedata1 ejtag user trace data 1 register. tracebpc ejtag trace breakpoint register. debug2 debug control/exception status 1. 24 depc program counter at last debug exception. usertracedata2 ejtag user trace data 2 register. 25 perfctl0 performance counter 0 control. perfcnt0 performance counter 0. perfctl1 performance counter 1 control. perfcnt1 performance counter 1. 26 errctl software test enable of way-select and data ram arrays for i-cache and d-cache (mpu only). 27 reserved reserved in the pic32 core. 28 taglo/datalo low-order portion of cache tag interface (mpu only). 29 reserved reserved in the pic32 core. 30 errorepc program counter at last error exception. 31 desave debug exception save. table 3-3: coprocessor 0 registers (continued) register number register name function
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 48 ? 2015-2016 microchip technology inc. 3.1.4 floating point unit (fpu) the floating point unit (fpu), coprocessor (cp1), implements the mips instruction set architecture for floating point computation. the implementation sup - ports the ansi/ieee standard 754 (ieee for binary floating point arithmetic) for 32-bit and 64-bit floating point data formats. the fpu can be programmed to have thirty-two 32-bit or 64-bit floating point registers used for floating point operations. the performance is optimized for 32-bit formats. most instructions have one fpu cycle throughput and four fpu cycle latency. the fpu implements the multiply- add (madd) and multiply-sub (msub) instructions with intermediate rounding after the multiply function. the result is guaranteed to be the same as executing a mul and an add instruction separately, but the instruction latency, instruction fetch, dispatch band - width, and the total number of register accesses are improved. ieee denormalized input operands and results are supported by hardware for some instructions. ieee denormalized results are not supported by hardware in general, but a fast flush-to-zero mode is provided to optimize performance. the fast flush-to-zero mode is enabled through the fccr register, and use of this mode is recommended for best performance when denormalized results are generated. the fpu has a separate pipeline for floating point instruction execution. this pipeline operates in parallel with the integer core pipeline and does not stall when the integer pipeline stalls. this allows long-running fpu operations, such as divide or square root, to be partially masked by system stalls and/or other integer unit instructions. arithmetic instructions are always dispatched and completed in order, but loads and stores can complete out of order. the exception model is precise at all times. table 3-4 contains the floating point instruction laten - cies and repeat rates for the processor core. in this table, 'latency' refers to the number of fpu cycles nec - essary for the first instruction to produce the result needed by the second instruction. the repeat rate refers to the maximum rate at which an instruction can be executed per fpu cycle. table 3-4: fpu instruction latencies and repeat rates op code latency (fpu cycles) repeat rate (fpu cycles) abs.[s,d], neg.[s,d], add.[s,d], sub.[s,d], c.cond.[s,d], mul.s 4 1 madd.s, msub.s, nmadd.s, nmsub.s, cabs.cond.[s,d] 4 1 cvt.d.s, cvt.ps.pw, cvt.[s,d].[w,l] 4 1 cvt.s.d, cvt.[w,l].[s,d], ceil.[w,l].[s,d], floor.[w,l].[s,d], round.[w,l].[s,d], trunc.[w,l].[s,d] 4 1 mov.[s,d], movf.[s,d], movn.[s,d], movt.[s,d], movz.[s,d] 4 1 mul.d 5 2 madd.d, msub.d, nmadd.d, nmsub.d 5 2 recip.s 13 10 recip.d 26 21 rsqrt.s 17 14 rsqrt.d 36 31 div.s, sqrt.s 17 14 div.d, sqrt.d 32 29 mtc1, dmtc1, lwc1, ldc1, ldxc1, luxc1, lwxc1 4 1 mfc1, dmfc1, swc1, sdc1, sdxc1, suxc1, swxc1 1 1 legend: s = single (32-bit) d = double (64-bit) ? w = word (32-bit) l = long word (64-bit)
? 2015-2016 microchip technology inc. ds60001320d-page 49 pic32mz embedded connectivity with floating point unit (ef) family the fpu implements a high-performance 7-stage pipeline: decode, register read and unpack (fr stage) multiply tree, double pumped for double (m1 stage) multiply complete (m2 stage) addition first step (a1 stage) addition second and final step (a2 stage) packing to ieee format (fp stage) register writeback (fw stage) the fpu implements a bypass mechanism that allows the result of an operation to be forwarded directly to the instruction that needs it without having to write the result to the fpu register and then read it back. table 3-5 lists the coprocessor 1 registers for the fpu. table 3-5: fpu (cp1) registers 3.2 power management the processor core offers a number of power manage - ment features, including low-power design, active power management and power-down modes of operation. the core is a static design that supports slowing or halting the clocks, which reduces system power consumption during idle periods. 3.2.1 instructio n-controlled power management the mechanism for invoking power-down mode is through execution of the wait instruction. for more information on power management, see section 33.0 power-saving features . 3.2.2 local clock gating the majority of the power consumed by the processor core is in the clock tree and clocking registers. the pic32mz family makes extensive use of local gated- clocks to reduce this dynamic power consumption. 3.3 l1 instruction and data caches 3.3.1 instruction cache (i-cache) the i-cache is an on-core memory block of 16 kbytes. because the i-cache is virtually indexed, the virtual-to- physical address translation occurs in parallel with the cache access rather than having to wait for the physical address translation. the tag holds 22 bits of physical address, a valid bit, and a lock bit. the lru replacement bits are stored in a separate array. the i-cache block also contains and manages the instruction line fill buffer. besides accumulating data to be written to the cache, instruction fetches that refer - ence data in the line fill buffer are serviced either by a bypass of that data, or data coming from the external interface. the i-cache control logic controls the bypass function. the processor core supports i-cache locking. cache locking allows critical code or data segments to be locked into the cache on a per-line basis, enabling the system programmer to maximize the efficiency of the system cache. the cache locking function is always available on all i-cache entries. entries can then be marked as locked or unlocked on a per entry basis using the cache instruction. 3.3.2 data cache (d-cache) the d-cache is an on-core memory block of 4 kbytes. this virtually indexed, physically tagged cache is pro - tected. because the d-cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access. the tag holds 22 bits of physical address, a valid bit, and a lock bit. there is an addi - tional array holding dirty bits and lru replacement algorithm bits for each set of the cache. in addition to i-cache locking, the processor core also supports a d-cache locking mechanism identical to the i-cache. critical data segments are locked into the cache on a per-line basis. the locked contents can be updated on a store hit, but cannot be selected for replacement on a cache miss. the d-cache locking function is always available on all d-cache entries. entries can then be marked as locked or unlocked on a per-entry basis using the cache instruction. 3.3.3 attributes the processor core i-cache and d-cache attributes are listed in the configuration registers (see register 3-1 through register 3-4 ). register number register name function 0 fir floating point implementation register. contains information that identifies the fpu. 25 fccr floating point condition codes register. 26 fexr floating point exceptions register. 28 fenr floating point enables register. 31 fcsr floating point control and status register.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 50 ? 2015-2016 microchip technology inc. 3.4 ejtag debug support the processor core provides for an enhanced jtag (ejtag) interface for use in the software debug of application and kernel code. in addition to standard user mode and kernel modes of operation, the proces - sor core provides a debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a debug exception return ( deret ) instruction is executed. during this time, the processor executes the debug exception handler routine. the ejtag interface operates through the test access port (tap), a serial communication port used for trans - ferring test data in and out of the core. in addition to the standard jtag instructions, special instructions defined in the ejtag specification specify which registers are selected and how they are used. 3.5 mips dsp ase extension the mips dsp application-specific extension revision 2 is an extension to the mips32 architecture. this extension comprises new integer instructions and states that include new hi/lo accumulator register pairs and a dsp control register. this extension is crucial in a wide range of dsp, multimedia, and dsp- like algorithms covering audio and video processing applications. the extension supports native fractional format data type operations, register single instruction multiple data (simd) operations, such as add, subtract, multiply, and shift. in addition, the extension includes the following features that are essential in making dsp algorithms computationally efficient: support for multiplication of complex operands variable bit insertion and extraction implementation and use of virtual circular buffers arithmetic saturation and overflow handling support zero cycle overhead saturation and rounding operations 3.6 micromips isa the processor core supports the micromips isa, which contains all mips32 isa instructions (except for branch-likely instructions) in a new 32-bit encoding scheme, with some of the commonly used instructions also available in 16-bit encoded format. this isa improves code density through the additional 16-bit instructions while maintaining a performance similar to mips32 mode. in micromips mode, 16-bit or 32-bit instructions will be fetched and recoded to legacy mips32 instruction opcodes in the pipelines i stage, so that the processor core can have the same microaptiv up microarchitecture. because the micromips instruc - tion stream can be intermixed with 16-bit halfword or 32-bit word size instructions on halfword or word boundaries, additional logic is in place to address the word misalignment issues, thus minimizing performance loss.
? 2015-2016 microchip technology inc. ds60001320d-page 51 pic32mz embedded connectivity with floating point unit (ef) family 3.7 m-class core configuration register 3-1 through register 3-4 show the default configuration of the m-class core, which is included on the pic32mz ef family of devices. register 3-1: config: co nfiguration register; cp0 register 16, select 0 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 u-0 u-0 u-0 u-0 u-0 u-0 r-0 i s p 23:16 r-0 r-0 r-1 r-0 u-0 r-1 r-0 r-0 dsp udi sb mdu mm<1:0> bm 15:8 r-0 r-0 r-0 r-0 r-0 r-1 r-0 r-0 be at<1:0> ar<2:0> mt<2:1> 7:0 r-1 u-0 u-0 u-0 u-0 r/w-0 r/w-1 r/w-0 mt<0> k0<2:0> legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 reserved: this bit is hardwired to 1 to indicate the presence of the config1 register. bit 30-25 unimplemented: read as 0 bit 24 isp: instruction scratch pad ram bit 0 = instruction scratch pad ram is not implemented bit 23 dsp: data scratch pad ram bit 0 = data scratch pad ram is not implemented bit 22 udi: user-defined bit 0 = corextend user-defined instructions are not implemented bit 21 sb: simplebe bit 1 = only simple byte enables are allowed on the internal bus interface bit 20 mdu: multiply/divide unit bit 0 = fast, high-performance mdu bit 19 unimplemented: read as 0 bit 18-17 mm<1:0>: merge mode bits 10 = merging is allowed bit 16 bm: burst mode bit 0 = burst order is sequential bit 15 be: endian mode bit 0 = little-endian bit 14-13 at<1:0>: architecture type bits 00 = mips32 bit 12-10 ar<2:0>: architecture revision level bits 001 = mips32 release 2 bit 9-7 mt<2:0>: mmu type bits 001 = m-class mpu microprocessor core uses a tlb-based mmu bit 6-3 unimplemented: read as 0 bit 2-0 k0<2:0>: kseg0 coherency algorithm bits 011 = cacheable, non-coherent, write-back, write allocate 010 = uncached 001 = cacheable, non-coherent, write-through, write allocate 000 = cacheable, non-coherent, write-through, no write allocate all other values are not used and mapped to other values. 100 , 101 , and 110 are mapped to 010 . 111 is mapped to 010.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 52 ? 2015-2016 microchip technology inc. register 3-2: config 1: configuration register 1; cp0 register 16, select 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 r-0 r-0 r-1 r-1 r-1 r-1 r-0 mmu size<5:0> is<2> 23:16 r-1 r-0 r-0 r-1 r-1 r-0 r-1 r-1 is<1:0> il<2:0> ia<2:0> 15:8 r-0 r-0 r-0 r-0 r-1 r-1 r-0 r-1 ds<2:0> dl<2:0> da<2:1> 7:0 r-1 u-0 u-0 r-1 r-1 r-0 r-1 r-1 da<0> p cw rc ae pf p legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 reserved: this bit is hardwired to a 1 to indicate the presence of the config2 register. bit 30-25 mmu size<5:0>: contains the number of tlb entries minus 1 001111 = 16 tlb entries bit 24-22 is<2:0>: instruction cache sets bits 010 = contains 256 instruction cache sets per way bit 21-19 il<2:0>: instruction-cache line bits 011 = contains instruction cache line size of 16 bytes bit 18-16 ia<2:0: instruction-cache associativity bits 011 = contains 4-way instruction cache associativity bit 15-13 ds<2:0>: data-cache sets bits 000 = contains 64 data cache sets per way bit 12-10 dl<2:0>: data-cache line bits 011 = contains data cache line size of 16 bytes bit 9-7 da<2:0>: data-cache associativity bits 011 = contains the 4-way set associativity for the data cache bit 6-5 unimplemented: read as 0 bit 4 pc: performance counter bit 1 = the processor core contains performance counters bit 3 wr: watch register presence bit 1 = no watch registers are present bit 2 ca: code compression implemented bit 0 = no mips16e ? present bit 1 ep: ejtag present bit 1 = core implements ejtag bit 0 fp: floating point unit bit 1 = floating point unit is present
? 2015-2016 microchip technology inc. ds60001320d-page 53 pic32mz embedded connectivity with floating point unit (ef) family register 3-3: config 3: configuration register 3; cp0 register 16, select 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 r-0 r-1 r-0 r-0 r-0 r-1 r/w-y iplw<1:0> mmar<2:0> mcu isaonexc (1) 15:8 r-y r-y r-1 r-1 r-1 r-1 u-0 r-1 isa<1:0> (1) ulri rxi dsp2p dspp i t l 7:0 u-0 r-1 r-1 r-0 r-1 u-0 u-0 r-0 veic vint sp cdmm t l legend: r = reserved bit y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 reserved: this bit is hardwired as 1 to indicate the presence of the config4 register bit 30-23 unimplemented: read as 0 bit 22-21 iplw<1:0>: width of the status ipl and cause ripl bits 01 = ipl and ripl bits are 8-bits in width bit 20-18 mmar<2:0>: micromips architecture revision level bits 000 = release 1 bit 17 mcu: mips ? mcu? ase implemented bit 1 = mcu ase is implemented bit 16 isaonexc: isa on exception bit (1) 1 = micromips is used on entrance to an exception vector 0 = mips32 isa is used on entrance to an exception vector bit 15-14 isa<1:0>: instruction set availability bits (1) 11 = both mips32 and micromips are implemented; micromips is used when coming out of reset 10 = both mips32 and micromips are implemented; mips32 isa used when coming out of reset bit 13 ulri: userlocal register implemented bit 1 = userlocal coprocessor 0 register is implemented bit 12 rxi: rie and xie implemented in pagegrain bit 1 = rie and xie bits are implemented bit 11 dsp2p: mips dsp ase revision 2 presence bit 1 = dsp revision 2 is present bit 10 dspp: mips dsp ase presence bit 1 = dsp is present bit 9 unimplemented: read as 0 bit 8 itl: indicates that iflowtrace ? hardware is present 1 = the iflowtrace ? is implemented in the core bit 7 unimplemented: read as 0 bit 6 veic: external vector interrupt controller bit 1 = support for an external interrupt controller is implemented bit 5 vint: vector interrupt bit 1 = vector interrupts are implemented bit 4 sp: small page bit 0 = 4 kb page size bit 3 cdmm: common device memory map bit 1 = cdmm is implemented bit 2-1 unimplemented: read as 0 bit 0 tl: trace logic bit 0 = trace logic is not implemented note 1: these bits are set based on the value of the bootisa configuration bit (devcfg0<6>).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 54 ? 2015-2016 microchip technology inc. register 3-4: config 5: configuration register 5; cp0 register 16, select 5 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-1 n f legend: r = reserved r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-1 unimplemented: read as 0 bit 0 nf: nested fault bit 1 = nested fault feature is implemented register 3-5: config 7: configuration register 7; cp0 register 16, select 7 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 wii 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 wii: wait ie ignore bit 1 = indicates that this processor will allow an interrupt to unblock a wait instruction bit 30-0 unimplemented: read as 0
? 2015-2016 microchip technology inc. ds60001320d-page 55 pic32mz embedded connectivity with floating point unit (ef) family register 3-6: fir: floating point implementation register; cp1 register 0 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r-1 u-0 u-0 u-0 r-1 u f r p f c 23:16 r-1 r-1 r-1 r-1 r-0 r-0 r-1 r-1 has2008 f64 l w mips3d ps d s 15:8 r-1 r-0 r-1 r-0 r-0 r-1 r-1 r-1 prid<7:0> 7:0 r-x r-x r-x r-x r-x r-x r-x r-x revision<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28 ufrp: user mode fr switching instruction bit 1 = user mode fr switching instructions are supported 0 = user mode fr switching instructions are not supported bit 27-25 unimplemented: read as 0 bit 24 fc: full convert ranges bit 1 = full convert ranges are implemented (all numbers can be converted to another type by the fpu) 0 = full convert ranges are not implemented bit 23 has008: ieee-754-2008 bit 1 = mac2008, abs2008, nan2008 bits exist within the fcsr register 0 = mac2009, abs2008, and nan2008 bits do not exist within the fcsr register bit 22 f64: 64-bit fpu bit 1 = this is a 64-bit fpu 0 = this is not a 64-bit fpu bit 21 l: l ong fixed point data type bit 1 = long fixed point data types are implemented 0 = long fixed point data types are not implemented bit 20 w: word fixed point data type bit 1 = word fixed point data types are implemented 0 = word fixed point data types are not implemented bit 19 mips3d: mips-3d ase bit 1 = mips-3d is implemented 0 = mips-3d is not implemented bit 18 ps: paired single floating point data bit 1 = ps floating point is implemented 0 = ps floating point is not implemented bit 17 d: double-precision (64-bit) floating point data bit 1 = double-precision floating point data types are implemented 0 = double-precision floating point data types are not implemented bit 16 s: single-precision (32-bit) floating point data bit 1 = single-precision floating point data types are implemented 0 = single-precision floating point data types are not implemented bit 15-8 prid<7:0>: processor identification bits these bits allow software to distinguish between the various types of mips processors. for pic32 devices with the m-class core, this value is 0xa7. bit 7-0 revision<7:0>: processor revision identification bits these bits allow software to distinguish between one revision and another of the same processor type. this number is increased on major revisions of the processor core
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 56 ? 2015-2016 microchip technology inc. register 3-7: fccr: floatin g point condition codes register; cp1 register 25 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x fcc<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as 0 bit 7-0 fcc<7:0>: floating point condition code bits these bits record the results of floating point compares and are tested for floating point conditiona l branches and conditional moves.
? 2015-2016 microchip technology inc. ds60001320d-page 57 pic32mz embedded connectivity with floating point unit (ef) family register 3-8: fexr: floating point except ions status register; cp1 register 26 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x cause<5:4> ev 15:8 r/w-x r/w-x r/w-x u-0 u-0 u-0 u-0 u-0 cause<3:0> zoui 7:0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x u-0 u-0 flags<4:0> vzoui legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-18 unimplemented: read as 0 bit 17-12 cause<5:0>: fpu exception cause bits these bits indicated the exception conditions that arise during execution of an fpu arithmetic instruction. bit 17 e: unimplemented operation bit bit 16 v: invalid operation bit bit 15 z: divide-by-zero bit bit 14 o: overflow bit bit 13 u: underflow bit bit 12 i: inexact bit bit 11-7 unimplemented: read as 0 bit 6-2 flags<4:0>: fpu flags bits these bits show any exception conditions that have occurred for completed inst ructions since the flag was last reset by software. bit 6 v: invalid operation bit bit 4 z: divide-by-zero bit bit 4 o: overflow bit bit 3 u: underflow bit bit 2 i: inexact bit bit 1-0 unimplemented: read as 0
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 58 ? 2015-2016 microchip technology inc. register 3-9: fenr: floating point ex ceptions and modes enable register; ? cp1 register 28 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x enables<4:1> vzou 7:0 r/w-x u-0 u-0 u-0 u-0 r-x r/w-x r/w-x enables<0> f s r m < 1 : 0 > i legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-12 unimplemented: read as 0 bit 11-7 enables<4:0>: fpu exception enable bits these bits control whether or not a trap is taken when an ieee exception condition occurs for any of the five conditions. the trap occurs when both an enable bit and its corresponding cause bit are set either during an fpu arithmetic operation or by moving a value to the fcsr or one of its alternative representations. bit 11 v: invalid operation bit bit 10 z: divide-by-zero bit bit 9 o: overflow bit bit 8 u: underflow bit bit 7 i: inexact bit bit 6-3 unimplemented: read as 0 bit 2 fs: flush to zero control bit 1 = denormal input operands are flushed to zero. tiny results are flushed to either zero or the applied format's smallest normalized number (minnorm) depending on the rounding mode settings. 0 = denormal input operands result in an unimplemented operation exception. bit 1-0 rm<1:0>: rounding mode control bits 11 = round towards minus infinity ( C ? ) 10 = round towards plus infinity ( + ? ) 01 = round toward zero (0) 00 = round to nearest
? 2015-2016 microchip technology inc. ds60001320d-page 59 pic32mz embedded connectivity with floating point unit (ef) family register 3-10: fcsr: floating point contro l and status register; cp1 register 31 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x fcc<7:1> fs 23:16 r/w-x r/w-x r/w-x r-0 r-1 r-1 r/w-x r/w-x fcc<0> fo fn mac2008 abs2008 nan2008 cause<5:4> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x cause<3:0> enables<4:1> vzou 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x enables<0> flags<4:0> rm<1:0> ivzoui legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-25 fcc<7:1>: floating point condition code bits these bits record the results of floating point compares and are tested for floating point conditional branches and conditional moves. bit 24 fs: flush to zero control bit 1 = denormal input operands are flushed to zero. tiny results are flushed to either zero or the applied format's smallest normalized number (minnorm) depending on the rounding mode settings. 0 = denormal input operands result in an unimplemented operation exception. bit 23 fcc<0>: floating point condition code bits these bits record the results of floating point compares and are tested for floating point conditional branches and conditional moves. bit 22 fo: flush override control bit 1 = the intermediate result is kept in an internal format, which can be perceived as having the usual mantissa precision but with unlimited exponent precision and without forcing to a specific value or taking an exception. 0 = handling of tiny result values depends on setting of the fs bit. bit 21 fn: flush to nearest control bit 1 = final result is rounded to either zero or 2e_min (minnorm), whichever is closest when in round to nearest (rn) rounding mode. for other rounding modes, a final result is given as if fs was set to 1. 0 = handling of tiny result values depends on setting of the fs bit. bit 20 mac2008: fused multiply add mode control bit 0 = unfused multiply-add. intermediary multiplication results are rounded to the destination format. bit 19 abs2008: absolute value format control bit 1 = abs.fmt and neg.fmt instructions compliant with ieee standard 754-2008. the abs and neg functions accept qnan inputs without trapping. bit 18 nan2008: nan encoding control bit 1 = quiet and signaling nan encodings recommended by the ieee standard 754-2008. a quiet nan is encoded with the first bit of the fraction being 1 and a signaling nan is encoded with the first bit of the fraction being 0. bit 17-12 cause<5:0>: fpu exception cause bits these bits indicated the exception conditions that arise during execution of an fpu arithmetic instruction. bit 17 e: unimplemented operation bit
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 60 ? 2015-2016 microchip technology inc. bit 16 v: invalid operation bit bit 15 z: divide-by-zero bit bit 14 o: overflow bit bit 13 u: underflow bit bit 12 i: inexact bit bit 11-7 enables<4:0>: fpu exception enable bits these bits control whether or not a trap is taken when an ieee exception condition occurs for any of th e five conditions. the trap occurs when both an enable bit and its corresponding cause bit are set either during an fpu arithmetic operation or by moving a value to the fcsr or one of its alternative representations. bit 11 v: invalid operation bit bit 10 z: divide-by-zero bit bit 9 o: overflow bit bit 8 u: underflow bit bit 7 i: inexact bit bit 6-2 flags<4:0>: fpu flags bits these bits show any exception conditions that have occurred for completed inst ructions since the flag was last reset by software. bit 6 v: invalid operation bit bit 5 z: divide-by-zero bit bit 4 o: overflow bit bit 3 u: underflow bit bit 2 i: inexact bit bit 1-0 rm<1:0>: rounding mode control bits 11 = round towards minus infinity ( C ? ) 10 = round towards plus infinity ( + ? ) 01 = round toward zero (0) 00 = round to nearest register 3-10: fcsr: floating point contro l and status register; cp1 register 31
? 2015-2016 microchip technology inc. ds60001320d-page 61 pic32mz embedded connectivity with floating point unit (ef) family 4.0 memory organization pic32mz ef microcontrollers provide 4 gb of unified virtual memory address space. all memory regions, in - cluding program, data memory, sfrs and configura - tion registers, reside in this address space at their respective unique addresses. the program and data memories can be optionally partitioned into user and kernel memories. in addition, pic32mz ef devices allow execution from data memory. key features include: 32-bit native data width separate user (kuseg) and kernel (kseg0/ kseg1/kseg2/kseg3) mode address space separate boot flash memory for protected code robust bus exception handling to intercept ? runaway code cacheable (kseg0/kseg2) and non-cacheable (kseg1/kseg3) address regions read/write permission access to predefined memory regions 4.1 memory layout pic32mz ef microcontrollers implement two address schemes: virtual and physical. all hardware resources, such as program memory, data memory and peripher - als, are located at their respective physical addresses. virtual addresses are exclusively used by the cpu to fetch and execute instructions as well as access pe - ripherals. physical addresses are used by bus master peripherals, such as dma and the flash controller, that access memory independently of the cpu. the main memory maps for the pic32mz ef devices are illustrated in figure 4-1 through figure 4-4 . figure 4-5 provides memory map information for boot flash and boot alias. tab l e 4-1 provides memory map information for special function registers (sfrs). note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source.for detailed information, refer to section 48. memory organization and permissions in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 62 ? 2015-2016 microchip technology inc. figure 4-1: memory map for device s with 512 kb of program memory (1,2) virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xf4000000 0x40000000 0xf3ffffff external memory via sqi 0x3fffffff 0xf0000000 0x34000000 reserved external memory via sqi 0x33ffffff 0xe4000000 0xe3ffffff external memory via ebi 0x30000000 0xe0000000 reserved reserved 0x24000000 0xd4000000 external memory via ebi 0x23ffffff 0xd3ffffff external memory via sqi 0xd0000000 0x20000000 reserved reserved 0xc4000000 0x1fc74000 0xc3ffffff external memory via ebi boot flash (see figure 4-5 ) 0x1fc73fff 0xc0000000 0xbfffffff reserved 0x1fc00000 0xbfc74000 reserved 0xbfc73fff boot flash (see figure 4-5 ) 0x1f900000 sfrs (see table 4-1 ) 0x1f8fffff 0xbfc00000 reserved 0x1f800000 0xbf900000 reserved 0xbf8fffff sfrs (see table 4-1 ) 0x1d080000 0xbf800000 program flash 0x1d07ffff reserved 0xbd080000 0x1d000000 0xbd07ffff program flash reserved 0x00020000 0xbd000000 ram (3) 0x0001ffff reserved 0x00000000 0xa0020000 0xa001ffff ram (3) 0xa0000000 reserved 0x9fc74000 0x9fc73fff boot flash (see figure 4-5 ) 0x9fc00000 reserved 0x9d080000 0x9d07ffff program flash 0x9d000000 reserved 0x80020000 0x8001ffff ram (3) 0x80000000 reserved 0x00000000 note 1: memory areas are not shown to scale. 2: the cache, mmu, and tlb are initialized by compiler start-up code. 3: ram memory is divided into two equal banks: ram bank 1 and ram bank 2 on a half boundary . 4: the mmu must be enabled and the tlb must be set up to access this segment. kseg1 kseg0 kseg3 (4) (not cacheable) (not cacheable) (cacheable) kseg2 (4) (cacheable)
? 2015-2016 microchip technology inc. ds60001320d-page 63 pic32mz embedded connectivity with floating point unit (ef) family figure 4-2: memory map fo r devices with 1024 kb of program memory and 256 kb of ram (1,2) virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xf4000000 0xf3ffffff external memory via sqi 0xf0000000 0x34000000 reserved external memory via sqi 0x33ffffff 0xe4000000 0xe3ffffff external memory via ebi 0x30000000 0xe0000000 reserved reserved 0x24000000 0xd4000000 external memory via ebi 0x23ffffff 0xd3ffffff external memory via sqi 0xd0000000 0x20000000 reserved reserved 0xc4000000 0x1fc74000 0xc3ffffff external memory via ebi boot flash (see figure 4-5 ) 0x1fc73fff 0xc0000000 0xbfffffff reserved 0x1fc00000 0xbfc74000 reserved 0xbfc73fff boot flash (see figure 4-5 ) 0x1f900000 sfrs (see table 4-1 ) 0x1f8fffff 0xbfc00000 reserved 0x1f800000 0xbf900000 reserved 0xbf8fffff sfrs (see table 4-1 ) 0x1d100000 0xbf800000 program flash 0x1d0fffff reserved 0xbd100000 0x1d000000 0xbd0fffff program flash reserved 0x00040000 0xbd000000 ram (3) 0x0003ffff reserved 0x00000000 0xa0040000 0xa003ffff ram (3) 0xa0000000 reserved 0x9fc74000 0x9fc73fff boot flash (see figure 4-5 ) 0x9fc00000 reserved 0x9d100000 0x9d0fffff program flash 0x9d000000 reserved 0x80040000 0x8003ffff ram (3) 0x80000000 reserved 0x00000000 note 1: memory areas are not shown to scale. 2: the cache, mmu, and tlb are initialized by compiler start-up code. 3: ram memory is divided into two equal banks: ram bank 1 and ram bank 2 on a half boundar y. 4: the mmu must be enabled and the tlb must be set up to access this segment. kseg1 kseg0 kseg3 (4) (not cacheable) (not cacheable) (cacheable) kseg2 (4) (cacheable)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 64 ? 2015-2016 microchip technology inc. figure 4-3: memory map fo r devices with 1024 kb of program memory and 512 kb of ram (1,2) virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xf4000000 0xf3ffffff external memory via sqi 0xf0000000 0x34000000 reserved external memory via sqi 0x33ffffff 0xe4000000 0xe3ffffff external memory via ebi 0x30000000 0xe0000000 reserved reserved 0x24000000 0xd4000000 external memory via ebi 0x23ffffff 0xd3ffffff external memory via sqi 0xd0000000 0x20000000 reserved reserved 0xc4000000 0x1fc74000 0xc3ffffff external memory via ebi boot flash (see figure 4-5 ) 0x1fc73fff 0xc0000000 0xbfffffff reserved 0x1fc00000 0xbfc74000 reserved 0xbfc73fff boot flash (see figure 4-5 ) 0x1f900000 sfrs (see table 4-1 ) 0x1f8fffff 0xbfc00000 reserved 0x1f800000 0xbf900000 reserved 0xbf8fffff sfrs (see table 4-1 ) 0x1d100000 0xbf800000 program flash 0x1d0fffff reserved 0xbd100000 0x1d000000 0xbd0fffff program flash reserved 0x00080000 0xbd000000 ram (3) 0x0007ffff reserved 0x00000000 0xa0080000 0xa007ffff ram (3) 0xa0000000 reserved 0x9fc74000 0x9fc73fff boot flash (see figure 4-5 ) 0x9fc00000 reserved 0x9d100000 0x9d0fffff program flash 0x9d000000 reserved 0x80080000 0x8007ffff ram (3) 0x80000000 reserved 0x00000000 note 1: memory areas are not shown to scale. 2: the cache, mmu, and tlb are initialized by compiler start-up code. 3: ram memory is divided into two equal banks: ram bank 1 and ram bank 2 on a half boundar y. 4: the mmu must be enabled and the tlb must be set up to access this segment. kseg1 kseg0 kseg3 (4) (not cacheable) (not cacheable) (cacheable) kseg2 (4) (cacheable)
? 2015-2016 microchip technology inc. ds60001320d-page 65 pic32mz embedded connectivity with floating point unit (ef) family figure 4-4: memory map for devices with 2048 kb of program memory (1,2) virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xf4000000 0xf3ffffff external memory via sqi 0xf0000000 0x34000000 reserved external memory via sqi 0x33ffffff 0xe4000000 0xe3ffffff external memory via ebi 0x30000000 0xe0000000 reserved reserved 0x24000000 0xd4000000 external memory via ebi 0x23ffffff 0xd3ffffff external memory via sqi 0xd0000000 0x20000000 reserved reserved 0xc4000000 0x1fc74000 0xc3ffffff external memory via ebi boot flash (see figure 4-5 ) 0x1fc73fff 0xc0000000 0xbfffffff reserved 0x1fc00000 0xbfc74000 reserved 0xbfc73fff boot flash (see figure 4-5 ) 0x1f900000 sfrs (see table 4-1 ) 0x1f8fffff 0xbfc00000 reserved 0x1f800000 0xbf900000 reserved 0xbf8fffff sfrs (see table 4-1 ) 0x1d200000 0xbf800000 program flash 0x1d1fffff reserved 0xbd200000 0x1d000000 0xbd1fffff program flash reserved 0x00080000 0xbd000000 ram (3) 0x0007ffff reserved 0x00000000 0xa0080000 0xa007ffff ram (3) 0xa0000000 reserved 0x9fc74000 0x9fc73fff boot flash (see figure 4-5 ) 0x9fc00000 reserved 0x9d200000 0x9d1fffff program flash 0x9d000000 reserved 0x80080000 0x8007ffff ram (3) 0x80000000 reserved 0x00000000 note 1: memory areas are not shown to scale. 2: the cache, mmu, and tlb are initialized by compiler start-up code. 3: ram memory is divided into two equal banks: ram bank 1 and ram bank 2 on a half boundar y. 4: the mmu must be enabled and the tlb must be set up to access this segment. kseg1 kseg0 kseg3 (4) (not cacheable) (not cacheable) (cacheable) kseg2 (4) (cacheable)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 66 ? 2015-2016 microchip technology inc. figure 4-5: boot and alias memory map table 4-1: sfr memory map physical memory map (1) 0x1fc74000 sequence/configuration space (3) 0x1fc70000 0x1fc6ff00 boot flash 2 0x1fc60000 reserved 0x1fc54020 serial number (4) 0x1fc54000 sequence/configuration space (3) 0x1fc50000 0x1fc4ff00 boot flash 1 0x1fc40000 reserved 0x1fc34000 unused configuration space (5) 0x1fc30000 0x1fc2ff00 upper boot alias 0x1fc20000 reserved 0x1fc14000 configuration space (2,3) 0x1fc10000 0x1fc0ff00 lower boot alias 0x1fc00000 note 1: memory areas are not shown to scale. 2: memory locations 0x1fc0ff40 through 0x1fc0fffc are used to initialize configuration registers (see section 34.0 special features ). 3: refer to section 4.1.1 boot flash sequence and configuration spaces for more information. 4: memory locations 0x1fc54020 and 0x1fc54024 contain a unique device serial number (see section 34.0 special features ). 5: this configuration space cannot be used for executing code in the upper boot alias. peripheral virtual address base offset start system bus (1) 0xbf8f0000 0x0000 prefetch 0xbf8e0000 0x0000 ebi 0x1000 sqi1 0x2000 usb 0x3000 crypto 0x5000 rng 0x6000 can1 and can2 0xbf880000 0x0000 ethernet 0x2000 usbcr 0x4000 porta-portk 0xbf860000 0x0000 timer1-timer9 0xbf840000 0x0000 ic1-ic9 0x2000 oc1-oc9 0x4000 adc 0xb000 comparator 1, 2 0xc000 i2c1-i2c5 0xbf820000 0x0000 spi1-spi6 0x1000 uart1-uart6 0x2000 pmp 0xe000 interrupt controller 0xbf810000 0x0000 dma 0x1000 configuration 0xbf800000 0x0000 flash controller 0x0600 watchdog timer 0x0800 deadman timer 0x0a00 rtcc 0x0c00 cv ref 0x0e00 oscillator 0x1200 pps 0x1400 note 1: refer to 4.2 system bus arbitration for important legal information.
? 2015-2016 microchip technology inc. ds60001320d-page 67 pic32mz embedded connectivity with floating point unit (ef) family 4.1.1 boot flash sequence and configuration spaces sequence space is used to identify which boot flash is aliased by aliased regions. if the value programmed into the tseq<15:0> bits of the bf1seq3 word is equal to or greater than the value programmed into the tseq<15:0> bits of the bf2seq3 word, boot flash 1 is aliased by the lower boot alias region, and boot flash 2 is aliased by the upper boot alias region. if the tseq<15:0> bits of the bf2seq3 word is greater than the tseq<15:0> bits of the bf1seq3 word, the oppo - site is true (see ta b l e 4-2 and tab le 4-3 for bfxseq3 word memory locations). the cseq<15:0> bits must contain the ones complement value of the tseq<15:0> bits; otherwise, the value of the tseq<15:0> bits is considered invalid, and an alternate sequence is used. see section 4.1.2 alternate sequence and configuration words for more information. once boot flash memories are aliased, configuration space located in the lower boot alias region is used as the basis for the configuration words, devsign0, devcp0, and devcfgx (and the associated alternate configuration registers). this means that the boot flash region to be aliased by lower boot alias region memory must contain configuration values in the appropriate memory locations. 4.1.2 alternate sequence and configuration words every word in the configuration space and sequence space has an associated alternate word (designated by the letter a as the first letter in the name of the word). during device start-up, primary words are read and if uncorrectable ecc errors are found, the bcfgerr (rcon<27>) flag is set and alternate words are used. if uncorrectable ecc errors are found in primary and alternate words, the bcfgfail (rcon<26>) flag is set and the default configuration is used. note: do not use word program operation (nvmop<3:0> = 0001 ) when program - ming data into the sequence and configuration spaces.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 68 ? 2015-2016 microchip technology inc. table 4-2: boot flash 1 sequence and configuration words summary virtual address (bfc4_#) register name bit range bits all reset 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ff40 abf1devcfg3 31:0 note: see table 34-2 for the bit descriptions. xxxx ff44 abf1devcfg2 31:0 xxxx ff48 abf1devcfg1 31:0 xxxx ff4c abf1devcfg0 31:0 xxxx ff50 abf1devcp3 31:0 xxxx ff54 abf1devcp2 31:0 xxxx ff58 abf1devcp1 31:0 xxxx ff5c abf1devcp0 31:0 xxxx ff60 abf1devsign3 31:0 xxxx ff64 abf1devsign2 31:0 xxxx ff68 abf1devsign1 31:0 xxxx ff6c abf1devsign0 31:0 xxxx ffc0 bf1devcfg3 31:0 note: see table 34-1 for the bit descriptions. xxxx ffc4 bf1devcfg2 31:0 xxxx ffc8 bf1devcfg1 31:0 xxxx ffcc bf1devcfg0 31:0 xxxx ffd0 bf1devcp3 31:0 xxxx ffd4 bf1devcp2 31:0 xxxx ffd8 bf1devcp1 31:0 xxxx ffdc bf1devcp0 31:0 xxxx ffe0 bf1devsign3 31:0 xxxx ffe4 bf1devsign2 31:0 xxxx ffe8 bf1devsign1 31:0 xxxx ffec bf1devsign0 31:0 xxxx fff0 bf1seq3 31:16 cseq<15:0> xxxx 15:0 tseq<15:0> xxxx fff4 bf1seq2 31:16 xxxx 15:0 xxxx fff8 bf1seq1 31:16 xxxx 15:0 xxxx fffc bf1seq0 31:16 xxxx 15:0 xxxx legend: x = unknown value on reset; = reserved, read as 1 . reset values are shown in hexadecimal.
? 2015-2016 microchip technology inc. ds60001320d-page 69 pic32mz embedded connectivity with floating point unit (ef) family table 4-3: boot flash 2 sequence and configuration words summary virtual address (bfc6_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ff40 abf2devcfg3 31:0 note: see table 34-2 for the bit descriptions. xxxx ff44 abf2devcfg2 31:0 xxxx ff48 abf2devcfg1 31:0 xxxx ff4c abf2devcfg0 31:0 xxxx ff50 abf2devcp3 31:0 xxxx ff54 abf2devcp2 31:0 xxxx ff58 abf2devcp1 31:0 xxxx ff5c abf2devcp0 31:0 xxxx ff60 abf2devsign3 31:0 xxxx ff64 abf2devsign2 31:0 xxxx ff68 abf2devsign1 31:0 xxxx ff6c abf2devsign0 31:0 xxxx ffc0 bf2devcfg3 31:0 note: see table 34-1 for the bit descriptions. xxxx ffc4 bf2devcfg2 31:0 xxxx ffc8 bf2devcfg1 31:0 xxxx ffcc bf2devcfg0 31:0 xxxx ffd0 bf2devcp3 31:0 xxxx ffd4 bf2devcp2 31:0 xxxx ffd8 bf2devcp1 31:0 xxxx ffdc bf2devcp0 31:0 xxxx ffe0 bf2devsign3 31:0 xxxx ffe4 bf2devsign2 31:0 xxxx ffe8 bf2devsign1 31:0 xxxx ffec bf2devsign0 31:0 xxxx fff0 bf2seq3 31:16 cseq<15:0> xxxx 15:0 tseq<15:0> xxxx fff4 bf2seq2 31:16 xxxx 15:0 xxxx fff8 bf2seq1 31:16 xxxx 15:0 xxxx fffc bf2seq0 31:16 xxxx 15:0 xxxx legend: x = unknown value on reset; = reserved, read as 1 . reset values are shown in hexadecimal.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 70 ? 2015-2016 microchip technology inc. register 4-1: bfxseq3: boot flash x sequence word 3 register (x = 1 and 2) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/p r/p r/p r/p r/p r/p r/p r/p cseq<15:8> 23:16 r/p r/p r/p r/p r/p r/p r/p r/p cseq<7:0> 15:8 r/p r/p r/p r/p r/p r/p r/p r/p tseq<15:8> 7:0 r/p r/p r/p r/p r/p r/p r/p r/p tseq<7:0> legend: p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 cseq<15:0>: boot flash complement sequence number bits bit 15-0 tseq<15:0>: boot flash true sequence number bits note: the bfxseq0, bfxseq1, and bfxseq2 registers are used for quad word programming operation when programming the bfxseq3 registers, and do not contain any valid information.
? 2015-2016 microchip technology inc. ds60001320d-page 71 pic32mz embedded connectivity with floating point unit (ef) family 4.2 system bus arbitration as shown in the pic32mz ef family block diagram (see figure 1-1 ), there are multiple initiator modules (i1 through i14) in the system that can access various tar - get modules (t1 through t13). tab l e 4-4 illustrates which initiator can access which target. the system bus supports simultaneous access to targets by initiators, so long as the initiators are accessing differ - ent targets. the system bus will perform arbitration, if multiple initiators attempt to access the same target. note: the system bus interconnect implements one or more instantiations of the sonicssx ? interconnect from sonics, inc. this document contains materials that are (c) 2003-2015 sonics, inc., and that constitute proprietary information of sonics, inc. sonicssx is a registered trademark of sonics, inc. all such materials and trademarks are used under license from sonics, inc.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 72 ? 2015-2016 microchip technology inc. table 4-4: initiators to targets access association target # i n i t i a t o r i d 1234567891 01 11 21 31 4 name cpu dma read dma write usb ethernet read ethernet write can1 can2 sqi1 flash controller crypto 1 flash memory: program flash ? boot flash ? prefetch module xx xx xx x 2r a m b a n k 1 m e m o r y x x x xxxxxx x x 3r a m b a n k 2 m e m o r y x x x xxxxxx x x 4e x t e r n a l m e m o r y v i a e b i a n d e b i m o d u l e x x x xxxxxx x 5 peripheral set 1: ? system control, flash control, dmt, ? rtcc, cvr, pps input, pps output, ? interrupts, dma, wdt x 6 peripheral set 2: ? spi1-spi6 ? i2c1-i2c5 ? uart1-uart6 ? pmp xxx 7 peripheral set 3: ? timer1-timer9 ? ic1-ic9 ? oc1-oc9 ? adc ? comparator 1 ? comparator 2 xxx 8 peripheral set 4: ? porta-portk xxx 9 peripheral set 5: ? can1 ? can2 ? ethernet controller x 10 peripheral set 6 : ? usb x 11 external memory via sqi1 and ? sqi1 module x 12 peripheral set 7: ? crypto engine x 13 peripheral set 8: ? rng module x
? 2015-2016 microchip technology inc. ds60001320d-page 73 pic32mz embedded connectivity with floating point unit (ef) family the system bus arbitration scheme implements a non- programmable, least recently serviced (lrs) priority, which provides quality of service (qos) for most initiators. however, some initiators can use fixed high priority (high) arbitration to guarantee their access to data. the arbitration scheme for the available initiators is shown in tab l e 4-5 . table 4-5: initiator id and qos 4.3 permission access and system bus registers the system bus on pic32mz ef family of microcontrollers provides access control capabilities for the transaction initiators on the system bus. the system bus divides the entire memory space into fourteen target regions and permits access to each target by initiators via permission groups. four permission groups (0 through 3) can be assigned to each initiator. each permission group is independent of the others and can have exclusive or shared access to a region. using the cfgpg register (see register 34-10 in section 34.0 special features ), boot firmware can assign a permission group to each initiator, which can make requests on the system bus. the available targets and their regions, as well as the associated control registers to assign protection, are described and listed in table 4-6 . register 4-2 through register 4-10 are used for setting and controlling access permission groups and regions. to change these registers, they must be unlocked in hardware. the register lock is controlled by the pglock configuration bit (cfgcon<11>). setting pglock prevents writes to the control registers; clearing pglock allows writes. to set or clear the pglock bit, an unlock sequence must be executed. refer to section 42. oscillators with enhanced pll in the ?pic32 family reference manual? for details. name id qos cpu 1 lrs (1) cpu 2 high (1,2) dma read 3 lrs (1) dma read 4 high (1,2) dma write 5 lrs (1) dma write 6 high (1,2) usb 7 lrs ethernet read 8 lrs ethernet write 9 lrs can1 10 lrs can2 11 lrs sqi1 12 lrs flash controller 13 high (2) crypto 14 lrs note 1: when accessing sram, the dmapri bit (cfgcon<25>) and the cpupri bit (cfgcon<24>) provide arbitration con - trol for the dma and cpu (when servicing an interrupt (i.e., exl = 1 )), respectively, by selecting the use of lrs or high when using high, the dma and cpu get arbitration preference over all initiators using lrs. 2: using high arbitration can have serious negative effects on other initiators. therefore, it is recommended to not enable this type of arbitration for an initia - tor that uses significant system band - width. high arbitration is intended to be used for low bandwidth applications that require low latency, such as lcc graphics applications.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 74 ? 2015-2016 microchip technology inc. table 4-6: system bus targets and associated protection registers target number target description (5) sbtxregy register sbtxrdy register sbtxwry register name region base (base<21:0>) (see note 2) physical start address region size (size<4:0>) (see note 3) region size priority (pri) priority level name read permission (group3, group2, group1, group0) name write permission (group3, group2, group1, group0) 0 system bus sbt0reg0 r 0x1f8f0000 r 64 kb 0 sbt0rd0 r/w (1) sbt0wr0 r/w (1) sbt0reg1 r 0x1f8f8000 r 32 kb 3 sbt0rd1 r/w (1) sbt0wr1 r/w (1) 1 flash memory (6) : program flash boot flash prefetch module sbt1reg0 r 0x1d000000 r (4) r (4) 0 sbt1rd0 r/w (1) sbt1wr0 0, 0, 0, 0 sbt1reg2 r 0x1f8e0000 r 4 kb 1 2 sbt1rd2 r/w (1) sbt1wr2 r/w (1) sbt1reg3 r/w r/w r/w r/w 1 2 sbt1rd3 r/w (1) sbt1wr3 0, 0, 0, 0 sbt1reg4 r/w r/w r/w r/w 1 2 sbt1rd4 r/w (1) sbt1wr4 0, 0, 0, 0 sbt1reg5 r/w r/w r/w r/w 1 2 sbt1rd5 r/w (1) sbt1wr5 0, 0, 0, 0 sbt1reg6 r/w r/w r/w r/w 1 2 sbt1rd6 r/w (1) sbt1wr6 0, 0, 0, 0 sbt1reg7 r/w r/w r/w r/w 0 1 sbt1rd7 r/w (1) sbt1wr7 0, 0, 0, 0 sbt1reg8 r/w r/w r/w r/w 0 1 sbt1rd8 r/w (1) sbt1wr8 0, 0, 0, 0 2 ram bank 1 memory sbt2reg0 r 0x00000000 r (4) r (4) 0 sbt2rd0 r/w (1) sbt2wr0 r/w (1) sbt2reg1 r/w r/w r/w r/w 3 sbt2rd1 r/w (1) sbt2wr1 r/w (1) sbt2reg2 r/w r/w r/w r/w 0 1 sbt2rd2 r/w (1) sbt2wr2 r/w (1) 3 ram bank 2 memory sbt3reg0 r (4) r (4) r (4) r (4) 0 sbt3rd0 r/w (1) sbt3wr0 r/w (1) sbt3reg1 r/w r/w r/w r/w 3 sbt3rd1 r/w (1) sbt3wr1 r/w (1) sbt3reg2 r/w r/w r/w r/w 0 1 sbt3rd2 r/w (1) sbt3wr2 r/w (1) 4 external memory via ebi and ebi module (6) sbt4reg0 r 0x20000000 r 64 mb 0 sbt4rd0 r/w (1) sbt4wr0 r/w (1) sbt4reg2 r 0x1f8e1000 r 4 kb 0 1 sbt4rd2 r/w (1) sbt4wr2 r/w (1) 5 peripheral set 1: system control flash control dmt/wdt rtcc cvr pps input pps output interrupts dma sbt5reg0 r 0x1f800000 r 128 kb 0 sbt5rd0 r/w (1) sbt5wr0 r/w (1) sbt5reg1 r/w r/w r/w r/w 3 sbt5rd1 r/w (1) sbt5wr1 r/w (1) sbt5reg2 r/w r/w r/w r/w 0 1 sbt5rd2 r/w (1) sbt5wr2 r/w (1) legend: r = read; r/w = read/write; x in a register name = 0-13; y in a register name = 0-8. note 1: reset values for these bits are 0 , 1 , 1 , 1 , respectively. 2: the base<21:0> bits must be set to the corresponding physical ad dress and right shifted by 10 bits. for read-only bits, this va lue is set by hardware on reset. 3: the size<4:0> bits must be set to the corresponding region size, based on the following formula: regi on size = 2 (size-1) x 1024 bytes. for read-only bits, this value is set by hardware on reset. 4: refer to the device memory maps ( figure 4-1 through figure 4-4 ) for specific device memory sizes and start addresses. 5: see table 4-1 for information on specific target memory size and start addresses. 6: the sbtxreg1 sfrs are reserved, and therefore, are not listed in this table for this target.
? 2015-2016 microchip technology inc. ds60001320d-page 75 pic32mz embedded connectivity with floating point unit (ef) family 6 peripheral set 2: spi1-spi6 i2c1-i2c5 uart1-uart6 pmp sbt6reg0 r 0x1f820000 r 64 kb 0 sbt6rd0 r/w (1) sbt6wr0 r/w (1) sbt6reg1 r/w r/w r/w r/w 3 sbt6rd1 r/w (1) sbt6wr1 r/w (1) 7 peripheral set 3: timer1-timer9 ic1-ic9 oc1-oc9 adc comparator 1 comparator 2 sbt7reg0 r 0x1f840000 r 64 kb 0 sbt7rd0 r/w (1) sbt7wr0 r/w (1) sbt7reg1 r/w r/w r/w r/w 3 sbt7rd1 r/w (1) sbt7wr1 r/w (1) 8 peripheral set 4: porta-portk sbt8reg0 r 0x1f860000 r 64 kb 0 sbt8rd0 r/w (1) sbt8wr0 r/w (1) sbt8reg1 r/w r/w r/w r/w 3 sbt8rd1 r/w (1) sbt8wr1 r/w (1) 9 peripheral set 5: can1can2 ethernet controller sbt9reg0 r 0x1f880000 r 64 kb 0 sbt9rd0 r/w (1) sbt9wr0 r/w (1) sbt9reg1 r/w r/w r/w r/w 3 sbt9rd1 r/w (1) sbt9wr1 r/w (1) 10 peripheral set 6: usb sbt10reg0 r 0x1f8e3000 r 4 kb 0 sbt10rd0 r/w (1) sbt10wr0 r/w (1) 11 external memory via sqi1 and sqi1 module sbt11reg0 r 0x30000000 r 64 mb 0 sbt11rd0 r/w (1) sbt11wr0 r/w (1) sbt11reg1 r 0x1f8e2000 r 4 kb 3 sbt11rd1 r/w (1) sbt11wr1 r/w (1) 12 peripheral set 7: crypto engine sbt12reg0 r 0x1f8e5000 r 4 kb 0 sbt12rd0 r/w (1) sbt12wr0 r/w (1) 13 peripheral set 8: rng module sbt13reg0 r 0x1f8e6000 r 4 kb 0 sbt13rd0 r/w (1) sbt13wr0 r/w (1) table 4-6: system bus targets and associated protection registers (continued) target number target description (5) sbtxregy register sbtxrdy register sbtxwry register name region base (base<21:0>) (see note 2) physical start address region size (size<4:0>) (see note 3) region size priority (pri) priority level name read permission (group3, group2, group1, group0) name write permission (group3, group2, group1, group0) legend: r = read; r/w = read/write; x in a register name = 0-13; y in a register name = 0-8. note 1: reset values for these bits are 0 , 1 , 1 , 1 , respectively. 2: the base<21:0> bits must be set to the corresponding physical ad dress and right shifted by 10 bits. for read-only bits, this va lue is set by hardware on reset. 3: the size<4:0> bits must be set to the corresponding region size, based on the following formula: regi on size = 2 (size-1) x 1024 bytes. for read-only bits, this value is set by hardware on reset. 4: refer to the device memory maps ( figure 4-1 through figure 4-4 ) for specific device memory sizes and start addresses. 5: see table 4-1 for information on specific target memory size and start addresses. 6: the sbtxreg1 sfrs are reserved, and therefore, are not listed in this table for this target.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 76 ? 2015-2016 microchip technology inc. table 4-7: system bus register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 0510 sbflag 31:16 0000 15:0 t13pgv t12pgv t11pgv t10pgv t9pgv t8pgv t7pgv t6pgv t5pgv t4pgv t3pgv t2pgv t1 pgv t0pgv 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-8: system bus target 0 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 8020 sbt0elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> cmd<2:0> 0000 8024 sbt0elog2 31:16 0000 15:0 group<1:0> 0000 8028 sbt0econ 31:16 errp 0000 15:0 0000 8030 sbt0eclrs 31:16 0000 15:0 clear 0000 8038 sbt0eclrm 31:16 0000 15:0 clear 0000 8040 sbt0reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri size<4:0> xxxx 8050 sbt0rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8058 sbt0wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8060 sbt0reg1 31:16 base<21:6> xxxx 15:0 base<5:0> pri size<4:0> xxxx 8070 sbt0rd1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8078 sbt0wr1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
? 2015-2016 microchip technology inc. ds60001320d-page 77 pic32mz embedded connectivity with floating point unit (ef) family table 4-9: system bus target 1 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 8420 sbt1elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 8424 sbt1elog2 31:16 0000 15:0 group<1:0> 0000 8428 sbt1econ 31:16 errp 0000 15:0 0000 8430 sbt1eclrs 31:16 0000 15:0 c l e a r 0000 8438 sbt1eclrm 31:16 0000 15:0 c l e a r 0000 8440 sbt1reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 8450 sbt1rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8458 sbt1wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8480 sbt1reg2 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 8490 sbt1rd2 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8498 sbt1wr2 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 84a0 sbt1reg3 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 84b0 sbt1rd3 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 84b8 sbt1wr3 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 84c0 sbt1reg4 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 84d0 sbt1rd4 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 84d8 sbt1wr4 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 78 ? 2015-2016 microchip technology inc. 84e0 sbt1reg5 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 84f0 sbt1rd5 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 84f8 sbt1wr5 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8500 sbt1reg6 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 8510 sbt1rd6 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8518 sbt1wr6 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8520 sbt1reg7 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 8530 sbt1rd7 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8538 sbt1wr7 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8540 sbt1reg8 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 8550 sbt1rd8 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8558 sbt1wr8 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx table 4-9: system bus target 1 register map (continued) virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
? 2015-2016 microchip technology inc. ds60001320d-page 79 pic32mz embedded connectivity with floating point unit (ef) family table 4-10: system bus target 2 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 8820 sbt2elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 8824 sbt2elog2 31:16 0000 15:0 group<1:0> 0000 8828 sbt2econ 31:16 errp 0000 15:0 0000 8830 sbt2eclrs 31:16 0000 15:0 c l e a r 0000 8838 sbt2eclrm 31:16 0000 15:0 c l e a r 0000 8840 sbt2reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 8850 sbt2rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8858 sbt2wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8860 sbt2reg1 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 8870 sbt2rd1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8878 sbt2wr1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8880 sbt2reg2 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 8890 sbt2rd2 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8898 sbt2wr2 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 80 ? 2015-2016 microchip technology inc. table 4-11: system bus target 3 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 8c20 sbt3elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 8c24 sbt3elog2 31:16 0000 15:0 group<1:0> 0000 8c28 sbt3econ 31:16 errp 0000 15:0 0000 8c30 sbt3eclrs 31:16 0000 15:0 c l e a r 0000 8c38 sbt3eclrm 31:16 0000 15:0 c l e a r 0000 8c40 sbt3reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 8c50 sbt3rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8c58 sbt3wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8c60 sbt3reg1 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 8c70 sbt3rd1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8c78 sbt3wr1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8c80 sbt3reg2 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 8c90 sbt3rd2 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 8c98 sbt3wr2 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
? 2015-2016 microchip technology inc. ds60001320d-page 81 pic32mz embedded connectivity with floating point unit (ef) family table 4-12: system bus target 4 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 9020 sbt4elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 9024 sbt4elog2 31:16 0000 15:0 group<1:0> 0000 9028 sbt4econ 31:16 errp 0000 15:0 0000 9030 sbt4eclrs 31:16 0000 15:0 c l e a r 0000 9038 sbt4eclrm 31:16 0000 15:0 c l e a r 0000 9040 sbt4reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 9050 sbt4rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9058 sbt4wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9080 sbt4reg2 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 9090 sbt4rd2 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9098 sbt4wr2 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 82 ? 2015-2016 microchip technology inc. table 4-13: system bus target 5 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 9420 sbt5elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 9424 sbt5elog2 31:16 0000 15:0 group<1:0> 0000 9428 sbt5econ 31:16 errp 0000 15:0 0000 9430 sbt5eclrs 31:16 0000 15:0 c l e a r 0000 9438 sbt5eclrm 31:16 0000 15:0 c l e a r 0000 9440 sbt5reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 9450 sbt5rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9458 sbt5wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9460 sbt5reg1 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 9470 sbt5rd1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9478 sbt5wr1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9480 sbt5reg2 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 9490 sbt5rd2 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9498 sbt5wr2 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
? 2015-2016 microchip technology inc. ds60001320d-page 83 pic32mz embedded connectivity with floating point unit (ef) family table 4-14: system bus target 6 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 9820 sbt6elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 9824 sbt6elog2 31:16 0000 15:0 group<1:0> 0000 9828 sbt6econ 31:16 errp 0000 15:0 0000 9830 sbt6eclrs 31:16 0000 15:0 c l e a r 0000 9838 sbt6eclrm 31:16 0000 15:0 c l e a r 0000 9840 sbt6reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 9850 sbt6rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9858 sbt6wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9860 sbt6reg1 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 9870 sbt6rd1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9878 sbt6wr1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 84 ? 2015-2016 microchip technology inc. table 4-15: system bus target 7 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 9c20 sbt7elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 9c24 sbt7elog2 31:16 0000 15:0 group<1:0> 0000 9c28 sbt7econ 31:16 errp 0000 15:0 0000 9c30 sbt7eclrs 31:16 0000 15:0 c l e a r 0000 9c38 sbt7eclrm 31:16 0000 15:0 c l e a r 0000 9c40 sbt7reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 9c50 sbt7rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9c58 sbt7wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9c60 sbt7reg1 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx 9c70 sbt7rd1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx 9c78 sbt7wr1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
? 2015-2016 microchip technology inc. ds60001320d-page 85 pic32mz embedded connectivity with floating point unit (ef) family table 4-16: system bus target 8 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 a020 sbt8elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 a024 sbt8elog2 31:16 0000 15:0 group<1:0> 0000 a028 sbt8econ 31:16 errp 0000 15:0 0000 a030 sbt8eclrs 31:16 0000 15:0 c l e a r 0000 a038 sbt8eclrm 31:16 0000 15:0 c l e a r 0000 a040 sbt8reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx a050 sbt8rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx a058 sbt8wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx a060 sbt8reg1 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx a070 sbt8rd1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx a078 sbt8wr1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 86 ? 2015-2016 microchip technology inc. table 4-17: system bus target 9 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 a420 sbt9elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 a424 sbt9elog2 31:16 0000 15:0 group<1:0> 0000 a428 sbt9econ 31:16 errp 0000 15:0 0000 a430 sbt9eclrs 31:16 0000 15:0 c l e a r 0000 a438 sbt9eclrm 31:16 0000 15:0 c l e a r 0000 a440 sbt9reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx a450 sbt9rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx a458 sbt9wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx a460 sbt9reg1 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx a470 sbt9rd1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx a478 sbt9wr1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
? 2015-2016 microchip technology inc. ds60001320d-page 87 pic32mz embedded connectivity with floating point unit (ef) family table 4-18: system bus target 10 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 a820 sbt10elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 a824 sbt10elog2 31:16 0000 15:0 group<1:0> 0000 a828 sbt10econ 31:16 errp 0000 15:0 0000 a830 sbt10eclrs 31:16 0000 15:0 c l e a r 0000 a838 sbt10eclrm 31:16 0000 15:0 c l e a r 0000 a840 sbt10reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx a850 sbt10rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx a858 sbt10wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 88 ? 2015-2016 microchip technology inc. table 4-19: system bus target 11 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 ac20 sbt11elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 ac24 sbt11elog2 31:16 0000 15:0 group<1:0> 0000 ac28 sbt11econ 31:16 errp 0000 15:0 0000 ac30 sbt11eclrs 31:16 0000 15:0 c l e a r 0000 ac38 sbt11eclrm 31:16 0000 15:0 c l e a r 0000 ac40 sbt11reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx ac50 sbt11rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx ac58 sbt11wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx ac60 sbt11reg1 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx ac70 sbt11rd1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx ac78 sbt11wr1 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 89 ? 2015-2016 microchip technology inc. table 4-20: system bus target 12 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 b020 sbt12elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 b024 sbt12elog2 31:16 0000 15:0 group<1:0> 0000 b028 sbt12econ 31:16 errp 0000 15:0 0000 b030 sbt12eclrs 31:16 0000 15:0 c l e a r 0000 b038 sbt12eclrm 31:16 0000 15:0 c l e a r 0000 b040 sbt12reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx b050 sbt12rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx b058 sbt12wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 90 ? 2015-2016 microchip technology inc. table 4-21: system bus target 13 register map virtual address (bf8f_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 1 7/1 16/0 b420 sbt13elog1 31:16 multi code<3:0> 0000 15:0 initid<7:0> region<3:0> c m d < 2 : 0 > 0000 b424 sbt13elog2 31:16 0000 15:0 group<1:0> 0000 b428 sbt13econ 31:16 errp 0000 15:0 0000 b430 sbt13eclrs 31:16 0000 15:0 c l e a r 0000 b438 sbt13eclrm 31:16 0000 15:0 c l e a r 0000 b440 sbt13reg0 31:16 base<21:6> xxxx 15:0 base<5:0> pri s i z e < 4 : 0 > xxxx b450 sbt13rd0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx b458 sbt13wr0 31:16 xxxx 15:0 group3 group2 group1 group0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note: for reset values listed as xxxx , please refer to table 4-6 for the actual reset values.
? 2015-2016 microchip technology inc. ds60001320d-page 91 pic32mz embedded connectivity with floating point unit (ef) family register 4-2: sbflag: system bus status flag register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 t13pgv t12pgv t11pgv t10pgv t9pgv t8pgv 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 t7pgv t6pgv t5pgv t4pgv t3pgv t2pgv t1pgv t0pgv legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared bit 31-14 unimplemented: read as 0 bit 13-0 txpgv: target x permission group violation status bits (x = 0-13) refer to table 4-6 for the list of available targets and their descriptions. 1 = target is reporting a permission group (pg) violation 0 = target is not reporting a pg violation note: all errors are cleared at the source (i.e., sbtxelog1, sbtxelog2, sbtxeclrs, or sbtxeclrm registers).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 92 ? 2015-2016 microchip technology inc. register 4-3: sbtxelog1: system bus target x error log register 1 ? (x = 0-13) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0, c u-0 u-0 u-0 r/w-0, c r/w-0, c r/w-0, c r/w-0, c multi c o d e < 3 : 0 > 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 initid<7:0> 7:0 r-0 r-0 r-0 r-0 u-0 r-0 r-0 r-0 region<3:0> c m d < 2 : 0 > legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared bit 31 multi: multiple permission violations status bit this bit is cleared by writing a 1 . 1 = multiple errors have been detected 0 = no multiple errors have been detected bit 30-28 unimplemented: read as 0 bit 27-24 code<3:0>: error code bits indicates the type of error that was detected. these bits are cleared by writing a 1 . 1111 = reserved 1101 = reserved 0011 = permission violation 0010 = reserved 0001 = reserved 0000 = no error bit 23-16 unimplemented: read as 0 bit 15-8 initid<7:0>: initiator id of requester bits 11111111 = reserved 00001111 = reserved 00001110 = crypto engine 00001101 = flash controller 00001100 = sqi1 00001011 = can2 00001010 = can1 00001001 = ethernet write 00001000 = ethernet read 00000111 = usb 00000110 = dma write (dmapr i (cfgcon<25>) = 1 ) 00000101 = dma write (dmapr i (cfgcon<25>) = 0 ) 00000100 = dma read (dmapri (cfgcon<25>) = 1 ) 00000011 = dma read (dmapri (cfgcon<25>) = 0 ) 00000010 = cpu (cpupri (cfgcon<24>) = 1 ) 00000001 = cpu (cpupri (cfgcon<25>) = 0 ) 00000000 = reserved note: refer to table 4-6 for the list of available targets and their descriptions.
? 2015-2016 microchip technology inc. ds60001320d-page 93 pic32mz embedded connectivity with floating point unit (ef) family bit 7-4 region<3:0>: requested region number bits 1111 - 0000 = targets region that reported a permission group violation bit 3 unimplemented: read as 0 bit 2-0 cmd<2:0>: transaction command of the requester bits 111 = reserved 110 = reserved 101 = write (a non-posted write) 100 = reserved 011 = read (a locked read caused by a read-modify-write transaction) 010 = read 001 = write 000 = idle register 4-3: sbtxelog1: system bus target x error log register 1 ? (x = 0-13) (continued) note: refer to table 4-6 for the list of available targets and their descriptions.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 94 ? 2015-2016 microchip technology inc. register 4-4: sbtxelog2: system bus target x error log register 2 (x = 0-13) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 r-0 group<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared bit 31-3 unimplemented: read as 0 bit 1-0 group<1:0>: requested permissions group bits 11 = group 3 10 = group 2 01 = group 1 00 = group 0 note: refer to table 4-6 for the list of available targets and their descriptions. register 4-5: sbtxecon: system bus target x error control register ? (x = 0-13) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 errp 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared bit 31-25 unimplemented: read as 0 bit 24 errp: error control bit 1 = report protection group violation errors 0 = do not report protection group violation errors bit 23-0 unimplemented: read as 0 note: refer to table 4-6 for the list of available targets and their descriptions.
? 2015-2016 microchip technology inc. ds60001320d-page 95 pic32mz embedded connectivity with floating point unit (ef) family register 4-6: sbtxeclrs: system bus t arget x single error clear register ? (x = 0-13) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 clear legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared bit 31-1 unimplemented: read as 0 bit 0 clear: clear single error on read bit a single error as reported via sbtxelog1 and sbtxelog2 is cleared by a read of this register. note: refer to table 4-6 for the list of available targets and their descriptions. register 4-7: sbtxeclrm: system bus t arget x multiple error clear register (x = 0-13) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 clear legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared bit 31-1 unimplemented: read as 0 bit 0 clear: clear multiple errors on read bit multiple errors as reported via sbtxelog1 and sbtxelog2 is cleared by a read of this register. note: refer to table 4-6 for the list of available targets and their descriptions.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 96 ? 2015-2016 microchip technology inc. register 4-8: sbtxregy: system bus target x region y register ? (x = 0-13; y = 0-8) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 base<21:14> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 base<13:6> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 u-0 base<5:0> pri 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 size<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared bit 31-10 base<21:0>: region base address bits bit 9 pri: region priority level bit 1 = level 2 0 = level 1 bit 8 unimplemented: read as 0 bit 7-3 size<4:0>: region size bits permissions for a region are only active is the size is non-zero. 11111 = region size = 2 (size C 1) x 1024 (bytes) 00001 = region size = 2 (size C 1) x 1024 (bytes) 00000 = region is not present bit 2-0 unimplemented: read as 0 note 1: refer to table 4-6 for the list of available targets and their descriptions. 2: for some target regions, certain bits in this register are read-only with preset values. see table 4-6 for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 97 pic32mz embedded connectivity with floating point unit (ef) family register 4-9: sbtxrdy: system bus t arget x region y read permissions register (x = 0-13; y = 0-8) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-1 r/w-1 r/w-1 group3 group2 group1 group0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared bit 31-4 unimplemented: read as 0 bit 3 group3: group3 read permissions bits 1 = privilege group 3 has read permission 0 = privilege group 3 does not have read permission bit 2 group2: group2 read permissions bits 1 = privilege group 2 has read permission 0 = privilege group 2 does not have read permission bit 1 group1: group1 read permissions bits 1 = privilege group 1 has read permission 0 = privilege group 1 does not have read permission bit 0 group0: group0 read permissions bits 1 = privilege group 0 has read permission 0 = privilege group 0 does not have read permission note 1: refer to table 4-6 for the list of available targets and their descriptions. 2: for some target regions, certain bits in this register are read-only with preset values. see table 4-6 for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 98 ? 2015-2016 microchip technology inc. register 4-10: sbtxwry: system bus target x region y write permissions register (x = 0-13; y = 0-8) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-1 r/w-1 r/w-1 group3 group2 group1 group0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared bit 31-4 unimplemented: read as 0 bit 3 group3: group 3 write permissions bits 1 = privilege group 3 has write permission 0 = privilege group 3 does not have write permission bit 2 group2: group 2 write permissions bits 1 = privilege group 2 has write permission 0 = privilege group 2 does not have write permission bit 1 group1: group 1 write permissions bits 1 = privilege group 1 has write permission 0 = privilege group 1 does not have write permission bit 0 group0: group 0 write permissions bits 1 = privilege group 0 has write permission 0 = privilege group 0 does not have write permission note 1: refer to table 4-6 for the list of available targets and their descriptions. 2: for some target regions, certain bits in this register are read-only with preset values. see table 4-6 for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 99 pic32mz embedded connectivity with floating point unit (ef) family 5.0 flash program memory pic32mz ef devices contain an internal flash program memory for executing user code, which includes the following features: two flash banks for live update support dual boot support write protection for program and boot flash ecc support there are three methods by which the user can program this memory: run-time self-programming (rtsp) ejtag programming in-circuit serial programming? (icsp?) rtsp is performed by software executing from either flash or ram memory. information about rtsp techniques is available in section 52. flash program memory with support for live update (ds60001193) in the ?pic32 family reference manual?. ejtag is performed using the ejtag port of the device and an ejtag capable programmer. icsp is performed using a serial data connection to the device and allows much faster programming times than rtsp. the ejtag and icsp methods are described in the ?pic32 flash programming specification? (ds60001145), which is available for download from the microchip web site ( www.microchip.com ). note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive refer - ence source. to complement the informa - tion in this data sheet, refer to section 52. flash program memory with support for live update (ds60001193) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). note: in pic32mz ef devices, the flash page size is 16 kb (4k iw) and the row size is 2 kb (512 iw).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 100 ? 2015-2016 microchip technology inc. 5.1 flash control registers table 5-1: flash controller register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0600 nvmcon (1) 31:16 0000 15:0 wr wren wrerr lvderr pfswap bfswap nvmop<3:0> 00x0 0610 nvmkey 31:16 nvmkey<31:0> 0000 15:0 0000 0620 nvmaddr (1) 31:16 nvmaddr<31:0> 0000 15:0 0000 0630 nvmdata0 31:16 nvmdata0<31:0> 0000 15:0 0000 0640 nvmdata1 31:16 nvmdata1<31:0> 0000 15:0 0000 0650 nvmdata2 31:16 nvmdata2<31:0> 0000 15:0 0000 0660 nvmdata3 31:16 nvmdata3<31:0> 0000 15:0 0000 0670 nvmsrc addr 31:16 nvmsrcaddr<31:0> 0000 15:0 0000 0680 nvmpwp (1) 31:16 pwpulock pwp<23:16> 8000 15:0 pwp<15:0> 0000 0690 nvmbwp (1) 31:16 0000 15:0 lbwpulock lbwp4 lbwp3 lbwp2 lbwp1 lbwp0 ubwpulock ubwp4 ubwp3 ubwp2 ubwp1 ubwp0 9fdf 06a0 nvmcon2 (1) 31:16 001f 15:0 swaplock<1:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 101 pic32mz embedded connectivity with floating point unit (ef) family register 5-1: nvmcon: flash pr ogramming control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0, hc r/w-0 r-0, hs, hc r-0, hs, hc u-0 u-0 u-0 u-0 wr (1) wren (1) wrerr (1) lvderr (1) 7:0 r/w-0 r/w-x u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 pfswap bfswap n v m o p < 3 : 0 > legend: hc = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 wr: write control bit (1) this bit cannot be cleared and can be set only when wren = 1 and the unlock sequence has been performed. 1 = initiate a flash operation 0 = flash operation is complete or inactive bit 14 wren: write enable bit (1) 1 = enable writes to the wr bit and disables writes to the nvmop<3:0> bits 0 = disable writes to wr bit and enables writes to the nvmop<3:0> bits bit 13 wrerr: write error bit (1) this bit can be cleared only by setting the nvmop<3:0> bits = 0000 and initiating a flash operation. 1 = program or erase sequence did not complete successfully 0 = program or erase sequence completed normally bit 12 lvderr: low-voltage detect error bit (1) this bit can be cleared only by setting the nvmop<3:0> bits = 0000 and initiating a flash operation. 1 = low-voltage detected (possible data corruption, if wrerr is set) 0 = voltage level is acceptable for programming bit 11-8 unimplemented: read as 0 bit 7 pfswap: program flash bank swap control bit this bit is only writable when wren = 0 and the unlock sequence has been performed. 1 = program flash bank 2 is mapped to the lower mapped region and program flash bank 1 is mapped to the upper mapped region 0 = program flash bank 1 is mapped to the lower mapped region and program flash bank 2 is mapped to the upper mapped region note 1: these bits are only reset by a power-on reset (por) and are not affected by other reset sources. 2: this operation results in a no operation ( nop ) when the dynamic flash ecc configuration bits = 00 (fecccon<1:0> (dvcfg0<9:8>)), which enables ecc at all times. for all other fecccon<1:0> bit settings, this command will execute, but will not write the ecc bits for the word and can cause ded errors if dynamic flash ecc is enabled (fecccon<1:0> = 01 ). refer to section 52. flash program memory with support for live update (ds60001193) for information regarding ecc and flash programming.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 102 ? 2015-2016 microchip technology inc. bit 6 bfswap: boot flash bank alias swap control bit this bit is only writable when wren = 0 and the unlock sequence has been performed. 1 = boot flash bank 2 is mapped to the lower boot alias and boot flash bank 1 is mapped to the upper boot alias 0 = boot flash bank 1 is mapped to the lower boot alias and boot flash bank 2 is mapped to the upper boot alias bit 5-4 unimplemented: read as 0 bit 3-0 nvmop<3:0>: nvm operation bits these bits are only writable when wren = 0 . 1111 = reserved 1000 = reserved 0111 = program erase operation: erase all of program flash memory (all pages must be unprotected, ? pwp<23:0> = 0x000000) 0110 = upper program flash memory erase operation: erases only the upper mapped region of program flash (all pages in that region must be unprotected) 0101 = lower program flash memory erase operation: erases only the lower mapped region of program flash (all pages in that region must be unprotected) 0100 = page erase operation: erases page selected by nvmaddr, if it is not write-protected 0011 = row program operation: programs row selected by nvmaddr, if it is not write-protected 0010 = quad word (128-bit) program operation: programs the 128-bit flash word se lected by nvmaddr, ? if it is not write-protected 0001 = word program operation: programs word selected by nvmaddr, if it is not wri te-protected (2) 0000 = no operation register 5-1: nvmcon: flash program ming control register (continued) note 1: these bits are only reset by a power-on reset (por) and are not affected by other reset sources. 2: this operation results in a no operation ( nop ) when the dynamic flash ecc configuration bits = 00 (fecccon<1:0> (dvcfg0<9:8>)), which enables ecc at all times. for all other fecccon<1:0> bit settings, this command will execute, but will not write the ecc bits for the word and can cause ded errors if dynamic flash ecc is enabled (fecccon<1:0> = 01 ). refer to section 52. flash program memory with support for live update (ds60001193) for information regarding ecc and flash programming.
? 2015-2016 microchip technology inc. ds60001320d-page 103 pic32mz embedded connectivity with floating point unit (ef) family register 5-2: nvmcon2: flash programming control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 swaplock<1:0> legend: hc = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as 0 bit 7-6 swaplock<1:0>: flash memory swap lock control bits 11 = pfswap and bfswap are not writable and swaplock is not writable 10 = pfswap and bfswap are not writable and swaplock is writable 01 = pfswap and bfswap are not writable and swaplock is writable 00 = pfswap and bfswap are writable and swaplock is writable bit 5-0 unimplemented: read as 0
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 104 ? 2015-2016 microchip technology inc. register 5-3: nvmkey: programming unlock register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<31:24> 23:16 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<23:16> 15:8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<15:8> 7:0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 nvmkey<31:0>: unlock register bits these bits are write-only, and read as 0 on any read note: this register is used as part of the unlock sequence to prevent inadvertent writes to the pfm. register 5-4: nvmaddr: flash address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<31:24> (1) 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<23:16> (1) 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<15:8> (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<7:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 nvmaddr<31:0>: flash address bits (1) note: the bits in this register are only reset by a power-on reset (por) and are not affected by other reset sources. nvmop<3:0> selection flash address bits (nvmaddr<31:0>) page erase address identifies the page to erase (nvmaddr<13:0> are ignored). row program address identifies the row to program (nvmaddr<10:0> are ignored). word program address identifies the word to program (nvmaddr<1:0> are ign ored). quad word program address identifies the quad word (128-bit) to progra m (nvmaddr<3:0> bits are ignored). note 1: for all other nvmop<3:0> bit settings, the flash address is ignored. see the nvmcon register ( register 5-1 ) for additional information on these bits.
? 2015-2016 microchip technology inc. ds60001320d-page 105 pic32mz embedded connectivity with floating point unit (ef) family register 5-5: nvmdatax: flash data register (x = 0-3) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 nvmdata<31:0>: flash data bits word program: writes nvmdata0 to the target flash address defined in nvmaddr quad word program: writes nvmdata3:nvmdata2:nvmdata1:nvmdata0 to the target flash address defined in nvmaddr. nvmdata0 contains the least significant instruction word. note: the bits in this register are only reset by a power-on reset (por) and are not affected by other reset sources. register 5-6: nvmsrcaddr: source data address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 nvmsrcaddr<31:0>: source data address bits the system physical address of the data to be programmed into the flash when the nvmop<3:0> bits (nvmcon<3:0>) are set to perform row programming. note: the bits in this register are only reset by a power-on reset (por) and are not affected by other reset sources.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 106 ? 2015-2016 microchip technology inc. register 5-7: nvmpwp: program flash write-protect register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 pwpulock 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pwp<23:16> 15:8 r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 pwp<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 pwp<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 pwpulock: program flash memory page write-protect unlock bit 1 = register is not locked and can be modified 0 = register is locked and cannot be modified this bit is only clearable and cannot be set except by any reset. bit 30-24 unimplemented: read as 0 bit 23-0 pwp<23:0>: flash program write-protect (page) address bits physical memory below address 0x1dxxxxxx is write protected, where xxxxxx is specified by pwp<23:0>. when pwp<23:0> has a value of 0 , write protection is disabled for the entire program flash. if the specified address falls within the page, the entire page and all pages below the current page will be protected. note: the bits in this register are only writable when the nvmkey unlock sequence is followed.
? 2015-2016 microchip technology inc. ds60001320d-page 107 pic32mz embedded connectivity with floating point unit (ef) family register 5-8: nvmbwp: flash boot (page) write-protect register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-1 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 lbwpulock lbwp4 (1) lbwp3 (1) lbwp2 (1) lbwp1 (1) lbwp0 (1) 7:0 r/w-1 r-1 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ubwpulock ubwp4 (1) ubwp3 (1) ubwp2 (1) ubwp1 (1) ubwp0 (1) legend: r = reserved r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 lbwpulock: lower boot alias write-protect unlock bit 1 = lbwpx bits are not locked and can be modified 0 = lbwpx bits are locked and cannot be modified this bit is only clearable and cannot be set except by any reset. bit 14-13 unimplemented: read as 0 bit 12 lbwp4: lower boot alias page 4 write-protect bit (1) 1 = write protection for physical address 0x01fc10000 through 0x1fc13fff enabled 0 = write protection for physical address 0x01fc10000 through 0x1fc13fff disabled bit 11 lbwp3: lower boot alias page 3 write-protect bit (1) 1 = write protection for physical address 0x01fc0c000 through 0x1fc0ffff enabled 0 = write protection for physical address 0x01fc0c000 through 0x1fc0ffff disabled bit 10 lbwp2: lower boot alias page 2 write-protect bit (1) 1 = write protection for physical address 0x01fc08000 through 0x1fc0bfff enabled 0 = write protection for physical address 0x01fc08000 through 0x1fc0bfff disabled bit 9 lbwp1: lower boot alias page 1 write-protect bit (1) 1 = write protection for physical address 0x01fc04000 through 0x1fc07fff enabled 0 = write protection for physical address 0x01fc04000 through 0x1fc07fff disabled bit 8 lbwp0: lower boot alias page 0 write-protect bit (1) 1 = write protection for physical address 0x01fc00000 through 0x1fc03fff enabled 0 = write protection for physical address 0x01fc00000 through 0x1fc03fff disabled bit 7 ubwpulock: upper boot alias write-protect unlock bit 1 = ubwpx bits are not locked and can be modified 0 = ubwpx bits are locked and cannot be modified this bit is only user-clearable and cannot be set except by any reset. bit 6 reserved: this bit is reserved for use by development tools bit 5 unimplemented: read as 0 note 1: these bits are only available when the nvmkey unlock sequence is performed and the associated lock bit (lbwpulock or ubwpulock) is set. note: the bits in this register are only writable when the nvmkey unlock sequence is followed.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 108 ? 2015-2016 microchip technology inc. bit 4 ubwp4: upper boot alias page 4 write-protect bit (1) 1 = write protection for physical address 0x01fc30000 through 0x1fc33fff enabled 0 = write protection for physical address 0x01fc30000 through 0x1fc33fff disabled bit 3 ubwp3: upper boot alias page 3 write-protect bit (1) 1 = write protection for physical address 0x01fc2c000 through 0x1fc2ffff enabled 0 = write protection for physical address 0x01fc2c000 through 0x1fc2ffff disabled bit 2 ubwp2: upper boot alias page 2 write-protect bit (1) 1 = write protection for physical address 0x01fc28000 through 0x1fc2bfff enabled 0 = write protection for physical address 0x01fc28000 through 0x1fc2bfff disabled bit 1 ubwp1: upper boot alias page 1 write-protect bit (1) 1 = write protection for physical address 0x01fc24000 through 0x1fc27fff enabled 0 = write protection for physical address 0x01fc24000 through 0x1fc27fff disabled bit 0 ubwp0: upper boot alias page 0 write-protect bit (1) 1 = write protection for physical address 0x01fc20000 through 0x1fc23fff enabled 0 = write protection for physical address 0x01fc20000 through 0x1fc23fff disabled register 5-8: nvmbwp: flash boot (page) write-protect register note 1: these bits are only available when the nvmkey unlock sequence is performed and the associated lock bit (lbwpulock or ubwpulock) is set. note: the bits in this register are only writable when the nvmkey unlock sequence is followed.
? 2015-2016 microchip technology inc. ds60001320d-page 109 pic32mz embedded connectivity with floating point unit (ef) family 6.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst. the device reset sources are as follows: power-on reset (por) master clear reset pin ( mclr ) software reset (swr) watchdog timer reset (wdtr) brown-out reset (bor) configuration mismatch reset (cmr) deadman timer reset (dmtr) a simplified block diagram of the reset module is illustrated in figure 6-1 . figure 6-1: system reset block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive refer - ence source. to complement the informa - tion in this data sheet, refer to section 7. resets (ds60001118) in the ?pic32 family reference manual? , which is avail - able from the microchip web site ( www.microchip.com/pic32 ). mclr v dd v dd rise detect por sleep or idle dmt time-out glitch filter bor configuration sysrst software reset power-up timer voltage regulator enabled reset dmtr/wdtr swr cmr mclr mismatch nmi time-out wdt time-out brown-out reset
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 110 ? 2015-2016 microchip technology inc. 6.1 reset control registers table 6-1: resets register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1240 rcon 31:16 bcfgerr bcfgfail 0x00 15:0 cmr extr swr dmto wdto sleep idle bor por 0003 1250 rswrst 31:16 0000 15:0 swrst 0000 1260 rnmicon 31:16 dmto wdto swnmi gnmi cf wdts 0000 15:0 nmicnt<15:0> 0000 1270 pwrcon 31:16 0000 15:0 vregs 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers have corresponding clr, set and inv registers at their vi rtual addresses, plus offsets of 0x4, 0x8 and 0xc, respe ctively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 111 pic32mz embedded connectivity with floating point unit (ef) family register 6-1: rcon: re set control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 r/w-0, hs r/w-0, hs u-0 u-0 bcfgerr bcfgfail 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0, hs u-0 c m r 7:0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-1, hs r/w-1, hs extr swr dmto wdto sleep idle bor (1) por (1) legend: hs = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-28 unimplemented: read as 0 bit 27 bcfgerr: primary configuration registers error flag bit 1 = an error occurred during a read of the primary configuration registers 0 = no error occurred during a read of the primary configuration registers bit 26 bcfgfail: primary/secondary configuration registers error flag bit 1 = an error occurred during a read of the primary and alternate configuration registers 0 = no error occurred during a read of the primary and alternate configuration registers bit 25-10 unimplemented: read as 0 bit 9 cmr: configuration mismatch reset flag bit 1 = a configuration mismatch reset has occurred 0 = a configuration mismatch reset has not occurred bit 8 unimplemented: read as 0 bit 7 extr: external reset (mclr ) pin flag bit 1 = master clear (pin) reset has occurred 0 = master clear (pin) reset has not occurred bit 6 swr: software reset flag bit 1 = software reset was executed 0 = software reset was not executed bit 5 dmto: deadman timer time-out flag bit 1 = a dmt time-out has occurred 0 = a dmt time-out has not occurred bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred bit 3 sleep: wake from sleep flag bit 1 = device was in sleep mode 0 = device was not in sleep mode bit 2 idle: wake from idle flag bit 1 = device was in idle mode 0 = device was not in idle mode bit 1 bor: brown-out reset flag bit (1) 1 = brown-out reset has occurred 0 = brown-out reset has not occurred bit 0 por: power-on reset flag bit (1) 1 = power-on reset has occurred 0 = power-on reset has not occurred note 1: user software must clear this bit to view the next detection.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 112 ? 2015-2016 microchip technology inc. register 6-2: rswrst: software reset register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 w-0, hc s w r s t (1,2) legend: hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-1 unimplemented: read as 0 bit 0 swrst: software reset trigger bit (1,2) 1 = enable software reset event 0 = no effect note 1: the system unlock sequence must be performed before the swrst bit can be written. refer to section 42. oscillators with enhanced pll in the ?pic32 family reference manual? for details. 2: once this bit is set, any read of the rswrst register will cause a reset to occur.
? 2015-2016 microchip technology inc. ds60001320d-page 113 pic32mz embedded connectivity with floating point unit (ef) family register 6-3: rnmicon: non-maskable interrupt (nmi) control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 d m t ow d t o 23:16 r/w-0 u-0 u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 swnmi g n m i c fw d t s 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nmicnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nmicnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-26 unimplemented: read as 0 bit 25 dmto: deadman timer time-out flag bit 1 = dmt time-out has occurred and caused a nmi 0 = dmt time-out has not occurred setting this bit will cause a dmt nmi event, and nmicnt will begin counting. bit 24 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred and caused a nmi 0 = wdt time-out has not occurred setting this bit will cause a wdt nmi event, and mnicnt will begin counting. bit 23 swnmi: software nmi trigger. 1 = an nmi will be generated 0 = an nmi will not be generated bit 22-20 unimplemented: read as 0 bit 19 gnmi: general nmi bit 1 = a general nmi event has been detected or a user-initiated nmi event has occurred 0 = a general nmi event has not been detected setting gnmi to a 1 causes a user-initiated nmi event. this bit is also set by writing 0x4e to the nmikey<7:0> (intcon<31:24>) bits. bit 18 unimplemented: read as 0 bit 17 cf: clock fail detect bit 1 = fscm has detected clock failure and caused an nmi 0 = fscm has not detected clock failure setting this bit will cause a a cf nmi event, but will not cause a clock switch to the bfrc. bit 16 wdts: watchdog timer time-out in sleep mode flag bit 1 = wdt time-out has occurred during sleep mode and caused a wake-up from sleep 0 = wdt time-out has not occurred during sleep mode setting this bit will cause a wdt nmi. bit 15-0 nmicnt<15:0>: nmi reset counter value bits 1111111111111111 - 0000000000000001 = number of sysclk cycles before a device reset occurs (1) 0000000000000000 = no delay between nmi assertion and device reset event note 1: when a watchdog timer nmi event (when not in sleep mode) or a deadman timer nmi event is triggered the nmicnt will start decrementing. when nmicnt reaches zero, the device is reset. this nmi reset counter is only applicable to these two specific nmi events. note: the system unlock sequence must be performed before the swrst bit can be written. refer to section 42. oscillators with enhanced pll in the ?pic32 family reference manual? for details.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 114 ? 2015-2016 microchip technology inc. register 6-4: pwrcon: power control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 v r e g s legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-1 unimplemented: read as 0 bit 0 vregs: voltage regulator stand-by enable bit 1 = voltage regulator will remain active during sleep 0 = voltage regulator will go to stand-by mode during sleep
? 2015-2016 microchip technology inc. ds60001320d-page 115 pic32mz embedded connectivity with floating point unit (ef) family 7.0 cpu exceptions and interrupt controller pic32mz ef devices generate interrupt requests in response to interrupt events from peripheral modules. the interrupt controller module exists outside of the cpu and prioritizes the interrupt events before presenting them to the cpu. the cpu handles interrupt events as part of the excep - tion handling mechanism, which is described in section 7.1 cpu exceptions . the interrupt controller module includes the following features: up to 213 interrupt sources and vectors with dedicated programmable offsets, eliminating the need for redirection single and multi-vector mode operations five external interrupts with edge polarity control interrupt proximity timer seven user-selectable priority levels for each vector four user-selectable subpriority levels within each priority seven shadow register sets that can be used for any priority level, eliminating software context switch and reducing interrupt latency software can generate any interrupt figure 7-1 shows the block diagram for the interrupt controller and cpu exceptions. figure 7-1: cpu exceptions and interrupt controller module block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 8. interrupt controller (ds60001108) and section 50. cpu for devices with mips32 ? microaptiv? and m-class cores (ds60001192) of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). interrupt controller interrupt requests vector number and offset cpu core priority level shadow set number sysclk (exception handling)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 116 ? 2015-2016 microchip technology inc. 7.1 cpu exceptions cpu coprocessor 0 contains the logic for identifying and managing exceptions. exceptions can be caused by a variety of sources, including boundary cases in data, external events or program errors. table 7-1 lists the exception types in order of priority. table 7-1: mips32 ? m-class microprocessor core exception types exception type (in order of priority) description branches to status bits set debug bits set exccode xc32 function name highest priority reset assertion mclr or a power-on reset (por). 0xbfc0_0000 bev, erl _on_reset soft reset assertion of a software reset. 0xbfc0_0000 bev, sr, erl _on_reset dss ejtag debug single step. 0xbfc0_0480 dss dint ejtag debug interrupt. caused by the assertion of the external ej_dint input or by setting the ejtagbrk bit in the ecr register. 0xbfc0_0480 dint nmi assertion of nmi signal. 0xbfc0_0000 bev, nmi, erl _nmi_handler machine check tlb write that conflicts with an existing entry. ebase+0x180 mcheck, exl 0x18 _general_exception_handler interrupt assertion of unmasked hardware or software inter - rupt signal. see table 7-2 . ipl<2:0> 0x00 see ta b l e 7-2 . deferred watch deferred watch (unmasked by k|dm=>!(k|dm) transition). ebase+0x180 wp, exl 0x17 _general_exception_handler dib ejtag debug hardware instruction break matched. 0xbfc0_0480 dib watch a reference to an address that is in one of the watch registers (fetch). ebase+0x180 exl 0x17 _general_exception_handler adel fetch address alignment error. fetch reference to protected address. ebase+0x180 exl 0x04 _general_exception_handler tlbl fetch tlb miss or fetch tlb hit to page with v = 0. ebase if status.exl = 0 0x02 ebase+0x180 if status.exl == 1 0x02 _general_exception_handler tlbl execute inhibit an instruction fetch matched a valid tlb entry that had the xi bit set. ebase+0x180 exl 0x14 _general_exception_handler ibe instruction fetch bus error. ebase+0x180 exl 0x06 _general_exception_handler
? 2015-2016 microchip technology inc. ds60001320d-page 117 pic32mz embedded connectivity with floating point unit (ef) family instruction validity exceptions an instruction could not be completed because it was not allowed to access the required resources (coprocessor unusable) or was illegal (reserved instruction). if both exceptions occur on the same instruction, the coprocessor unusable exception takes priority over the reserved instruction exception. ebase+0x180 exl 0x0a or 0x0b _general_exception_handler execute exception an instruction-based exception occurred: integer overflow, trap, system call, breakpoint, floating point, or dsp ase state disabled exception. ebase+0x180 exl 0x08-0x0c _general_exception_handler tr execution of a trap (when trap condition is true). ebase+0x180 exl 0x0d _general_exception_handler ddbl/ddbs ejtag data address break (address only) or ejtag data value break on store (address + value). 0xbfc0_0480 ddbl or ddbs watch a reference to an address that is in one of the watch registers (data). ebase+0x180 exl 0x17 _general_exception_handler adel load address alignment error. user mode load reference to kernel address. ebase+0x180 exl 0x04 _general_exception_handler ades store address alignment error. user mode store to kernel address. ebase+0x180 exl 0x05 _general_exception_handler tlbl load tlb miss or load tlb hit to page with v = 0. ebase+0x180 exl 0x02 _general_exception_handler tlbs store tlb miss or store tlb hit to page with v = 0. ebase+0x180 exl 0x03 _general_exception_handler dbe load or store bus error. ebase+0x180 exl 0x07 _general_exception_handler ddbl ejtag data hardware breakpoint matched in load data compare. 0xbfc0_0480 ddbl cbrk ejtag complex breakpoint. 0xbfc0_0480 dibimpr, ddblimpr, and/or ddbsimpr lowest priority table 7-1: mips32 ? m-class microprocessor core exception types (continued) exception type (in order of priority) description branches to status bits set debug bits set exccode xc32 function name
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 118 ? 2015-2016 microchip technology inc. 7.2 interrupts the pic32mz ef family uses variable offsets for vector spacing. this allows the interrupt vector spacing to be configured according to application needs. a unique interrupt vector offset can be set for each vector using its associated offx register. for details on the variable offset feature, refer to 8.5.2 variable offset in section 8. interrupt controller (ds60001108) of the ?pic32 family reference manual? . tab l e 7-2 provides the interrupt irq, vector and bit location information. table 7-2: interrupt irq, vector, and bit location interrupt source (1) xc32 vector name irq # vector # interrupt bit location persistent interrupt flag enable priority sub-priority highest natural order priority core timer interrupt _core_timer_vector 0 off000<17:1> ifs0<0> iec0<0> ipc0<4:2> ipc0<1:0> no core software interrupt 0 _core_software_0_vector 1 off001<17:1> ifs0<1> iec0<1> ipc0<12:10> ipc0<9:8> no core software interrupt 1 _core_software_1_vector 2 off002<17:1> ifs0<2> iec0<2> ipc0<20:18> ipc0<17:16> no external interrupt 0 _external_0_vector 3 off003<17:1> ifs0<3> iec0<3> ipc0<28:26> ipc0<25:24> no timer1 _timer_1_vector 4 off004<17:1> ifs0<4> iec0<4> ipc1<4:2> ipc1<1:0> no input capture 1 error _input_capture_1_error_vector 5 off005<17:1> ifs0<5> iec0<5> ipc1<12:10> ipc1<9:8> yes input capture 1 _input_capture_1_vector 6 off006<17:1> ifs0<6> iec0<6> ipc1<20:18> ipc1<17:16> yes output compare 1 _output_compare_1_vector 7 off007<17:1> ifs0<7> iec0<7> ipc1<28:26> ipc1<25:24> no external interrupt 1 _external_1_vector 8 off008<17:1> ifs0<8> iec0<8> ipc2<4:2> ipc2<1:0> no timer2 _timer_2_vector 9 off009<17:1> ifs0<9> iec0<9> ipc2<12:10> ipc2<9:8> no input capture 2 error _input_capture_2_error_vector 10 off010<17:1> ifs0<10> iec0<10> ipc2<20:18> ipc2<17:16> yes input capture 2 _input_capture_2_vector 11 off011<17:1> ifs0<11> iec0<11> ipc2<28:26> ipc2<25:24> yes output compare 2 _output_compare_2_vector 12 off012<17:1> ifs0<12> iec0<12> ipc3<4:2> ipc3<1:0> no external interrupt 2 _external_2_vector 13 off013<17:1> ifs0<13> iec0<13> ipc3<12:10> ipc3<9:8> no timer3 _timer_3_vector 14 off014<17:1> ifs0<14> iec0<14> ipc3<20:18> ipc3<17:16> no input capture 3 error _input_capture_3_error_vector 15 off015<17:1> ifs0<15> iec0<15> ipc3<28:26> ipc3<25:24> yes input capture 3 _input_capture_3_vector 16 off016<17:1> ifs0<16> iec0<16> ipc4<4:2> ipc4<1:0> yes output compare 3 _output_compare_3_vector 17 off017<17:1> ifs0<17> iec0<17> ipc4<12:10> ipc4<9:8> no external interrupt 3 _external_3_vector 18 off018<17:1> ifs0<18> iec0<18> ipc4<20:18> ipc4<17:16> no timer4 _timer_4_vector 19 off019<17:1> ifs0<19> iec0<19> ipc4<28:26> ipc4<25:24> no input capture 4 error _input_capture_4_error_vector 20 off020<17:1> ifs0<20> iec0<20> ipc5<4:2> ipc5<1:0> yes input capture 4 _input_capture_4_vector 21 off021<17:1> ifs0<21> iec0<21> ipc5<12:10> ipc5<9:8> yes note 1: not all interrupt sources are available on all devices. see table 1: pic32mz ef family features for the list of available peripherals. 2: this interrupt source is not available on 64-pin devices. 3: this interrupt source is not available on 100-pin devices. 4: this interrupt source is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 119 pic32mz embedded connectivity with floating point unit (ef) family output compare 4 _output_compare_4_vector 22 off022<17:1> ifs0<22> iec0<22> ipc5<20:18> ipc5<17:16> no external interrupt 4 _external_4_vector 23 off023<17:1> ifs0<23> iec0<23> ipc5<28:26> ipc5<25:24> no timer5 _timer_5_vector 24 off024<17:1> ifs0<24> iec0<24> ipc6<4:2> ipc6<1:0> no input capture 5 error _input_capture_5_error_vector 25 off025<17:1> ifs0<25> iec0<25> ipc6<12:10> ipc6<9:8> yes input capture 5 _input_capture_5_vector 26 off026<17:1> ifs0<26> iec0<26> ipc6<20:18> ipc6<17:16> yes output compare 5 _output_compare_5_vector 27 off027<17:1> ifs0<27> iec0<27> ipc6<28:26> ipc6<25:24> no timer6 _timer_6_vector 28 off028<17:1> ifs0<28> iec0<28> ipc7<4:2> ipc7<1:0> no input capture 6 error _input_capture_6_error_vector 29 off029<17:1> ifs0<29> iec0<29> ipc7<12:10> ipc7<9:8> yes input capture 6 _input_capture_6_vector 30 off030<17:1> ifs0<30> iec0<30> ipc7<20:18> ipc7<17:16> yes output compare 6 _output_compare_6_vector 31 off031<17:1> ifs0<31> iec0<31> ipc7<28:26> ipc7<25:24> no timer7 _timer_7_vector 32 off032<17:1> ifs1<0> iec1<0> ipc8<4:2> ipc8<1:0> no input capture 7 error _input_capture_7_error_vector 33 off033<17:1> ifs1<1> iec1<1> ipc8<12:10> ipc8<9:8> yes input capture 7 _input_capture_7_vector 34 off034<17:1> ifs1<2> iec1<2> ipc8<20:18> ipc8<17:16> yes output compare 7 _output_compare_7_vector 35 off035<17:1> ifs1<3> iec1<3> ipc8<28:26> ipc8<25:24> no timer8 _timer_8_vector 36 off036<17:1> ifs1<4> iec1<4> ipc9<4:2> ipc9<1:0> no input capture 8 error _input_capture_8_error_vector 37 off037<17:1> ifs1<5> iec1<5> ipc9<12:10> ipc9<9:8> yes input capture 8 _input_capture_8_vector 38 off038<17:1> ifs1<6> iec1<6> ipc9<20:18> ipc9<17:16> yes output compare 8 _output_compare_8_vector 39 off039<17:1> ifs1<7> iec1<7> ipc9<28:26> ipc9<25:24> no timer9 _timer_9_vector 40 off040<17:1> ifs1<8> iec1<8> ipc10<4:2> ipc10<1:0> no input capture 9 error _input_capture_9_error_vector 41 off041<17:1> ifs1<9> iec1<9> ipc10<12:10> ipc10<9:8> yes input capture 9 _input_capture_9_vector 42 off042<17:1> ifs1<10> iec1<10> ipc10<20:18> ipc10<17:16> yes output compare 9 _output_compare_9_vector 43 off043<17:1> ifs1<11> iec1<11> ipc10<28:26> ipc10<25:24> no adc global interrupt _adc_vector 44 off044<17:1> ifs1<12> iec1<12> ipc11<4:2> ipc11<1:0> yes adc fifo data ready interrupt _adc_fifo_vector 45 off045<17:1> ifs1<13> iec1<13> ipc11<12:10> ipc11<9:8> yes adc digital comparator 1 _adc_dc1_vector 46 off046<17:1> ifs1<14> iec1<14> ipc11<20:18> ipc11<17:16> yes adc digital comparator 2 _adc_dc2_vector 47 off047<17:1> ifs1<15> iec1<15> ipc11<28:26> ipc11<25:24> yes adc digital comparator 3 _adc_dc3_vector 48 off048<17:1> ifs1<16> iec1<16> ipc12<4:2> ipc12<1:0> yes adc digital comparator 4 _adc_dc4_vector 49 off049<17:1> ifs1<17> iec1<17> ipc12<12:10> ipc12<9:8> yes table 7-2: interrupt irq, vector, and bit location (continued) interrupt source (1) xc32 vector name irq # vector # interrupt bit location persistent interrupt flag enable priority sub-priority note 1: not all interrupt sources are available on all devices. see table 1: pic32mz ef family features for the list of available peripherals. 2: this interrupt source is not available on 64-pin devices. 3: this interrupt source is not available on 100-pin devices. 4: this interrupt source is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 120 ? 2015-2016 microchip technology inc. adc digital comparator 5 _adc_dc5_vector 50 off050<17:1> ifs1<18> iec1<18> ipc12<20:18> ipc12<17:16> yes adc digital comparator 6 _adc_dc6_vector 51 off051<17:1> ifs1<19> iec1<19> ipc12<28:26> ipc12<25:24> yes adc digital filter 1 _adc_df1_vector 52 off052<17:1> ifs1<20> iec1<20> ipc13<4:2> ipc13<1:0> yes adc digital filter 2 _adc_df2_vector 53 off053<17:1> ifs1<21> iec1<21> ipc13<12:10> ipc13<9:8> yes adc digital filter 3 _adc_df3_vector 54 off054<17:1> ifs1<22> iec1<22> ipc13<20:18> ipc13<17:16> yes adc digital filter 4 _adc_df4_vector 55 off055<17:1> ifs1<23> iec1<23> ipc13<28:26> ipc13<25:24> yes adc digital filter 5 _adc_df5_vector 56 off056<17:1> ifs1<24> iec1<24> ipc14<4:2> ipc14<1:0> yes adc digital filter 6 _adc_df6_vector 57 off057<17:1> ifs1<25> iec1<25> ipc14<12:10> ipc14<9:8> yes adc fault _adc_fault_vector 58 off058<17:1> ifs1<26> iec1<26> ipc14<20:18> ipc14<17:16> no adc data 0 _adc_data0_vector 59 off059<17:1> ifs1<27> iec1<27> ipc14<28:26> ipc14<25:24> yes adc data 1 _adc_data1_vector 60 off060<17:1> ifs1<28> iec1<28> ipc15<4:2> ipc15<1:0> yes adc data 2 _adc_data2_vector 61 off061<17:1> ifs1<29> iec1<29> ipc15<12:10> ipc15<9:8> yes adc data 3 _adc_data3_vector 62 off062<17:1> ifs1<30> iec1<30> ipc15<20:18> ipc15<17:16> yes adc data 4 _adc_data4_vector 63 off063<17:1> ifs1<31> iec1<31> ipc15<28:26> ipc15<25:24> yes adc data 5 _adc_data5_vector 64 off064<17:1> ifs2<0> iec2<0> ipc16<4:2> ipc16<1:0> yes adc data 6 _adc_data6_vector 65 off065<17:1> ifs2<1> iec2<1> ipc16<12:10> ipc16<9:8> yes adc data 7 _adc_data7_vector 66 off066<17:1> ifs2<2> iec2<2> ipc16<20:18> ipc16<17:16> yes adc data 8 _adc_data8_vector 67 off067<17:1> ifs2<3> iec2<3> ipc16<28:26> ipc16<25:24> yes adc data 9 _adc_data9_vector 68 off068<17:1> ifs2<4> iec2<4> ipc17<4:2> ipc17<1:0> yes adc data 10 _adc_data10_vector 69 off069<17:1> ifs2<5> iec2<5> ipc17<12:10> ipc17<9:8> yes adc data 11 _adc_data11_vector 70 off070<17:1> ifs2<6> iec2<6> ipc17<20:18> ipc17<17:16> yes adc data 12 _adc_data12_vector 71 off071<17:1> ifs2<7> iec2<7> ipc17<28:26> ipc17<25:24> yes adc data 13 _adc_data13_vector 72 off072<17:1> ifs2<8> iec2<8> ipc18<4:2> ipc18<1:0> yes adc data 14 _adc_data14_vector 73 off073<17:1> ifs2<9> iec2<9> ipc18<12:10> ipc18<9:8> yes adc data 15 _adc_data15_vector 74 off074<17:1> ifs2<10> iec2<10> ipc18<20:18> ipc18<17:16> yes adc data 16 _adc_data16_vector 75 off075<17:1> ifs2<11> iec2<11> ipc18<28:26> ipc18<25:24> yes adc data 17 _adc_data17_vector 76 off076<17:1> ifs2<12> iec2<12> ipc19<4:2> ipc19<1:0> yes adc data 18 _adc_data18_vector 77 off077<17:1> ifs2<13> iec2<13> ipc19<12:10> ipc19<9:8> yes table 7-2: interrupt irq, vector, and bit location (continued) interrupt source (1) xc32 vector name irq # vector # interrupt bit location persistent interrupt flag enable priority sub-priority note 1: not all interrupt sources are available on all devices. see table 1: pic32mz ef family features for the list of available peripherals. 2: this interrupt source is not available on 64-pin devices. 3: this interrupt source is not available on 100-pin devices. 4: this interrupt source is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 121 pic32mz embedded connectivity with floating point unit (ef) family adc data 19 (2) _adc_data19_vector 78 off078<17:1> ifs2<14> iec2<14> ipc19<20:18> ipc19<17:16> yes adc data 20 (2) _adc_data20_vector 79 off079<17:1> ifs2<15> iec2<15> ipc19<28:26> ipc19<25:24> yes adc data 21 (2) _adc_data21_vector 80 off080<17:1> ifs2<16> iec2<16> ipc20<4:2> ipc20<1:0> yes adc data 22 (2) _adc_data22_vector 81 off081<17:1> ifs2<17> iec2<17> ipc20<12:10> ipc20<9:8> yes adc data 23 (2) _adc_data23_vector 82 off082<17:1> ifs2<18> iec2<18> ipc20<20:18> ipc20<17:16> yes adc data 24 (2) _adc_data24_vector 83 off083<17:1> ifs2<19> iec2<19> ipc20<28:26> ipc20<25:24> yes adc data 25 (2) _adc_data25_vector 84 off084<17:1> ifs2<20> iec2<20> ipc21<4:2> ipc21<1:0> yes adc data 26 (2) _adc_data26_vector 85 off085<17:1> ifs2<21> iec2<21> ipc21<12:10> ipc21<9:8> yes adc data 27 (2) _adc_data27_vector 86 off086<17:1> ifs2<22> iec2<22> ipc21<20:18> ipc21<17:16> yes adc data 28 (2) _adc_data28_vector 87 off087<17:1> ifs2<23> iec2<23> ipc21<28:26> ipc21<25:24> yes adc data 29 (2) _adc_data29_vector 88 off088<17:1> ifs2<24> iec2<24> ipc22<4:2> ipc22<1:0> yes adc data 30 (2) _adc_data30_vector 89 off089<17:1> ifs2<25> iec2<25> ipc22<12:10> ipc22<9:8> yes adc data 31 (2) _adc_data31_vector 90 off090<17:1> ifs2<26> iec2<26> ipc22<20:18> ipc22<17:16> yes adc data 32 (2) _adc_data32_vector 91 off091<17:1> ifs2<27> iec2<27> ipc22<28:26> ipc22<25:24> yes adc data 33 (2) _adc_data33_vector 92 off092<17:1> ifs2<28> iec2<28> ipc23<4:2> ipc23<1:0> yes adc data 34 (2) _adc_data34_vector 93 off093<17:1> ifs2<29> iec2<29> ipc23<12:10> ipc23<9:8> yes adc data 35 (2,3) _adc_data35_vector 94 off094<17:1> ifs2<30> iec2<30> ipc23<20:18> ipc23<17:16> yes adc data 36 (2,3) _adc_data36_vector 95 off095<17:1> ifs2<31> iec2<31> ipc23<28:26> ipc23<25:24> yes adc data 37 (2,3) _adc_data37_vector 96 off096<17:1> ifs3<0> iec3<0> ipc24<4:2> ipc24<1:0> yes adc data 38 (2,3) _adc_data38_vector 97 off097<17:1> ifs3<1> iec3<1> ipc24<12:10> ipc24<9:8> yes adc data 39 (2,3) _adc_data39_vector 98 off098<17:1> ifs3<2> iec3<2> ipc24<20:18> ipc24<17:16> yes adc data 40 (2,3) _adc_data40_vector 99 off099<17:1> ifs3<3> iec3<3> ipc24<28:26> ipc24<25:24> yes adc data 41 (2,3) _adc_data41_vector 100 off100<17:1> ifs3<4> iec3<4> ipc25<4:2> ipc25<1:0> yes adc data 42 (2,3) _adc_data42_vector 101 off101<17:1> ifs3<5> iec3<5> ipc25<12:10> ipc25<9:8> yes adc data 43 _adc_data43_vector 102 off102<17:1> ifs3<6> iec3<6> ipc25<20:18> ipc25<17:16> yes adc data 44 _adc_data44_vector 103 off103<17:1> ifs3<7> iec3<7> ipc25<28:26> ipc25<25:24> yes core performance counter interrupt _core_perf_count_vector 104 off104<17:1> ifs3<8> iec3<8> ipc26<4:2> ipc26<1:0> no core fast debug channel interrupt _core_fast_debug_chan_vector 105 off105<17:1> ifs3<9> iec3<9> ipc26<12:10> ipc26<9:8> yes table 7-2: interrupt irq, vector, and bit location (continued) interrupt source (1) xc32 vector name irq # vector # interrupt bit location persistent interrupt flag enable priority sub-priority note 1: not all interrupt sources are available on all devices. see table 1: pic32mz ef family features for the list of available peripherals. 2: this interrupt source is not available on 64-pin devices. 3: this interrupt source is not available on 100-pin devices. 4: this interrupt source is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 122 ? 2015-2016 microchip technology inc. system bus protection violation _system_bus_protection_vector 106 off106<17:1> ifs3<10> iec3<10> ipc26<20:18> ipc26<17:16> yes crypto engine event _crypto_vector 107 off107<17:1> ifs3<11> iec3<11> ipc26<28:26> ipc26<25:24> yes reserved 108 spi1 fault _spi1_fault_vector 109 off109<17:1> ifs3<13> iec3<13> ipc27<12:10> ipc27<9:8> yes spi1 receive done _spi1_rx_vector 110 off110<17:1> ifs3<14> iec3<14> ipc27<20:18> ipc27<17:16> yes spi1 transfer done _spi1_tx_vector 111 off111<17:1> ifs3<15> iec3<15> ipc27<28:26> ipc27<25:24> yes uart1 fault _uart1_fault_vector 112 off112<17:1> ifs3<16> iec3<16> ipc28<4:2> ipc28<1:0> yes uart1 receive done _uart1_rx_vector 113 off113<17:1> ifs3<17> iec3<17> ipc28<12:10> ipc28<9:8> yes uart1 transfer done _uart1_tx_vector 114 off114<17:1> ifs3<18> iec3<18> ipc28<20:18> ipc28<17:16> yes i2c1 bus collision event _i2c1_bus_vector 115 off115<17:1> ifs3<19> iec3<19> ipc28<28:26> ipc28<25:24> yes i2c1 slave event _i2c1_slave_vector 116 off116<17:1> ifs3<20> iec3<20> ipc29<4:2> ipc29<1:0> yes i2c1 master event _i2c1_master_vector 117 off117<17:1> ifs3<21> iec3<21> ipc29<12:10> ipc29<9:8> yes porta input change interrupt (2) _change_notice_a_vector 118 off118<17:1> ifs3<22> iec3<22> ipc29<20:18> ipc29<17:16> yes portb input change interrupt _change_notice_b_vector 119 off119<17:1> ifs3<23> iec3<23> ipc29<28:26> ipc29<25:24> yes portc input change interrupt _change_notice_c_vector 120 off120<17:1> ifs3<24> iec3<24> ipc30<4:2> ipc30<1:0> yes portd input change interrupt _change_notice_d_vector 121 off121<17:1> ifs3<25> iec3<25> ipc30<12:10> ipc30<9:8> yes porte input change interrupt _change_notice_e_vector 122 off122<17:1> ifs3<26> iec3<26> ipc30<20:18> ipc30<17:16> yes portf input change interrupt _change_notice_f_vector 123 off123<17:1> ifs3<27> iec3<27> ipc30<28:26> ipc30<25:24> yes portg input change interrupt _change_notice_g_vector 124 off124<17:1> ifs3<28> iec3<28> ipc31<4:2> ipc31<1:0> yes porth input change interrupt (2,3) _change_notice_h_vector 125 off125<17:1> ifs3<29> iec3<29> ipc31<12:10> ipc31<9:8> yes portj input change interrupt (2,3) _change_notice_j_vector 126 off126<17:1> ifs3<30> iec3<30> ipc31<20:18> ipc31<17:16> yes portk input change interrupt (2,3,4) _change_notice_k_vector 127 off127<17:1> ifs3<31> iec3<31> ipc31<28:26> ipc31<25:24> yes parallel master port _pmp_vector 128 off128<17:1> ifs4<0> iec4<0> ipc32<4:2> ipc32<1:0> yes parallel master port error _pmp_error_vector 129 off129<17:1> ifs4<1> iec4<1> ipc32<12:10> ipc32<9:8> yes comparator 1 interrupt _comparator_1_vector 130 off130<17:1> ifs4<2> iec4<2> ipc32<20:18> ipc32<17:16> no comparator 2 interrupt _comparator_2_vector 131 off131<17:1> ifs4<3> iec4<3> ipc32<28:26> ipc32<25:24> no usb general event _usb1_vector 132 off132<17:1> ifs4<4> iec4<4> ipc33<4:2> ipc33<1:0> yes usb dma event _usb1_dma_vector 133 off133<17:1> ifs4<5> iec4<5> ipc33<12:10> ipc33<9:8> yes table 7-2: interrupt irq, vector, and bit location (continued) interrupt source (1) xc32 vector name irq # vector # interrupt bit location persistent interrupt flag enable priority sub-priority note 1: not all interrupt sources are available on all devices. see table 1: pic32mz ef family features for the list of available peripherals. 2: this interrupt source is not available on 64-pin devices. 3: this interrupt source is not available on 100-pin devices. 4: this interrupt source is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 123 pic32mz embedded connectivity with floating point unit (ef) family dma channel 0 _dma0_vector 134 off134<17:1> ifs4<6> iec4<6> ipc33<20:18> ipc33<17:16> no dma channel 1 _dma1_vector 135 off135<17:1> ifs4<7> iec4<7> ipc33<28:26> ipc33<25:24> no dma channel 2 _dma2_vector 136 off136<17:1> ifs4<8> iec4<8> ipc34<4:2> ipc34<1:0> no dma channel 3 _dma3_vector 137 off137<17:1> ifs4<9> iec4<9> ipc34<12:10> ipc34<9:8> no dma channel 4 _dma4_vector 138 off138<17:1> ifs4<10> iec4<10> ipc34<20:18> ipc34<17:16> no dma channel 5 _dma5_vector 139 off139<17:1> ifs4<11> iec4<11> ipc34<28:26> ipc34<25:24> no dma channel 6 _dma6_vector 140 off140<17:1> ifs4<12> iec4<12> ipc35<4:2> ipc35<1:0> no dma channel 7 _dma7_vector 141 off141<17:1> ifs4<13> iec4<13> ipc35<12:10> ipc35<9:8> no spi2 fault _spi2_fault_vector 142 off142<17:1> ifs4<14> iec4<14> ipc35<20:18> ipc35<17:16> yes spi2 receive done _spi2_rx_vector 143 off143<17:1> ifs4<15> iec4<15> ipc35<28:26> ipc35<25:24> yes spi2 transfer done _spi2_tx_vector 144 off144<17:1> ifs4<16> iec4<16> ipc36<4:2> ipc36<1:0> yes uart2 fault _uart2_fault_vector 145 off145<17:1> ifs4<17> iec4<17> ipc36<12:10> ipc36<9:8> yes uart2 receive done _uart2_rx_vector 146 off146<17:1> ifs4<18> iec4<18> ipc36<20:18> ipc36<17:16> yes uart2 transfer done _uart2_tx_vector 147 off147<17:1> ifs4<19> iec4<19> ipc36<28:26> ipc36<25:24> yes i2c2 bus collision event (2) _i2c2_bus_vector 148 off148<17:1> ifs4<20> iec4<20> ipc37<4:2> ipc37<1:0> yes i2c2 slave event (2) _i2c2_slave_vector 149 off149<17:1> ifs4<21> iec4<21> ipc37<12:10> ipc37<9:8> yes i2c2 master event (2) _i2c2_master_vector 150 off150<17:1> ifs4<22> iec4<22> ipc37<20:18> ipc37<17:16> yes control area network 1 _can1_vector 151 off151<17:1> ifs4<23> iec4<23> ipc37<28:26> ipc37<25:24> yes control area network 2 _can2_vector 152 off152<17:1> ifs4<24> iec4<24> ipc38<4:2> ipc38<1:0> yes ethernet interrupt _ethernet_vector 153 off153<17:1> ifs4<25> iec4<25> ipc38<12:10> ipc38<9:8> yes spi3 fault _spi3_fault_vector 154 off154<17:1> ifs4<26> iec4<26> ipc38<20:18> ipc38<17:16> yes spi3 receive done _spi3_rx_vector 155 off155<17:1> ifs4<27> iec4<27> ipc38<28:26> ipc38<25:24> yes spi3 transfer done _spi3_tx_vector 156 off156<17:1> ifs4<28> iec4<28> ipc39<4:2> ipc39<1:0> yes uart3 fault _uart3_fault_vector 157 off157<17:1> ifs4<29> iec4<29> ipc39<12:10> ipc39<9:8> yes uart3 receive done _uart3_rx_vector 158 off158<17:1> ifs4<30> iec4<30> ipc39<20:18> ipc39<17:16> yes uart3 transfer done _uart3_tx_vector 159 off159<17:1> ifs4<31> iec4<31> ipc39<28:26> ipc39<25:24> yes i2c3 bus collision event _i2c3_bus_vector 160 off160<17:1> ifs5<0> iec5<0> ipc40<4:2> ipc40<1:0> yes i2c3 slave event _i2c3_slave_vector 161 off161<17:1> ifs5<1> iec5<1> ipc40<12:10> ipc40<9:8> yes table 7-2: interrupt irq, vector, and bit location (continued) interrupt source (1) xc32 vector name irq # vector # interrupt bit location persistent interrupt flag enable priority sub-priority note 1: not all interrupt sources are available on all devices. see table 1: pic32mz ef family features for the list of available peripherals. 2: this interrupt source is not available on 64-pin devices. 3: this interrupt source is not available on 100-pin devices. 4: this interrupt source is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 124 ? 2015-2016 microchip technology inc. i2c3 master event _i2c3_master_vector 162 off162<17:1> ifs5<2> iec5<2> ipc40<20:18> ipc40<17:16> yes spi4 fault _spi4_fault_vector 163 off163<17:1> ifs5<3> iec5<3> ipc40<28:26> ipc40<25:24> yes spi4 receive done _spi4_rx_vector 164 off164<17:1> ifs5<4> iec5<4> ipc41<4:2> ipc41<1:0> yes spi4 transfer done _spi4_tx_vector 165 off165<17:1> ifs5<5> iec5<5> ipc41<12:10> ipc41<9:8> yes real time clock _rtcc_vector 166 off166<17:1> ifs5<6> iec5<6> ipc41<20:18> ipc41<17:16> no flash control event _flash_control_vector 167 off167<17:1> ifs5<7> iec5<7> ipc41<28:26> ipc41<25:24> no prefetch module sec event _prefetch_vector 168 off168<17:1> ifs5<8> iec5<8> ipc42<4:2> ipc42<1:0> yes sqi1 event _sqi1_vector 169 off169<17:1> ifs5<9> iec5<9> ipc42<12:10> ipc42<9:8> yes uart4 fault _uart4_fault_vector 170 off170<17:1> ifs5<10> iec5<10> ipc42<20:18> ipc42<17:16> yes uart4 receive done _uart4_rx_vector 171 off171<17:1> ifs5<11> iec5<11> ipc42<28:26> ipc42<25:24> yes uart4 transfer done _uart4_tx_vector 172 off172<17:1> ifs5<12> iec5<12> ipc43<4:2> ipc43<1:0> yes i2c4 bus collision event _i2c4_bus_vector 173 off173<17:1> ifs5<13> iec5<13> ipc43<12:10> ipc43<9:8> yes i2c4 slave event _i2c4_slave_vector 174 off174<17:1> ifs5<14> iec5<14> ipc43<20:18> ipc43<17:16> yes i2c4 master event _i2c4_master_vector 175 off175<17:1> ifs5<15> iec5<15> ipc43<28:26> ipc43<25:24> yes spi5 fault (2) _spi5_fault_vector 176 off176<17:1> ifs5<16> iec5<16> ipc44<4:2> ipc44<1:0> yes spi5 receive done (2) _spi5_rx_vector 177 off177<17:1> ifs5<17> iec5<17> ipc44<12:10> ipc44<9:8> yes spi5 transfer done (2) _spi5_tx_vector 178 off178<17:1> ifs5<18> iec5<18> ipc44<20:18> ipc44<17:16> yes uart5 fault _uart5_fault_vector 179 off179<17:1> ifs5<19> iec5<19> ipc44<28:26> ipc44<25:24> yes uart5 receive done _uart5_rx_vector 180 off180<17:1> ifs5<20> iec5<20> ipc45<4:2> ipc45<1:0> yes uart5 transfer done _uart5_tx_vector 181 off181<17:1> ifs5<21> iec5<21> ipc45<12:10> ipc45<9:8> yes i2c5 bus collision event _i2c5_bus_vector 182 off182<17:1> ifs5<22> iec5<22> ipc45<20:18> ipc45<17:16> yes i2c5 slave event _i2c5_slave_vector 183 off183<17:1> ifs5<23> iec5<23> ipc45<28:26> ipc45<25:24> yes i2c5 master event _i2c5_master_vector 184 off184<17:1> ifs5<24> iec5<24> ipc46<4:2> ipc46<1:0> yes spi6 fault (2) _spi6_fault_vector 185 off185<17:1> ifs5<25> iec5<25> ipc46<12:10> ipc46<9:8> yes spi6 receive done (2) _spi6_rx_vector 186 off186<17:1> ifs5<26> iec5<26> ipc46<20:18> ipc46<17:16> yes spi6 transfer done (2) _spi6_tx_vector 187 off187<17:1> ifs5<27> iec5<27> ipc46<28:26> ipc46<25:24> yes uart6 fault _uart6_fault_vector 188 off188<17:1> ifs5<28> iec5<28> ipc47<4:2> ipc47<1:0> yes uart6 receive done _uart6_rx_vector 189 off189<17:1> ifs5<29> iec5<29> ipc47<12:10> ipc47<9:8> yes table 7-2: interrupt irq, vector, and bit location (continued) interrupt source (1) xc32 vector name irq # vector # interrupt bit location persistent interrupt flag enable priority sub-priority note 1: not all interrupt sources are available on all devices. see table 1: pic32mz ef family features for the list of available peripherals. 2: this interrupt source is not available on 64-pin devices. 3: this interrupt source is not available on 100-pin devices. 4: this interrupt source is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 125 pic32mz embedded connectivity with floating point unit (ef) family uart6 transfer done _uart6_tx_vector 190 off190<17:1> ifs5<30> iec5<30> ipc47<20:18> ipc47<17:16> yes reserved 191 adc end of scan ready _adc_eos_vector 192 off192<17:1> ifs6<0> iec6<0> ipc48<4:2> ipc48<1:0> yes adc analog circuits ready _adc_ardy_vector 193 off193<17:1> ifs6<1> iec6<1> ipc48<12:10> ipc48<9:8> yes adc update ready _adc_urdy_vector 194 off194<17:1> ifs6<2> iec6<2> ipc48<20:18> ipc48<17:16> yes reserved 195 adc group early interrupt request _adc_early_vector 196 off196<17:1> ifs6<4> iec6<4> ipc49<4:2> ipc49<1:0> yes reserved 197 adc0 early interrupt _adc0_early_vector 198 off198<17:1> ifs6<6> iec6<6> ipc49<20:18> ipc49<17:16> yes adc1 early interrupt _adc1_early_vector 199 off199<17:1> ifs6<7> iec6<7> ipc49<28:26> ipc49<25:24> yes adc2 early interrupt _adc2_early_vector 200 off200<17:1> ifs6<8> iec6<8> ipc50<4:2> ipc50<1:0> yes adc3 early interrupt _adc2_early_vector 201 off201<17:1> ifs6<9> iec6<9> ipc50<12:10> ipc50<9:8> yes adc4 early interrupt _adc4_early_vector 202 off202<17:1> ifs6<10> iec6<10> ipc50<20:18> ipc50<17:16> yes reserved 203 reserved 204 adc7 early interrupt _adc7_early_vector 205 off205<17:1> ifs6<13> iec6<13> ipc51<12:10> ipc51<9:8> yes adc0 warm interrupt _adc0_warm_vector 206 off206<17:1> ifs6<14> iec6<14> ipc51<20:18> ipc51<17:16> yes adc1 warm interrupt _adc1_warm_vector 207 off207<17:1> ifs6<15> iec6<15> ipc51<28:26> ipc51<25:24> yes adc2 warm interrupt _adc2_warm_vector 208 off208<17:1> ifs6<16> iec6<16> ipc52<4:2> ipc52<1:0> yes adc3 warm interrupt _adc3_warm_vector 209 off209<17:1> ifs6<17> iec6<17> ipc52<12:10> ipc52<9:8> yes adc4 warm interrupt _adc4_warm_vector 210 off210<17:1> ifs6<18> iec6<18> ipc52<20:18> ipc52<17:16> yes reserved 211 reserved 212 adc7 warm interrupt _adc7_warm_vector 213 off213<17:1> ifs6<21> iec6<21> ipc53<12:10> ipc53<9:8> yes lowest natural order priority table 7-2: interrupt irq, vector, and bit location (continued) interrupt source (1) xc32 vector name irq # vector # interrupt bit location persistent interrupt flag enable priority sub-priority note 1: not all interrupt sources are available on all devices. see table 1: pic32mz ef family features for the list of available peripherals. 2: this interrupt source is not available on 64-pin devices. 3: this interrupt source is not available on 100-pin devices. 4: this interrupt source is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 126 ? 2015-2016 microchip technology inc. 7.3 interrupt control registers table 7-3: interrupt register map virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0000 intcon 31:16 nmikey<7:0> 0000 15:0 mvec tpc<2:0> int4ep int3ep int2ep int1ep int0ep 0000 0010 priss 31:16 pri7ss<3:0> pri6ss<3:0> pri5ss<3:0> pri4ss<3:0> 0000 15:0 pri3ss<3:0> pri2ss<3:0> pri1ss<3:0> ss0 0000 0020 intstat 31:16 0000 15:0 sripl<2:0> sirq<7:0> 0000 0030 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 0040 ifs0 31:16 oc6if ic6if ic6eif t6if oc5if ic5if ic5eif t5if int4if oc4if ic4if ic4eif t4if int3if oc3if ic3if 0000 15:0 ic3eif t3if int2if oc2if ic2if ic2eif t2if int1if oc1if ic1if ic1eif t1if int0if cs1if cs0if ctif 0000 0050 ifs1 31:16 adcd4if adcd3if adcd2if adcd1if adcd0if adcfltif adcdf6if adcdf5if adcdf4if adcdf3if adcdf2if adcdf1if adcdc6if adcdc5if adcdc4if adcdc3if 0000 15:0 adcdc2if adcdc1if adcfifoif adcif oc9if ic9if ic9eif t9if oc8if ic8if ic8eif t8if oc7if ic7if ic7eif t7if 0000 0060 ifs2 (5) 31:16 adcd36if adcd35if adcd34if adcd33if adcd32if adcd31if adcd30if adcd29if adcd28if adcd27if adcd26if adcd25if adcd24if adcd23if adcd22if adcd21if 0000 15:0 adcd20if adcd19if adcd18if adcd17if adcd16if adcd15if adcd14if adcd13if adcd12if adcd11if adcd10if adcd9if adcd8if adcd7if adcd6if adcd5if 0000 0070 ifs3 (6) 31:16 cnkif (8) cnjif cnhif cngif cnfif cneif cndif cncif cnbif cnaif i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif 0000 15:0 spi1txif spi1rxif spi1eif crptif (7) sbif cfdcif cpcif adcd44if adcd43if adcd42if adcd41if adcd40if adcd39if adcd38if adcd37if 0000 0080 ifs4 31:16 u3txif u3rxif u3eif spi3txif spi3rxif spi3eif ethif can2if (3) can1if (3) i2c2mif (2) i2c2sif (2) i2c2bif (2) u2txif u2rxif u2eif spi2txif 0000 15:0 spi2rxif spi2eif dma7if dma6if dma5if dma4if dma3if dma2if dma1if dma0if usbdmaif usbif cmp2if cmp1if pmpeif pmpif 0000 0090 ifs5 31:16 u6txif u6rxif u6eif spi6tx (2) spi6rxif (2) spi6if (2) i2c5mif i2c5sif i2c5bif u5txif u5rxif u5eif spi5txif (2) spi5rxif (2) spi5eif (2) 0000 15:0 i2c4mif i2c4sif i2c4bif u4txif u4rxif u4eif sqi1if preif fceif rtccif spi4txif spi4rxif spi4eif i2c3mif i2c3sif i2c3bif 0000 00a0 ifs6 31:16 adc7wif adc4wif adc3wif adc2wif 0000 15:0 adc1wif adc0wif adc7eif adc4eif adc3eif adc2eif adc1eif adc0eif adcgrpif adcurdyif adcardyif adceosif 0000 00c0 iec0 31:16 oc6ie ic6ie ic6eie t6ie oc5ie ic5ie ic5eie t5ie int4ie oc4ie ic4ie ic4eie t4ie int3ie oc3ie ic3ie 0000 15:0 ic3eie t3ie int2ie oc2ie ic2ie ic2eie t2ie int1ie oc1ie ic1ie ic1eie t1ie int0ie cs1ie cs0ie ctie 0000 00d0 iec1 31:16 adcd4ie adcd3ie adcd2ie adcd1ie adcd0ie adcfltie adcdf6ie adcdf5ie adcdf4ie adcdf3ie adcdf2ie adcdf1ie adcdc6ie adcdc5ie adcdc4ie adcdc3ie 0000 15:0 adcdc2ie adcdc1ie adcfifoie adcie oc9ie ic9ie ic9eie t9ie oc8ie ic8ie ic8eie t8ie oc7ie ic7ie ic7eie t7ie 0000 00e0 iec2 (5) 31:16 adcd36ie adcd35ie adcd34ie adcd33ie adcd32ie adcd31ie adcd30ie adcd29ie adcd28ie adcd27ie adcd26ie adcd25ie adcd24ie adcd23ie adcd22ie adcd21ie 0000 15:0 adcd20ie adcd19ie adcd18ie adcd17ie adcd16ie adcd15ie adcd14ie adcd13ie adcd12ie adcd11ie adcd10ie adcd9ie adcd8ie adcd7ie adcd6ie adcd5ie 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 127 pic32mz embedded connectivity with floating point unit (ef) family 00f0 iec3 (6) 31:16 cnkie cnjie cnhie cngie cnfie cneie cndie cncie cnbie cnaie i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie 0000 15:0 spi1txie spi1rxie spi1eie crptie (7) sbie cfdcie cpcie adcd44ie adcd43ie adcd42ie adcd41ie adcd40ie adcd39ie adcd38ie adcd37ie 0000 0100 iec4 31:16 u3txie u3rxie u3eie spi3txie spi3rxie spi3eie ethie can2ie (3) can1ie (3) i2c2mie (2) i2c2sie (2) i2c2bie (2) u2txie u2rxie u2eie spi2txie 0000 15:0 spi2rxie spi2eie dma7ie dma6ie dma5ie dma4ie dma3ie dma2ie dma1ie dma0ie usbdmaie usbie cmp2ie cmp1ie pmpeie pmpie 0000 0110 iec5 31:16 u6txie u6rxie u6eie spi6txie (2) spi6rxie (2) spi6ie (2) i2c5mie i2c5sie i2c5bie u5txie u5rxie u5eie spi5txie (2) spi5rxie (2) spi5eie (2) 0000 15:0 i2c4mie i2c4sie i2c4bie u4txie u4rxie u4eie sqi1ie preie fceie rtccie spi4txie spi4rxie spi4eie i2c3mie i2c3sie i2c3bie 0000 0120 iec6 31:16 adc7wie adc4wie adc3wie adc2wie 0000 15:0 adc1wie adc0wie adc7eie adc4eie adc3eif adc2eie adc1eie adc0eie adcgrpie adcurdyie adcardyie adceosie 0000 0140 ipc0 31:16 int0ip<2:0> int0is<1:0> cs1ip<2:0> cs1is<1:0> 0000 15:0 cs0ip<2:0> cs0is<1:0> ctip<2:0> ctis<1:0> 0000 0150 ipc1 31:16 oc1ip<2:0> oc1is<1:0> ic1ip<2:0> ic1is<1:0> 0000 15:0 ic1eip<2:0> ic1eis<1:0> t1ip<2:0> t1is<1:0> 0000 0160 ipc2 31:16 ic2ip<2:0> ic2is<1:0> ic2eip<2:0> ic2eis<1:0> 0000 15:0 t2ip<2:0> t2is<1:0> int1ip<2:0> int1is<1:0> 0000 0170 ipc3 31:16 ic3eip<2:0> ic3eis<1:0> t3ip<2:0> t3is<1:0> 0000 15:0 int2ip<2:0> int2is<1:0> oc2ip<2:0> oc2is<1:0> 0000 0180 ipc4 31:16 t4ip<2:0> t4is<1:0> int3ip<2:0> int3is<1:0> 0000 15:0 oc3ip<2:0> oc3is<1:0> ic3ip<2:0> ic3is<1:0> 0000 0190 ipc5 31:16 int4ip<2:0> int4is<1:0> oc4ip<2:0> oc4is<1:0> 0000 15:0 ic4ip<2:0> ic4is<1:0> ic4eip<2:0> ic4eis<1:0> 0000 01a0 ipc6 31:16 oc5ip<2:0> oc5is<1:0> ic5ip<2:0> ic5is<1:0> 0000 15:0 ic5eip<2:0> ic5eis<1:0> t5ip<2:0> t5is<1:0> 0000 01b0 ipc7 31:16 oc6ip<2:0> oc6is<1:0> ic6ip<2:0> ic6is<1:0> 0000 15:0 ic6eip<2:0> ic6eis<1:0> t6ip<2:0> t6is<1:0> 0000 01c0 ipc8 31:16 oc7ip<2:0> oc7is<1:0> ic7ip<2:0> ic7is<1:0> 0000 15:0 ic7eip<2:0> ic7eis<1:0> t7ip<2:0> t7is<1:0> 0000 01d0 ipc9 31:16 oc8ip<2:0> oc8is<1:0> ic8ip<2:0> ic8is<1:0> 0000 15:0 ic8eip<2:0> ic8eis<1:0> t8ip<2:0> t8is<1:0> 0000 01e0 ipc10 31:16 oc9ip<2:0> oc9is<1:0> ic9ip<2:0> ic9is<1:0> 0000 15:0 ic9eip<2:0> ic9eis<1:0> t9ip<2:0> t9is<1:0> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 128 ? 2015-2016 microchip technology inc. 01f0 ipc11 31:16 adcdc2ip<2:0> adcdc2is<1:0> adcdc1ip<2:0> adcdc1is<1:0> 0000 15:0 adcfifoip<2:0> adcfifois<1:0> adcip<2:0> adcis<1:0> 0000 0200 ipc12 31:16 adcdc6ip<2:0> adcdc6is<1:0> adcdc5ip<2:0> adcdc5is<1:0> 0000 15:0 adcdc4ip<2:0> adcdc4is<1:0> adcdc3ip<2:0> adcdc3is<1:0> 0000 0210 ipc13 31:16 adcdf4ip<2:0> adcdf4is<1:0> adcdf3ip<2:0> adcdf3is<1:0> 0000 15:0 adcdf2ip<2:0> adcdf2is<1:0> adcdf1ip<2:0> adcdf1is<1:0> 0000 0220 ipc14 31:16 adcd0ip<2:0> adcd0is<1:0> adcdfltip<2:0> adcdfltis<1:0> 0000 15:0 adcdf6ip<2:0> adcdf6is<1:0> adcdf5ip<2:0> adcdf5is<1:0> 0000 0230 ipc15 31:16 adcd4ip<2:0> adcd4is<1:0> adcd3ip<2:0> adcd3is<1:0> 0000 15:0 adcd2ip<2:0> adcd2is<1:0> adcd1ip<2:0> adcd1is<1:0> 0000 0240 ipc16 31:16 adcd8ip<2:0> adcd8is<1:0> adcd7ip<2:0> adcd7is<1:0> 0000 15:0 adcd6ip<2:0> adcd6is<1:0> adcd5ip<2:0> adcd5is<1:0> 0000 0250 ipc17 31:16 adcd12ip<2:0> adcd12is<1:0> adcd11ip<2:0> adcd11is<1:0> 0000 15:0 adcd10ip<2:0> adcd10is<1:0> adcd9ip<2:0> adcd9is<1:0> 0000 0260 ipc18 31:16 adcd16ip<2:0> adcd16is<1:0> adcd15ip<2:0> adcd15is<1:0> 0000 15:0 adcd14ip<2:0> adcd14is<1:0> adcd13ip<2:0> adcd13is<1:0> 0000 0270 ipc19 31:16 adcd20ip<2:0> (2) adcd20is<1:0> (2) adcd19ip<2:0> (2) adcd19is<1:0> (2) 0000 15:0 adcd18ip<2:0> adcd18is<1:0> adcd17ip<2:0> adcd17is<1:0> 0000 0280 ipc20 31:16 adcd24ip<2:0> (2) adcd24is<1:0> (2) adcd23ip<2:0> (2) adcd23is<1:0> (2) 0000 15:0 adcd22ip<2:0> (2) adcd22is<1:0> (2) adcd21ip<2:0> (2) adcd21is<1:0> (2) 0000 0290 ipc21 31:16 adcd28ip<2:0> (2) adcd28is<1:0> (2) adcd27ip<2:0> (2) adcd27is<1:0> (2) 0000 15:0 adcd26ip<2:0> (2) adcd26is<1:0> (2) adcd25ip<2:0> (2) adcd25is<1:0> (2) 0000 02a0 ipc22 31:16 adcd32ip<2:0> (2) adcd32is<1:0> (2) adcd31ip<2:0> (2) adcd31is<1:0> (2) 0000 15:0 adcd30ip<2:0> (2) adcd30is<1:0> (2) adcd29ip<2:0> (2) adcd29is<1:0> (2) 0000 02b0 ipc23 31:16 adcd36ip<2:0> (2,4) adcd36is<1:0> (2,4) adcd35ip<2:0> (2,4) adcd35is<1:0> (2,4) 0000 15:0 adcd34ip<2:0> (2) adcd34is<1:0> (2) adcd33ip<2:0> (2) adcd33is<1:0> (2) 0000 02c0 ipc24 31:16 adcd40ip<2:0> (2,4) adcd40is<1:0> (2,4) adcd39ip<2:0> (2,4) adcd39is<1:0> (2,4) 0000 15:0 adcd38ip<2:0> (2,4) adcd38is<1:0> (2,4) adcd37ip<2:0> (2,4) adcd37is<1:0> (2,4) 0000 02d0 ipc25 31:16 adcd44ip<2:0> adcd44is<1:0> adcd43ip<2:0> adcd43is<1:0> 0000 15:0 adcd42ip<2:0> (2,4) adcd42is<1:0> (2,4) adcd41ip<2:0> (2,4) adcd41is<1:0> (2,4) 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 129 pic32mz embedded connectivity with floating point unit (ef) family 02e0 ipc26 31:16 crptip<2:0> (7) crptis<1:0> (7) sbip<2:0> sbis<1:0> 0000 15:0 cfdcip<2:0> cfdcis<1:0> cpcip<2:0> cpcis<1:0> 0000 02f0 ipc27 31:16 spi1txip<2:0> spi1txis<1:0> spi1rxip<2:0> spi1rxis<1:0> 0000 15:0 spi1eip<2:0> spi1eis<1:0> 0000 0300 ipc28 31:16 i2c1bip<2:0> i2c1bis<1:0> u1txip<2:0> u1txis<1:0> 0000 15:0 u1rxip<2:0> u1rxis<1:0> u1eip<2:0> u1eis<1:0> 0000 0310 ipc29 31:16 cnbip<2:0> cnbis<1:0> cnaip<2:0> (2) cnais<1:0> (2) 0000 15:0 i2c1mip<2:0> i2c1mis<1:0> i2c1sip<2:0> i2c1sis<1:0> 0000 0320 ipc30 31:16 cnfip<2:0> cnfis<1:0> cneip<2:0> cneis<1:0> 0000 15:0 cndip<2:0> cndis<1:0> cncip<2:0> cncis<1:0> 0000 0330 ipc31 31:16 cnkip<2:0> (2,4,8) cnkis<1:0> (2,4,8) cnjip<2:0> (2,4) cnjis<1:0> (2,4) 0000 15:0 cnhip<2:0> (2,4) cnhis<1:0> (2,4) cngip<2:0> cngis<1:0> 0000 0340 ipc32 31:16 cmp2ip<2:0> cmp2is<1:0> cmp1ip<2:0> cmp1is<1:0> 0000 15:0 pmpeip<2:0> pmpeis<1:0> pmpip<2:0> pmpis<1:0> 0000 0350 ipc33 31:16 dma1ip<2:0> dma1is<1:0> dma0ip<2:0> dma0is<1:0> 0000 15:0 usbdmaip<2:0> usbdmais<1:0> usbip<2:0> usbis<1:0> 0000 0360 ipc34 31:16 dma5ip<2:0> dma5is<1:0> dma4ip<2:0> dma4is<1:0> 0000 15:0 dma3ip<2:0> dma3is<1:0> dma2ip<2:0> dma2is<1:0> 0000 0370 ipc35 31:16 spi2rxip<2:0> spi2rxis<1:0> spi2eip<2:0> spi2eis<1:0> 0000 15:0 dma7ip<2:0> dma7is<1:0> dma6ip<2:0> dma6is<1:0> 0000 0380 ipc36 31:16 u2txip<2:0> u2txis<1:0> u2rxip<2:0> u2rxis<1:0> 0000 15:0 u2eip<2:0> u2eis<1:0> spi2txip<2:0> spi2txis<1:0> 0000 0390 ipc37 31:16 can1ip<2:0> (3) can1is<1:0> (3) i2c2mip<2:0> (2) i2c2mis<1:0> (2) 0000 15:0 i2c2sip<2:0> (2) i2c2sis<1:0> (2) i2c2bip<2:0> (2) i2c2bis<1:0> (2) 0000 03a0 ipc38 31:16 spi3rxip<2:0> spi3rxis<1:0> spi3eip<2:0> spi3eis<1:0> 0000 15:0 ethip<2:0> ethis<1:0> can2ip<2:0> (3) can2is<1:0> (3) 0000 03b0 ipc39 31:16 u3txip<2:0> u3txis<1:0> u3rxip<2:0> u3rxis<1:0> 0000 15:0 u3eip<2:0> u3eis<1:0> spi3txip<2:0> spi3txis<1:0> 0000 03c0 ipc40 31:16 spi4eip<2:0> spi4eis<1:0> i2c3mip<2:0> i2c3mis<1:0> 0000 15:0 i2c3sip<2:0> i2c3sis<1:0> i2c3bip<2:0> i2c3bis<1:0> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 130 ? 2015-2016 microchip technology inc. 03d0 ipc41 31:16 fceip<2:0> fceis<1:0> rtccip<2:0> rtccis<1:0> 0000 15:0 spi4txip<2:0> spi4txis<1:0> spi4rxip<2:0> spi4rxis<1:0> 0000 03e0 ipc42 31:16 u4rxip<2:0> u4rxis<1:0> u4eip<2:0> u4eis<1:0> 0000 15:0 sqi1ip<2:0> sqi1is<1:0> preip<2:0> preis<1:0> 0000 03f0 ipc43 31:16 i2c4mip<2:0> i2c4mis<1:0> i2c4sip<2:0> i2c4sis<1:0> 0000 15:0 i2c4bip<2:0> i2c4bis<1:0> u4txip<2:0> u4txis<1:0> 0000 0400 ipc44 31:16 u5eip<2:0> u5eis<1:0> spi5txip<2:0> (2) spi5txis<1:0> (2) 0000 15:0 spi5rxip<2:0> (2) spi5rxis<1:0> (2) spi5eip<2:0> (2) spi5eis<1:0> (2) 0000 0410 ipc45 31:16 i2c5sip<2:0> i2c5sis<1:0> i2c5bip<2:0> i2c5bis<1:0> 0000 15:0 u5txip<2:0> u5txis<1:0> u5rxip<2:0> u5rxis<1:0> 0000 0420 ipc46 31:16 spi6txip<2:0> (2) spi6txis<1:0> (2) spi6rxip<2:0> (2) spi6rxis<1:0> (2) 0000 15:0 spi6eip<2:0> (2) spi6eis<1:0> (2) i2c5mip<2:0> i2c5mis<1:0> 0000 0430 ipc47 31:16 u6txip<2:0> u6txis<1:0> 0000 15:0 u6rxip<2:0> u6rxis<1:0> u6eip<2:0> u6eis<1:0> 0000 0440 ipc48 31:16 adcurdyip<2:0> adcurdyis<1:0> 0000 15:0 adcardyip<2:0> adcardyis<1:0> adceosip<2:0> adceosis<1:0> 0000 0450 ipc49 31:16 adc1eip<2:0> adc1eis<1:0> adc0eip<2:0> adc0eis<1:0> 0000 15:0 adcgrpip<2:0> adcgrpis<1:0> 0000 0460 ipc50 31:16 adc4eip<2:0> adc4eis<1:0> 0000 15:0 adc3eip<2:0> adc3eis<1:0> adc2eip<2:0> adc2eis<1:0> 0000 0470 ipc51 31:16 adc1wip<2:0> adc1wis<1:0> adc0wip<2:0> adc0wis<1:0> 0000 15:0 adc7eip<2:0> adc7eis<1:0> 0000 0480 ipc52 31:16 adc4wip<2:0> adc4wis<1:0> 0000 15:0 adc3wip<2:0> adc3wis<1:0> adc2wip<2:0> adc2wis<1:0> 0000 0490 ipc53 31:16 0000 15:0 adc7wip<2:0> adc7wis<1:0> 0000 0540 off000 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0544 off001 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 131 pic32mz embedded connectivity with floating point unit (ef) family 0548 off002 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 054c off003 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0550 off004 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0554 off005 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0558 off006 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 055c off007 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0560 off008 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0564 off009 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0568 off010 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 056c off011 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0570 off012 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0574 off013 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0578 off014 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 057c off015 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0580 off016 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 132 ? 2015-2016 microchip technology inc. 0584 off017 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0588 off018 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 058c off019 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0590 off020 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0594 off021 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0598 off022 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 059c off023 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05a0 off024 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05a4 off025 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05a8 off026 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05ac off027 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05b0 off028 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05b4 off029 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05b8 off030 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05bc off031 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 133 pic32mz embedded connectivity with floating point unit (ef) family 05c0 off032 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05c4 off033 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05c8 off034 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05cc off035 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05d0 off036 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05d4 off037 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05d8 off038 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05dc off039 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05e0 off040 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05e4 off041 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05e8 off042 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05ec off043 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05f0 off044 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05f4 off045 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 05f8 off046 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 134 ? 2015-2016 microchip technology inc. 05fc off047 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0600 off048 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0604 off049 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0608 off050 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 060c off051 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0610 off052 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0614 off053 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0618 off054 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 061c off055 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0620 off056 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0624 off057 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0628 off058 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 062c off059 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0630 off060 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0634 off061 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 135 pic32mz embedded connectivity with floating point unit (ef) family 0638 off062 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 063c off063 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0640 off064 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0644 off065 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0648 off066 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 064c off067 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0650 off068 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0654 off069 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0658 off070 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 065c off071 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0660 off072 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0664 off073 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0668 off074 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 066c off075 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0670 off076 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 136 ? 2015-2016 microchip technology inc. 0674 off077 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0678 off078 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 067c off079 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0680 off080 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0684 off081 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0688 off082 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 068c off083 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0690 off084 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0694 off085 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0698 off086 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 069c off087 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06a0 off088 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06a4 off089 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06a8 off090 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06ac off091 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 137 pic32mz embedded connectivity with floating point unit (ef) family 06b0 off092 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06b4 off093 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06b8 off094 (2,4) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06bc off095 (2,4) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06c0 off096 (2,4) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06c4 off097 (2,4) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06c8 off098 (2,4) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06cc off099 (2,4) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06d0 off100 (2,4) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06d4 off101 (2,4) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06d8 off102 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06dc off103 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06e0 off104 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06e4 off105 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06e8 off106 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 138 ? 2015-2016 microchip technology inc. 06ec off107 (7) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06f4 off109 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06f8 off110 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 06fc off111 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0700 off112 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0704 off113 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0708 off114 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 070c off115 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0710 off116 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0714 off117 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0718 off118 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 071c off119 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0720 off120 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0724 off121 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0728 off122 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 139 pic32mz embedded connectivity with floating point unit (ef) family 072c off123 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0730 off124 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0734 off125 (2,4) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0738 off126 (2,4) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 073c off127 (2,4,8) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0740 off128 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0744 off129 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0748 off130 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 074c off131 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0750 off132 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0754 off133 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0758 off134 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 075c off135 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0760 off136 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0764 off137 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 140 ? 2015-2016 microchip technology inc. 0768 off138 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 076c off139 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0770 off140 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0774 off141 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0778 off142 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 077c off143 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0780 off144 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0784 off145 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0788 off146 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 078c off147 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0790 off148 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0794 off149 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0798 off150 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 079c off151 (3) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07a0 off152 (3) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 141 pic32mz embedded connectivity with floating point unit (ef) family 07a4 off153 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07a8 off154 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07ac off155 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07b0 off156 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07b4 off157 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07b8 off158 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07bc off159 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07c0 off160 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07c4 off161 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07c8 off162 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07cc off163 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07d0 off164 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07d4 off165 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07d8 off166 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07dc off167 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 142 ? 2015-2016 microchip technology inc. 07e0 off168 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07e4 off169 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07e8 off170 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07ec off171 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07f0 off172 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07f4 off173 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07f8 off174 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 07fc off175 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0800 off176 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0804 off177 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0808 off178 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 080c off179 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0810 off180 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0814 off181 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0818 off182 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 143 pic32mz embedded connectivity with floating point unit (ef) family 081c off183 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0820 off184 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0824 off185 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0828 off186 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 082c off187 (2) 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0830 off188 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0834 off189 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0838 off190 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0840 off192 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0844 off193 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0848 off194 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0850 off196 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0858 off198 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 085c off199 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0860 off200 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 144 ? 2015-2016 microchip technology inc. 0864 off201 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0868 off202 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0874 off205 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0878 off206 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 087c off207 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0880 off208 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0884 off209 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0888 off210 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 0894 off213 31:16 voff<17:16> 0000 15:0 voff<15:1> 0000 table 7-3: interrupt register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table with the exception of the offx registers, have corresponding clr, set, and inv registers at their v irtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this bit or register is not available on 64-pin devices. 3: this bit or register is not available on devices without a can module. 4: this bit or register is not available on 100-pin devices. 5: bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. 6: bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devi c es; bit 22 is not available on 64-pin devices. 7: this bit or register is not available on devices without a crypto module. 8: this bit or register is not available on 124-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 145 pic32mz embedded connectivity with floating point unit (ef) family register 7-1: intcon: interrupt control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nmikey<7:0> 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 mvec t p c < 2 : 0 > 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int4ep int3ep int2ep int1ep int0ep legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 nmikey<7:0>: non-maskable interrupt key bits when the correct key (0x4e) is written, a software nmi will be generated. the status is indicated by the gnmi bit (rnmicon<19>). bit 23-13 unimplemented: read as 0 bit 12 mvec: multi vector configuration bit 1 = interrupt controller configured for multi vectored mode 0 = interrupt controller configured for single vectored mode bit 11 unimplemented: read as 0 bit 10-8 tpc<2:0>: interrupt proximity timer control bits 111 = interrupts of group priority 7 or lower start the interrupt proximity timer 110 = interrupts of group priority 6 or lower start the interrupt proximity timer 101 = interrupts of group priority 5 or lower start the interrupt proximity timer 100 = interrupts of group priority 4 or lower start the interrupt proximity timer 011 = interrupts of group priority 3 or lower start the interrupt proximity timer 010 = interrupts of group priority 2 or lower start the interrupt proximity timer 001 = interrupts of group priority 1 start the interrupt proximity timer 000 = disables interrupt proximity timer bit 7-5 unimplemented: read as 0 bit 4 int4ep: external interrupt 4 edge polarity control bit 1 = rising edge 0 = falling edge bit 3 int3ep: external interrupt 3 edge polarity control bit 1 = rising edge 0 = falling edge bit 2 int2ep: external interrupt 2 edge polarity control bit 1 = rising edge 0 = falling edge bit 1 int1ep: external interrupt 1 edge polarity control bit 1 = rising edge 0 = falling edge bit 0 int0ep: external interrupt 0 edge polarity control bit 1 = rising edge 0 = falling edge
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 146 ? 2015-2016 microchip technology inc. register 7-2: priss: priori ty shadow select register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pri7ss<3:0> (1) pri6ss<3:0> (1) 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pri5ss<3:0> (1) pri4ss<3:0> (1) 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pri3ss<3:0> pri2ss<3:0> (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 pri1ss<3:0> (1) ss0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-28 pri7ss<3:0>: interrupt with priority level 7 shadow set bits (1) 1xxx = reserved (by default, an interrupt with a priority level of 7 uses shadow set 0) 0111 = interrupt with a priority level of 7 uses shadow set 7 0110 = interrupt with a priority level of 7 uses shadow set 6 0001 = interrupt with a priority level of 7 uses shadow set 1 0000 = interrupt with a priority level of 7 uses shadow set 0 bit 27-24 pri6ss<3:0>: interrupt with priority level 6 shadow set bits (1) 1xxx = reserved (by default, an interrupt with a priority level of 6 uses shadow set 0) 0111 = interrupt with a priority level of 6 uses shadow set 7 0110 = interrupt with a priority level of 6 uses shadow set 6 0001 = interrupt with a priority level of 6 uses shadow set 1 0000 = interrupt with a priority level of 6 uses shadow set 0 bit 23-20 pri5ss<3:0>: interrupt with priority level 5 shadow set bits (1) 1xxx = reserved (by default, an interrupt with a priority level of 5 uses shadow set 0) 0111 = interrupt with a priority level of 5 uses shadow set 7 0110 = interrupt with a priority level of 5 uses shadow set 6 0001 = interrupt with a priority level of 5 uses shadow set 1 0000 = interrupt with a priority level of 5 uses shadow set 0 bit 19-16 pri4ss<3:0>: interrupt with priority level 4 shadow set bits (1) 1xxx = reserved (by default, an interrupt with a priority level of 4 uses shadow set 0) 0111 = interrupt with a priority level of 4 uses shadow set 7 0110 = interrupt with a priority level of 4 uses shadow set 6 0001 = interrupt with a priority level of 4 uses shadow set 1 0000 = interrupt with a priority level of 4 uses shadow set 0 note 1: these bits are ignored if the mvec bit (intcon<12>) = 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 147 pic32mz embedded connectivity with floating point unit (ef) family bit 15-12 pri3ss<3:0>: interrupt with priority level 3 shadow set bits (1) 1xxx = reserved (by default, an interrupt with a priority level of 3 uses shadow set 0) 0111 = interrupt with a priority level of 3 uses shadow set 7 0110 = interrupt with a priority level of 3 uses shadow set 6 0001 = interrupt with a priority level of 3 uses shadow set 1 0000 = interrupt with a priority level of 3 uses shadow set 0 bit 11-8 pri2ss<3:0>: interrupt with priority level 2 shadow set bits (1) 1xxx = reserved (by default, an interrupt with a priority level of 2 uses shadow set 0) 0111 = interrupt with a priority level of 2 uses shadow set 7 0110 = interrupt with a priority level of 2 uses shadow set 6 0001 = interrupt with a priority level of 2 uses shadow set 1 0000 = interrupt with a priority level of 2 uses shadow set 0 bit 7-4 pri1ss<3:0>: interrupt with priority level 1 shadow set bits (1) 1xxx = reserved (by default, an interrupt with a priority level of 1 uses shadow set 0) 0111 = interrupt with a priority level of 1 uses shadow set 7 0110 = interrupt with a priority level of 1 uses shadow set 6 0001 = interrupt with a priority level of 1 uses shadow set 1 0000 = interrupt with a priority level of 1 uses shadow set 0 bit 3-1 unimplemented: read as 0 bit 0 ss0: single vector shadow register set bit 1 = single vector is presented with a shadow set 0 = single vector is not presented with a shadow set register 7-2: priss: priority shadow select register (continued) note 1: these bits are ignored if the mvec bit (intcon<12>) = 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 148 ? 2015-2016 microchip technology inc. register 7-3: intstat: interrupt status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 s r i p l < 2 : 0 > (1) 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 sirq<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-11 unimplemented: read as 0 bit 10-8 sripl<2:0>: requested priority level bits for single vector mode bits (1) 111-000 = the priority level of the latest interrupt presented to the cpu bit 7-6 unimplemented: read as 0 bit 7-0 sirq<7:0>: last interrupt request serviced status bits 11111111-00000000 = the last interrupt request number serviced by the cpu note 1: this value should only be used when the interrupt controller is configured for single vector mode. register 7-4: iptmr: interrupt proximity timer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iptmr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iptmr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iptmr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iptmr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 iptmr<31:0>: interrupt proximity timer reload bits used by the interrupt proximity timer as a reload value when the interrupt proximity timer is triggered by an interrupt event.
? 2015-2016 microchip technology inc. ds60001320d-page 149 pic32mz embedded connectivity with floating point unit (ef) family register 7-5: ifsx: interr upt flag status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs31 ifs30 ifs29 ifs28 ifs27 ifs26 ifs25 ifs24 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs23 ifs22 ifs21 ifs20 ifs19 ifs18 ifs17 ifs16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs15 ifs14 ifs13 ifs12 ifs11 ifs10 ifs9 ifs8 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs7 ifs6 ifs5 ifs4 ifs3 ifs2 ifs1 ifs0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 ifs31-ifs0: interrupt flag status bits 1 = interrupt request has occurred 0 = no interrupt request has occurred note: this register represents a generic definition of the ifsx register. refer to table 7-2 for the exact bit definitions. register 7-6: iecx: interrupt enable control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec31 iec30 iec29 iec28 iec27 iec26 iec25 iec24 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec23 iec22 iec21 iec20 iec19 iec18 iec17 iec16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec15 iec14 iec13 iec12 iec11 iec10 iec9 iec8 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec7 iec6 iec5 iec4 iec3 iec2 iec1 iec0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 iec31-iec0: interrupt enable bits 1 = interrupt is enabled 0 = interrupt is disabled note: this register represents a generic definition of the iecx register. refer to table 7-2 for the exact bit definitions.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 150 ? 2015-2016 microchip technology inc. register 7-7: ipcx: interrupt priority control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ip3<2:0> is3<1:0> 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ip2<2:0> is2<1:0> 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ip1<2:0> is1<1:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ip0<2:0> is0<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28-26 ip3<2:0>: interrupt priority bits 111 = interrupt priority is 7 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 is3<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 23-21 unimplemented: read as 0 bit 20-18 ip2<2:0>: interrupt priority bits 111 = interrupt priority is 7 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 is2<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 15-13 unimplemented: read as 0 note: this register represents a generic definition of the ipcx register. refer to table 7-2 for the exact bit definitions.
? 2015-2016 microchip technology inc. ds60001320d-page 151 pic32mz embedded connectivity with floating point unit (ef) family bit 12-10 ip1<2:0>: interrupt priority bits 111 = interrupt priority is 7 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 is1<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 unimplemented: read as 0 bit 4-2 ip0<2:0>: interrupt priority bits 111 = interrupt priority is 7 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 is0<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 7-7: ipcx: interrupt priori ty control register (continued) note: this register represents a generic definition of the ipcx register. refer to table 7-2 for the exact bit definitions.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 152 ? 2015-2016 microchip technology inc. register 7-8: offx: interrupt vector address offset register (x = 0-190) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 voff<17:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 voff<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 voff<7:1> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 17-1 voff<17:1>: interrupt vector x address offset bits bit 0 unimplemented: read as 0
? 2015-2016 microchip technology inc. ds60001320d-page 153 pic32mz embedded connectivity with floating point unit (ef) family 8.0 oscillator configuration the pic32mz ef oscillator system has the following modules and features: a total of five external and internal oscillator options as clock sources on-chip pll with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources on-chip user-selectable divisor postscaler on select oscillator sources software-controllable switching between ? various clock sources a fail-safe clock monitor (fscm) that detects clock failure and permits safe application recovery or shutdown with dedicated back-up frc (bfrc) dedicated on-chip pll for usb peripheral flexible reference clock output multiple clock branches for peripherals for better performance flexibility clock switch/slew control with output divider a block diagram of the oscillator system is shown in figure 8-1 . the clock distribution is provided in table 8-1 . note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 42. oscillators with enhanced pll (ds60001250) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). note: devices that support 252 mhz operation should be configured for sysclk <= 200 mhz opera - tion. adjust the dividers of the pbclks, and then increase the sysclk to the desired speed.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 154 ? 2015-2016 microchip technology inc. figure 8-1: pic32mz ef family oscillator diagram notes: 1. a series resistor, r s , may be required for at strip cut crystals, or to eliminate clipping. alternately, to incr ease oscillator circuit gain, add a parallel resistor, r p . 2. the internal feedback resistor, r f , is typically in the range of 2 to 10 m ?? 3. refer to section 42. oscillators with enhanced pll (ds60001250) in the pic32 family reference manual for help in determining the best oscillator components. 4. pbclk1 divided by 2 is available on the osc2 pin in certain clock modes. 5. shaded regions indicate multiple instant iations of a peripheral or feature. 6. refer to table 37-19 in section 37.0 electrical characteristics for frequency limitations. 7. if the devcfg registers are configured for a sysclk speed greater than 200 mhz, these pbclks will be running faster than the maximum rating when the device comes out of reset. to ensure proper operation, firmware must start the device at a speed less than or equal to 200 mhz, adjust the speed of the pbclks, and then raise the sysclk speed to the desired speed. timer1, rtcc clock control logic fail-safe clock monitor fscm int fscm event cosc<2:0> nosc<2:0> oswen fcksm<1:0> secondary oscillator (s osc ) soscen sosco sosci p osc (hs, ec) frcdiv<2:0> wdt, rtcc 8 mhz typical 32.768 khz frc oscillator lprc oscillator s osc lprc frcdiv tun<5:0> postscaler pllidiv<2:0> plliclk f in (6) pllodiv<2:0> 32.768 khz pllmult<6:0> sysclk ? n ? backup frc oscillator 8 mhz typical bfrc n ? (n) (n) (n) refclkox oe to spi, reference clock (5) rodiv<14:0> (n) rotrim<8:0> (m) n spll refclkix p osc frc lprc s osc pbclk1 sysclk rosel<3:0> peripheral bus clock (5,7) peripherals, pbxdiv<6:0> postscaler pbclkx (n) c1 (3) c2 (3) xtal r s (1) enable osc2 (4) osc1 r f (2) primary oscillator (p osc ) r p (1) (m) pll x m usb clock (usbclk) usb pll upllfsel f pll (6) bfrc pllrange<2:0> to adc and flash adc, sqi fvco (6) system pll from p osc (12 or 24 mhz only) cpu x = 1-5, 7, 8 f ref (6) x = 1-4 refoxcon refoxtrim 2n m 512 --------- - + ?? ?? ? ? spll fsys (6) clock switch/ slew poscboost poscgain<1:0> soscboost soscgain<1:0>
? 2015-2016 microchip technology inc. ds60001320d-page 155 pic32mz embedded connectivity with floating point unit (ef) family table 8-1: system and peri pheral clock distribution 8.1 fail-safe clock monitor (fscm) the pic32mz ef oscillator system includes a fail-safe clock monitor (fscm). the fscm monitors the sysclk for continuous operation. if it detects that the sysclk has failed, it switches the sysclk over to the bfrc oscillator and triggers a nmi. the bfrc is an untuned 8 mhz oscillator that will drive the sysclk during fscm event. when the nmi is executed, software can attempt to restart the main oscillator or shut down the system. in sleep mode both the sysclk and the fscm halt, which prevents fscm detection. peripheral clock source frc lprc sosc sysclk usbclk pbclk1 (1) pbclk2pbclk3 pbclk4 pbclk5 pbclk7 pbclk8 refclko1 refclko2 refclko3 cpu x wdt x x (2) deadman timer x (2) x flash x (2) x (2) x (2) adc x x x (3) x comparator x crypto x rng x usb x x (3) can x ethernet x (3) pmp x i 2 c x uart x rtcc x x x (2) ebi x sqi x (3) x spi x x timers x (4) x output compare x input capture x ports x dma x interrupts x prefetch x osc2 pin x (5) note 1: pbclk1 is used by system modules and cannot be turned off. 2: sysclk/pbclk1 is used to fetch data from/to the flash controller, while the frc clock is used for programming. 3: special function register (sfr) access only. 4: timer1 only. 5: pbclk1 divided by 2 is available on the osc2 pin in certain clock modes.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 156 ? 2015-2016 microchip technology inc. 8.2 oscillator control registers table 8-2: oscillator configuration register map virtual address (bf80_#) register name (1) bit range bits all resets (2) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1200 osccon 31:16 frcdiv<2:0> drmen slp2spd 0000 15:0 cosc<2:0> nosc<2:0> clklock slpen cf soscen oswen xx0x 1210 osctun 31:16 0000 15:0 tun<5:0> 00xx 1220 spllcon 31:16 pllodiv<2:0> pllmult<6:0> 01xx 15:0 pllidiv<2:0> plliclk pllrange<2:0> 0x0x 1280 refo1con 31:16 rodiv<14:0> 0000 15:0 on sidl oe rslp divswen active rosel<3:0> 0000 1290 refo1trim 31:16 rotrim<8:0> 0000 15:0 0000 12a0 refo2con 31:16 rodiv<14:0> 0000 15:0 on sidl oe rslp divswen active rosel<3:0> 0000 12b0 refo2trim 31:16 rotrim<8:0> 0000 15:0 0000 12c0 refo3con 31:16 rodiv<14:0> 0000 15:0 on sidl oe rslp divswen active rosel<3:0> 0000 12d0 refo3trim 31:16 rotrim<8:0> 0000 15:0 0000 12e0 refo4con 31:16 rodiv<14:0> 0000 15:0 on sidl oe rslp divswen active rosel<3:0> 0000 12f0 refo4trim 31:16 rotrim<8:0> 0000 15:0 0000 1300 pb1div 31:16 0000 15:0 pbdivrdy pbdiv<6:0> 8801 1310 pb2div 31:16 0000 15:0 on pbdivrdy pbdiv<6:0> 8801 1320 pb3div 31:16 0000 15:0 on pbdivrdy pbdiv<6:0> 8801 1330 pb4div 31:16 0000 15:0 on pbdivrdy pbdiv<6:0> 8801 1340 pb5div 31:16 0000 15:0 on pbdivrdy pbdiv<6:0> 8801 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set, and inv registers at their virtual addresses, plus offs ets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: reset values are dependent on the devcfgx configuration bits and the type of reset.
? 2015-2016 microchip technology inc. ds60001320d-page 157 pic32mz embedded connectivity with floating point unit (ef) family 1360 pb7div 31:16 0000 15:0 on pbdivrdy pbdiv<6:0> 8800 1370 pb8div 31:16 0000 15:0 on pbdivrdy pbdiv<6:0> 8801 13c0 slewcon 31:16 sysdiv<3:0> 0000 15:0 slwdiv<2:0> upen dnen busy 0204 13d0 clkstat 31:16 0000 15:0 lprc rdy sosc rdy posc rdy spll divrdy frcrdy 0000 table 8-2: oscillator configuration register map (continued) virtual address (bf80_#) register name (1) bit range bits all resets (2) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set, and inv registers at their virtual addresses, plus offs ets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: reset values are dependent on the devcfgx configuration bits and the type of reset.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 158 ? 2015-2016 microchip technology inc. register 8-1: osccon: os cillator control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 frcdiv<2:0> 23:16 r/w-0 u-0 r/w-y u-0 u-0 u-0 u-0 u-0 drmen slp2spd (1) 15:8 u-0 r-0 r-0 r-0 u-0 r/w-y r/w-y r/w-y c o s c < 2 : 0 > n o s c < 2 : 0 > 7:0 r/w-0 u-0 u-0 r/w-0 r/w-0, hs u-0 r/w-y r/w-y clklock slpen cf soscen oswen (1) legend: y = value set from configuration bits on por hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-27 unimplemented: read as 0 bit 26-24 frcdiv<2:0>: internal fast rc (frc) oscillator clock divider bits 111 = frc divided by 256 110 = frc divided by 64 101 = frc divided by 32 100 = frc divided by 16 011 = frc divided by 8 010 = frc divided by 4 001 = frc divided by 2 000 = frc divided by 1 (default setting) bit 23 drmen: dream mode enable bit 1 = dream mode is enabled 0 = dream mode is disabled bit 22 unimplemented: read as 0 bit 21 slp2spd: sleep 2-speed startup control bit (1) 1 = use frc as sysclk until selected clock is ready 0 = use the selected clock directly bit 20-15 unimplemented: read as 0 bit 14-12 cosc<2:0>: current oscillator selection bits 111 = internal fast rc (frc) oscillator divided by frcdiv<2:0> bits (frcdiv) 110 = back-up fast rc (bfrc) oscillator 101 = internal low-power rc (lprc) oscillator 100 = secondary oscillator (s osc ) 011 = reserved 010 = primary oscillator (p osc ) (hs or ec) 001 = system pll (spll) 000 = internal fast rc (frc) oscillator divided by frcdiv<2:0> bits (frcdiv) bit 11 unimplemented: read as 0 note 1: the reset value for this bit depends on the setting of the ieso bit (devcfg1<7>). when ieso = 1 , the reset value is 1 . when ieso = 0 , the reset value is 0 . note: writes to this register require an unlock sequence. refer to section 42. oscillators with enhanced pll (ds60001250) in the ?pic32 family reference manual? for details.
? 2015-2016 microchip technology inc. ds60001320d-page 159 pic32mz embedded connectivity with floating point unit (ef) family bit 10-8 nosc<2:0>: new oscillator selection bits 111 = internal fast rc (frc) oscillator divided by frcdiv<2:0> bits (frcdiv) 110 = reserved 101 = internal low-power rc (lprc) oscillator 100 = secondary oscillator (s osc ) 011 = reserved 010 = primary oscillator (p osc ) (hs or ec) 001 = system pll (spll) 000 = internal fast rc (frc) oscillator divided by frcdiv<2:0> bits (frcdiv) on reset, these bits are set to the value of the fnosc<2:0> configuration bits (devcfg1<2:0>). bit 7 clklock: clock selection lock enable bit 1 = clock and pll selections are locked 0 = clock and pll selections are not locked and may be modified bit 6-5 unimplemented: read as 0 bit 4 slpen: sleep mode enable bit 1 = device will enter sleep mode when a wait instruction is executed 0 = device will enter idle mode when a wait instruction is executed bit 3 cf: clock fail detect bit 1 = fscm has detected a clock failure 0 = no clock failure has been detected bit 2 unimplemented: read as 0 bit 1 soscen: secondary oscillator (s osc ) enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 0 oswen: oscillator switch enable bit (1) 1 = initiate an oscillator switch to selection specified by nosc<2:0> bits 0 = oscillator switch is complete register 8-1: osccon: os cillator control register note 1: the reset value for this bit depends on the setting of the ieso bit (devcfg1<7>). when ieso = 1 , the reset value is 1 . when ieso = 0 , the reset value is 0 . note: writes to this register require an unlock sequence. refer to section 42. oscillators with enhanced pll (ds60001250) in the ?pic32 family reference manual? for details.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 160 ? 2015-2016 microchip technology inc. register 8-2: osctun: frc tuning register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tun<5:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-6 unimplemented: read as 0 bit 5-0 tun<5:0>: frc oscillator tuning bits (1) 100000 = center frequency -2% 100001 = 111111 = 000000 = center frequency; oscillator runs at nominal frequency (8 mhz) 000001 = 011110 = 011111 = center frequency +2% note 1: osctun functionality has been provided to help customers compensate for temperature effects on the frc frequency over a wide range of temperatures. the tuning step size is an approximation, and is neithe r characterized nor tested. note: writes to this register require an unlock sequence. refer to section 42. oscillators with enhanced pll (ds60001250) in the ?pic32 family reference manual? for details.
? 2015-2016 microchip technology inc. ds60001320d-page 161 pic32mz embedded connectivity with floating point unit (ef) family register 8-3: spllcon: system pll control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 r/w-y r/w-y r/w-y pllodiv<2:0> 23:16 u-0 r/w-y r/w-y r/w-y r/w-y r/w-y r/w-y r/w-y pllmult<6:0> 15:8 u-0 u-0 u-0 u-0 u-0 r/w-y r/w-y r/w-y pllidiv<2:0> 7:0 r/w-y u-0 u-0 u-0 u-0 r/w-y r/w-y r/w-y plliclk pllrange<2:0> legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-27 unimplemented: read as 0 bit 26-24 pllodiv<2:0>: system pll output clock divider bits 111 = reserved 110 = reserved 101 = pll divide by 32 100 = pll divide by 16 011 = pll divide by 8 010 = pll divide by 4 001 = pll divide by 2 000 = reserved the default setting is specified by the fpllodiv<2:0> configuration bits in the devcfg2 register. refer to register 34-5 in section 34.0 special features for information. bit 23 unimplemented: read as 0 bit 22-16 pllmult<6:0>: system pll multiplier bits 1111111 = multiply by 128 1111110 = multiply by 127 1111101 = multiply by 126 1111100 = multiply by 125 0000000 = multiply by 1 the default setting is specified by the fpllmult<6:0> configuration bits in the devcfg2 register. refer to register 34-5 in section 34.0 special features for information. bit 15-11 unimplemented: read as 0 note 1: writes to this register require an unlock sequence. refer to section 42. oscillators with enhanced pll (ds60001250) in the ?pic32 family reference manual? for details. 2: writes to this register are not allowed if the spll is selected as a clock source (cosc<2:0> = 001 ).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 162 ? 2015-2016 microchip technology inc. bit 10-8 pllidiv<2:0>: system pll input clock divider bits 111 = divide by 8 110 = divide by 7 101 = divide by 6 100 = divide by 5 011 = divide by 4 010 = divide by 3 001 = divide by 2 000 = divide by 1 the default setting is specified by the fpllidiv<2:0> configuration bits in the devcfg2 register. if th e plliclk is set for frc, this setting is ignored by the pll and the divider is set for divide-by-1. refer to register 34-5 in section 34.0 special features for information. bit 7 plliclk: system pll input clock source bit 1 = frc is selected as the input to the system pll 0 = p osc is selected as the input to the system pll the por default is specified by the fplliclk configuration bit in the devcfg2 register. refer to register 34-5 in section 34.0 special features for information. bit 6-3 unimplemented: read as 0 bit 2-0 pllrange<2:0>: system pll frequency range selection bits 111 = reserved 110 = reserved 101 = 34-64 mhz 100 = 21-42 mhz 011 = 13-26 mhz 010 = 8-16 mhz 001 = 5-10 mhz 000 = bypass the default setting is specified by the fpllrng<2:0> configuration bits in the devcfg2 register. r efer to register 34-5 in section 34.0 special features for information. register 8-3: spllcon: system pll control register note 1: writes to this register require an unlock sequence. refer to section 42. oscillators with enhanced pll (ds60001250) in the ?pic32 family reference manual? for details. 2: writes to this register are not allowed if the spll is selected as a clock source (cosc<2:0> = 001 ).
? 2015-2016 microchip technology inc. ds60001320d-page 163 pic32mz embedded connectivity with floating point unit (ef) family register 8-4: refoxcon: reference osci llator control register (x = 1-4) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rodiv<14:8> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rodiv<7:0> 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0, hc r-0, hs, hc on (1) s i d lo e rslp (2) divswen active (1) 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 rosel<3:0> (3) legend: hc = hardware cleared hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 unimplemented: read as 0 bit 30-16 rodiv<14:0> reference clock divider bits the value selects the reference clock divider bits (see figure 8-1 for details). a value of 0 selects no divider. bit 15 on: output enable bit (1) 1 = reference oscillator module is enabled 0 = reference oscillator module is disabled bit 14 unimplemented: read as 0 bit 13 sidl: peripheral stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 oe: reference clock output enable bit 1 = reference clock is driven out on refclkox pin 0 = reference clock is not driven out on refclkox pin bit 11 rslp: reference oscillator module run in sleep bit (2) 1 = reference oscillator module output continues to run in sleep 0 = reference oscillator module output is disabled in sleep bit 10 unimplemented: read as 0 bit 9 divswen: divider switch enable bit 1 = divider switch is in progress 0 = divider switch is complete bit 8 active: reference clock request status bit (1) 1 = reference clock request is active 0 = reference clock request is not active bit 7-4 unimplemented: read as 0 bit 3-0 rosel<3:0>: reference clock source select bits (3) 1111 = reserved 1001 = bfrc 1000 =refclkix 0111 = system pll output 0110 = reserved 0101 =s osc 0100 =lprc 0011 =frc 0010 =p osc 0001 = pbclk1 0000 = sysclk note 1: do not write to this register when the on bit is not equal to the active bit. 2: this bit is ignored when the rosel<3:0> bits = 0000 or 0001 . 3: the rosel<3:0> bits should not be written while the active bit is 1 , as undefined behavior may result.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 164 ? 2015-2016 microchip technology inc. register 8-5: refoxtrim: reference os cillator trim register (x = 1-4) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rotrim<8:1> 23:16 r/w-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 rotrim<0> 15:8 u-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-23 rotrim<8:0>: reference oscillator trim bits 111111111 = 511/512 divisor added to rodiv value 111111110 = 510/512 divisor added to rodiv value 100000000 = 256/512 divisor added to rodiv value 000000010 = 2/512 divisor added to rodiv value 000000001 = 1/512 divisor added to rodiv value 000000000 = 0 divisor added to rodiv value bit 22-0 unimplemented: read as 0 note 1: while the on bit (refoxcon<15>) is 1 , writes to this register do not take effect until the divswen bit is also set to 1 . 2: do not write to this register when the on bit (refoxcon<15>) is not equal to the active bit (refoxcon<8>). 3: specified values in this register do not take effect if rodiv<14:0> (refoxcon<30:16>) = 0.
? 2015-2016 microchip technology inc. ds60001320d-page 165 pic32mz embedded connectivity with floating point unit (ef) family register 8-6: pbxdiv: peripheral bus x cl ock divisor control register (x = 1-7) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-1 u-0 u-0 u-0 r-1 u-0 u-0 u-0 on (1) pbdivrdy 7:0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x pbdiv<6:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 on: peripheral bus x output clock enable bit (1) 1 = output clock is enabled 0 = output clock is disabled bit 14-12 unimplemented: read as 0 bit 11 pbdivrdy: peripheral bus x clock divisor ready bit 1 = clock divisor logic is not switching divisors and the pbxdiv<6:0> bits may be written 0 = clock divisor logic is currently switching values and the pbxdiv<6:0> bits cannot be written bit 10-7 unimplemented: read as 0 bit 6-0 pbdiv<6:0>: peripheral bus x clock divisor control bits 1111111 = pbclkx is sysclk divided by 128 1111110 = pbclkx is sysclk divided by 127 0000011 = pbclkx is sysclk divided by 4 0000010 = pbclkx is sysclk divided by 3 0000001 = pbclkx is sysclk divided by 2 (default value for x ? 7) 0000000 = pbclkx is sysclk divided by 1 (default value for x = 7) note 1: the clock for peripheral bus 1 cannot be turned off. therefore, the on bit in the pb1div register cannot be written as a 0 . note: writes to this register require an unlock sequence. refer to section 42. oscillators with enhanced pll (ds60001250) in the ?pic32 family reference manual? for details.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 166 ? 2015-2016 microchip technology inc. register 8-7: slewcon: osci llator slew control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 sysdiv<3:0> (1) 15:8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-1 r/w-0 s l w d i v < 2 : 0 > 7:0 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r-0, hs, hc upen dnen busy legend: hc = hardware cleared hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-20 unimplemented: read as 0 bit 19-16 sysdiv<3:0>: system clock divide control bits (1) 1111 = sysclk is divided by 16 1110 = sysclk is divided by 15 0010 = sysclk is divided by 3 0001 = sysclk is divided by 2 0000 = sysclk is not divided bit 15-11 unimplemented: read as 0 bit 10-8 slwdiv<2:0>: slew divisor steps control bits these bits control the maximum division steps used when slewing during a frequency change. 111 = steps are divide by 128, 64, 32, 16, 8, 4, 2, and then no divisor 110 = steps are divide by 64, 32, 16, 8, 4, 2, and then no divisor 101 = steps are divide by 32, 16, 8, 4, 2, and then no divisor 100 = steps are divide by 16, 8, 4, 2, and then no divisor 011 = steps are divide by 8, 4, 2, and then no divisor 010 = steps are divide by 4, 2, and then no divisor 001 = steps are divide by 2, and then no divisor 000 = no divisor is used during slewing note: the steps apply in reverse order (i.e., 2, 4, 8, etc.) during a downward frequency change. bit 7-3 unimplemented: read as 0 bit 2 upen: upward slew enable bit 1 = slewing enabled for switching to a higher frequency 0 = slewing disabled for switching to a higher frequency bit 1 dnen: downward slew enable bit 1 = slewing enabled for switching to a lower frequency 0 = slewing disabled for switching to a lower frequency bit 0 busy: clock switching slewing active status bit 1 = clock frequency is being actively slewed to the new frequency 0 = clock switch has reached its final value note 1: the sysdiv<3:0> bit settings are ignored if both upen and dnen = 0 , and sysclk will be divided by 1.
? 2015-2016 microchip technology inc. ds60001320d-page 167 pic32mz embedded connectivity with floating point unit (ef) family register 8-8: clkstat: osci llator clock status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 r-0 r-0 u-0 r-0 r-0 r-0 lprcrdy soscrdy poscrdy divspllrdy frcrdy legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-6 unimplemented: read as 0 bit 5 lprcrdy : low-power rc (lprc) oscillator ready status bit 1 = lprc is stable and ready 0 = lprc is disabled or not operating bit 4 soscrdy: secondary oscillator (s osc ) ready status bit 1 = s osc is stable and ready 0 = s osc is disabled or not operating bit 3 unimplemented: read as 0 bit 2 poscrdy: primary oscillator (p osc ) ready status bit 1 = p osc is stable and ready 0 = p osc is disabled or not operating bit 1 divspllrdy: divided system pll ready status bit 1 = divided system pll is ready 0 = divided system pll is not ready bit 0 frcrdy: fast rc (frc) oscillator ready status bit 1 = frc is stable and ready 0 = frc is disabled for not operating
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 168 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 169 pic32mz embedded connectivity with floating point unit (ef) family 9.0 prefetch module the prefetch module is a performance enhancing module that is included in the pic32mz ef family of devices. when running at high-clock rates, wait states must be inserted into program flash memory (pfm) read transactions to meet the access time of the pfm. wait states can be hidden to the core by prefetching and storing instructions in a temporary holding area that the cpu can access quickly. although the data path to the cpu is 32 bits wide, the data path to the pfm is 128 bits wide. this wide data path provides the same bandwidth to the cpu as a 32-bit path running at four times the frequency. the prefetch module holds a subset of pfm in temporary holding spaces known as lines. each line contains a tag and data field. normally, the lines hold a copy of what is currently in memory to make instructions or data available to the cpu without flash wait states. the following are key features of the prefetch module: 4x16 byte fully-associative lines one line for cpu instructions one line for cpu data two lines for peripheral data 16-byte parallel memory fetch configurable predictive prefetch error detection and correction a simplified block diagram of the prefetch module is shown in figure 9-1 . figure 9-1: prefetch module block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive refer - ence source. to complement the informa - tion in this data sheet, refer to section 41. prefetch module for devices with l1 cpu cache (ds60001183) in the ?pic32 family reference manual? , which is avail - able from the microchip web site ( www.microchip.com/pic32 ). bus control prefetch buffer line control ta g data program flash memory (pfm) cpu cpu sysclk
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 170 ? 2015-2016 microchip technology inc. 9.1 prefetch control registers table 9-1: prefetch register map virtual address (bf8e_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0000 precon 31:16 pfmsecen 0000 15:0 prefen<1:0> pfmws<2:0> 0007 0010 prestat 31:16 pfmded pfmsec 0000 15:0 pfmseccnt<7:0> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual addr ess, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 171 pic32mz embedded connectivity with floating point unit (ef) family register 9-1: precon: pref etch module control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 u-0 pfmsecen 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 prefen<1:0> p f m w s < 2 : 0 > (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-27 unimplemented: read as 0 bit 26 pfmsecen: flash sec interrupt enable bit 1 = generate an interrupt when the pfmsec bit (prestat<26>) is set 0 = do not generate an interrupt when the pfmsec bit is set bit 25-6 unimplemented: read as 0 bit 5-4 prefen<1:0>: predictive prefetch enable bits 11 = enable predictive prefetch for any address 10 = enable predictive prefetch for cpu instructions and cpu data 01 = enable predictive prefetch for cpu instructions only 00 = disable predictive prefetch bit 3 unimplemented: read as 0 bit 2-0 pfmws<2:0>: pfm access time defined in terms of sysclk wait states bits (1) 111 = seven wait states 010 = two wait states 001 = one wait state 000 = zero wait states note 1: for the wait states to sysclk relationship, refer to table 37-13 in section37.0 electrical characteristics .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 172 ? 2015-2016 microchip technology inc. register 9-2: prestat: prefetch module status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 r/w-0, hs r/w-0, hs u-0 u-0 pfmded pfmsec 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs pfmseccnt<7:0> legend: hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-28 unimplemented: read as 0 bit 27 pfmded: flash double-bit error detected (ded) status bit this bit is set in hardware and can only be cleared (i.e., set to 0) in software. 1 = a ded error has occurred 0 = a ded error has not occurred bit 26 pfmsec: flash single-bit error corrected (sec) status bit 1 = a sec error occurred when pfmseccnt<7:0> was equal to zero 0 = a sec error has not occurred bit 25-8 unimplemented: read as 0 bit 7-0 pfmseccnt<7:0>: flash sec count bits 11111111 - 00000000 = sec count
? 2015-2016 microchip technology inc. ds60001320d-page 173 pic32mz embedded connectivity with floating point unit (ef) family 10.0 direct memory access (dma) controller the direct memory access (dma) controller is a bus master module useful for data transfers between different devices without cpu intervention. the source and destination of a dma transfer can be any of the memory mapped modules existent in the device such as spi, uart, pmp, etc., or memory itself. the following are key features of the dma controller: eight identical channels, each featuring: - auto-increment source and destination address registers - source and destination pointers - memory to memory and memory to peripheral transfers automatic word-size detection: - transfer granularity, down to byte level - bytes need not be word-aligned at source and destination fixed priority channel arbitration flexible dma channel operating modes: - manual (software) or automatic (interrupt) dma requests - one-shot or auto-repeat block transfer modes - channel-to-channel chaining flexible dma requests: - a dma request can be selected from any of the peripheral interrupt sources - each channel can select any (appropriate) observable interrupt as its dma request source - a dma transfer abort can be selected from any of the peripheral interrupt sources - up to 2-byte pattern (data) match transfer termination multiple dma channel status interrupts: - dma channel block transfer complete - source empty or half empty - destination full or half full - dma transfer aborted due to an external event - invalid dma address generated dma debug support features: - most recent error address accessed by a dma channel - most recent dma channel to transfer data crc generation module: - crc module can be assigned to any of the available channels - crc module is highly configurable figure 10-1: dma block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive refer - ence source. to complement the informa - tion in this data sheet, refer to section 31. direct memory access (dma) control - ler (ds60001117) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). address decoder channel 0 control channel 1 control channel n control global control (dmacon) bus channel priority arbitration s e l s e l y i 0 i 1 i 2 i n system irq int controller peripheral bus interface dma sysclk system bus + bus arbitration
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 174 ? 2015-2016 microchip technology inc. 10.1 dma control registers table 10-1: dma global register map virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 dmacon 31:16 0000 15:0 on suspend dmabusy 0000 1010 dmastat 31:16 rdwr 0000 15:0 dmach<2:0> 0000 1020 dmaaddr 31:16 dmaaddr<31:0> 0000 15:0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual addr ess, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. table 10-2: dma crc register map virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1030 dcrccon 31:16 byto<1:0> wbo bito 0000 15:0 plen<4:0> crcen crcapp crctyp crcch<2:0> 0000 1040 dcrcdata 31:16 dcrcdata<31:0> 0000 15:0 0000 1050 dcrcxor 31:16 dcrcxor<31:0> 0000 15:0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtua l addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 175 pic32mz embedded connectivity with floating point unit (ef) family table 10-3: dma channel 0 through channel 7 register map virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 1 6/0 1060 dch0con 31:16 chpign<7:0> 0000 15:0 chbusy chpignen chpatlen chchns chen chaed chchn chaen chedet chpri<1:0> 0000 1070 dch0econ 31:16 chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ff00 1080 dch0int 31:16 chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 1090 dch0ssa 31:16 chssa<31:0> 0000 15:0 0000 10a0 dch0dsa 31:16 chdsa<31:0> 0000 15:0 0000 10b0 dch0ssiz 31:16 0000 15:0 chssiz<15:0> 0000 10c0 dch0dsiz 31:16 0000 15:0 chdsiz<15:0> 0000 10d0 dch0sptr 31:16 0000 15:0 chsptr<15:0> 0000 10e0 dch0dptr 31:16 0000 15:0 chdptr<15:0> 0000 10f0 dch0csiz 31:16 0000 15:0 chcsiz<15:0> 0000 1100 dch0cptr 31:16 0000 15:0 chcptr<15:0> 0000 1110 dch0dat 31:16 0000 15:0 chpdat<15:0> 0000 1120 dch1con 31:16 chpign<7:0> 0000 15:0 chbusy chpignen chpatlen chchns chen chaed chchn chaen chedet chpri<1:0> 0000 1130 dch1econ 31:16 chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ff00 1140 dch1int 31:16 chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 1150 dch1ssa 31:16 chssa<31:0> 0000 15:0 0000 1160 dch1dsa 31:16 chdsa<31:0> 0000 15:0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 176 ? 2015-2016 microchip technology inc. 1170 dch1ssiz 31:16 0000 15:0 chssiz<15:0> 0000 1180 dch1dsiz 31:16 0000 15:0 chdsiz<15:0> 0000 1190 dch1sptr 31:16 0000 15:0 chsptr<15:0> 0000 11a0 dch1dptr 31:16 0000 15:0 chdptr<15:0> 0000 11b0 dch1csiz 31:16 0000 15:0 chcsiz<15:0> 0000 11c0 dch1cptr 31:16 0000 15:0 chcptr<15:0> 0000 11d0 dch1dat 31:16 0000 15:0 chpdat<15:0> 0000 11e0 dch2con 31:16 chpign<7:0> 0000 15:0 chbusy chpignen chpatlen chchns chen chaed chchn chaen chedet chpri<1:0> 0000 11f0 dch2econ 31:16 chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ff00 1200 dch2int 31:16 chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 1210 dch2ssa 31:16 chssa<31:0> 0000 15:0 0000 1220 dch2dsa 31:16 chdsa<31:0> 0000 15:0 0000 1230 dch2ssiz 31:16 0000 15:0 chssiz<15:0> 0000 1240 dch2dsiz 31:16 0000 15:0 chdsiz<15:0> 0000 1250 dch2sptr 31:16 0000 15:0 chsptr<15:0> 0000 1260 dch2dptr 31:16 0000 15:0 chdptr<15:0> 0000 1270 dch2csiz 31:16 0000 15:0 chcsiz<15:0> 0000 table 10-3: dma channel 0 through channel 7 register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 1 6/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 177 pic32mz embedded connectivity with floating point unit (ef) family 1280 dch2cptr 31:16 0000 15:0 chcptr<15:0> 0000 1290 dch2dat 31:16 0000 15:0 chpdat<15:0> 0000 12a0 dch3con 31:16 chpign<7:0> 0000 15:0 chbusy chpignen chpatlen chchns chen chaed chchn chaen chedet chpri<1:0> 0000 12b0 dch3econ 31:16 chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ff00 12c0 dch3int 31:16 chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 12d0 dch3ssa 31:16 chssa<31:0> 0000 15:0 0000 12e0 dch3dsa 31:16 chdsa<31:0> 0000 15:0 0000 12f0 dch3ssiz 31:16 0000 15:0 chssiz<15:0> 0000 1300 dch3dsiz 31:16 0000 15:0 chdsiz<15:0> 0000 1310 dch3sptr 31:16 0000 15:0 chsptr<15:0> 0000 1320 dch3dptr 31:16 0000 15:0 chdptr<15:0> 0000 1330 dch3csiz 31:16 0000 15:0 chcsiz<15:0> 0000 1340 dch3cptr 31:16 0000 15:0 chcptr<15:0> 0000 1350 dch3dat 31:16 0000 15:0 chpdat<15:0> 0000 1360 dch4con 31:16 chpign<7:0> 0000 15:0 chbusy chpignen chpatlen chchns chen chaed chchn chaen chedet chpri<1:0> 0000 1370 dch4econ 31:16 chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ff00 1380 dch4int 31:16 chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 table 10-3: dma channel 0 through channel 7 register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 1 6/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 178 ? 2015-2016 microchip technology inc. 1390 dch4ssa 31:16 chssa<31:0> 0000 15:0 0000 13a0 dch4dsa 31:16 chdsa<31:0> 0000 15:0 0000 13b0 dch4ssiz 31:16 0000 15:0 chssiz<15:0> 0000 13c0 dch4dsiz 31:16 0000 15:0 chdsiz<15:0> 0000 13d0 dch4sptr 31:16 0000 15:0 chsptr<15:0> 0000 13e0 dch4dptr 31:16 0000 15:0 chdptr<15:0> 0000 13f0 dch4csiz 31:16 0000 15:0 chcsiz<15:0> 0000 1400 dch4cptr 31:16 0000 15:0 chcptr<15:0> 0000 1410 dch4dat 31:16 0000 15:0 chpdat<15:0> 0000 1420 dch5con 31:16 chpign<7:0> 0000 15:0 chbusy chpignen chpatlen chchns chen chaed chchn chaen chedet chpri<1:0> 0000 1430 dch5econ 31:16 chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ff00 1440 dch5int 31:16 chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 1450 dch5ssa 31:16 chssa<31:0> 0000 15:0 0000 1460 dch5dsa 31:16 chdsa<31:0> 0000 15:0 0000 1470 dch5ssiz 31:16 0000 15:0 chssiz<15:0> 0000 1480 dch5dsiz 31:16 0000 15:0 chdsiz<15:0> 0000 1490 dch5sptr 31:16 0000 15:0 chsptr<15:0> 0000 table 10-3: dma channel 0 through channel 7 register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 1 6/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 179 pic32mz embedded connectivity with floating point unit (ef) family 14a0 dch5dptr 31:16 0000 15:0 chdptr<15:0> 0000 14b0 dch5csiz 31:16 0000 15:0 chcsiz<15:0> 0000 14c0 dch5cptr 31:16 0000 15:0 chcptr<15:0> 0000 14d0 dch5dat 31:16 0000 15:0 chpdat<15:0> 0000 14e0 dch6con 31:16 chpign<7:0> 0000 15:0 chbusy chpignen chpatlen chchns chen chaed chchn chaen chedet chpri<1:0> 0000 14f0 dch6econ 31:16 chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ff00 1500 dch6int 31:16 chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 1510 dch6ssa 31:16 chssa<31:0> 0000 15:0 0000 1520 dch6dsa 31:16 chdsa<31:0> 0000 15:0 0000 1530 dch6ssiz 31:16 0000 15:0 chssiz<15:0> 0000 1540 dch6dsiz 31:16 0000 15:0 chdsiz<15:0> 0000 1550 dch6sptr 31:16 0000 15:0 chsptr<15:0> 0000 1560 dch6dptr 31:16 0000 15:0 chdptr<15:0> 0000 1570 dch6csiz 31:16 0000 15:0 chcsiz<15:0> 0000 1580 dch6cptr 31:16 0000 15:0 chcptr<15:0> 0000 1590 dch6dat 31:16 0000 15:0 chpdat<15:0> 0000 15a0 dch7con 31:16 chpign<7:0> 0000 15:0 chbusy chpignen chpatlen chchns chen chaed chchn chaen chedet chpri<1:0> 0000 table 10-3: dma channel 0 through channel 7 register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 1 6/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 180 ? 2015-2016 microchip technology inc. 15b0 dch7econ 31:16 chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ff00 15c0 dch7int 31:16 chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 15d0 dch7ssa 31:16 chssa<31:0> 0000 15:0 0000 15e0 dch7dsa 31:16 chdsa<31:0> 0000 15:0 0000 15f0 dch7ssiz 31:16 0000 15:0 chssiz<15:0> 0000 1600 dch7dsiz 31:16 0000 15:0 chdsiz<15:0> 0000 1610 dch7sptr 31:16 0000 15:0 chsptr<15:0> 0000 1620 dch7dptr 31:16 0000 15:0 chdptr<15:0> 0000 1630 dch7csiz 31:16 0000 15:0 chcsiz<15:0> 0000 1640 dch7cptr 31:16 0000 15:0 chcptr<15:0> 0000 1650 dch7dat 31:16 0000 15:0 chpdat<15:0> 0000 table 10-3: dma channel 0 through channel 7 register map (continued) virtual address (bf81_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 1 6/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 181 pic32mz embedded connectivity with floating point unit (ef) family register 10-1: dmacon: dma co ntroller control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 u-0 u-0 r/w-0 r/w-0 u-0 u-0 u-0 on suspend dmabusy 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 on: dma on bit 1 = dma module is enabled 0 = dma module is disabled bit 14-13 unimplemented: read as 0 bit 12 suspend: dma suspend bit 1 = dma transfers are suspended to allow cpu uninterrupted access to data bus 0 = dma operates normally bit 11 dmabusy: dma module busy bit 1 = dma module is active and is transferring data 0 = dma module is disabled and not actively transferring data bit 10-0 unimplemented: read as 0
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 182 ? 2015-2016 microchip technology inc. register 10-2: dmastat: dma status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 rdwr 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 dmach<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 rdwr: read/write status bit 1 = last dma bus access when an error was detected was a read 0 = last dma bus access when an error was detected was a write bit 30-3 unimplemented: read as 0 bit 2-0 dmach<2:0>: dma channel bits these bits contain the value of the most recent active dma channel when an error was detected. register 10-3: dmaaddr: dma address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 dmaaddr<31:0>: dma module address bits these bits contain the address of the most recent dma access when an error was detected.
? 2015-2016 microchip technology inc. ds60001320d-page 183 pic32mz embedded connectivity with floating point unit (ef) family register 10-4: dcrccon: dma crc control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 byto<1:0> wbo (1) b i t o 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 plen<4:0> 7:0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 crcen crcapp (1) crctyp crcch<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-30 unimplemented: read as 0 bit 29-28 byto<1:0>: crc byte order selection bits 11 = endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order per half-word) 10 = swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per half-word) 01 = endian byte swap on word boundaries (i.e., reverse source byte order) 00 = no swapping (i.e., source byte order) bit 27 wbo: crc write byte order selection bit (1) 1 = source data is written to the destination re-ordered as defined by byto<1:0> 0 = source data is written to the destination unaltered bit 26-25 unimplemented: read as 0 bit 24 bito: crc bit order selection bit when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): 1 = the ip header checksum is calculated least significant bit (lsb) first (i.e., reflected) 0 = the ip header checksum is calculated most significant bit (msb) first (i.e., not reflected) when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): 1 = the lfsr crc is calculated least significant bit first (i.e., reflected) 0 = the lfsr crc is calculated most significant bit first (i.e., not reflected) bit 23-13 unimplemented: read as 0 bit 12-8 plen<4:0>: polynomial length bits (1) when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): these bits are unused. when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): denotes the length of the polynomial C 1. bit 7 crcen: crc enable bit 1 = crc module is enabled and channel transfers are routed through the crc module 0 = crc module is disabled and channel transfers proceed normally note 1: when wbo = 1 , unaligned transfers are not supported and the crcapp bit cannot be set.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 184 ? 2015-2016 microchip technology inc. bit 6 crcapp: crc append mode bit (1) 1 = the dma transfers data from the source into the crc but not to the destination. when a block transfer completes the dma writes the calculated crc value to the location given b y chxdsa 0 = the dma transfers data from the source through the crc obeying wbo as it writes the data to the destination bit 5 crctyp: crc type selection bit 1 = the crc module will calculate an ip header checksum 0 = the crc module will calculate a lfsr crc bit 4-3 unimplemented: read as 0 bit 2-0 crcch<2:0>: crc channel select bits 111 = crc is assigned to channel 7 110 = crc is assigned to channel 6 101 = crc is assigned to channel 5 100 = crc is assigned to channel 4 011 = crc is assigned to channel 3 010 = crc is assigned to channel 2 001 = crc is assigned to channel 1 000 = crc is assigned to channel 0 register 10-4: dcrccon: dma crc co ntrol register (continued) note 1: when wbo = 1 , unaligned transfers are not supported and the crcapp bit cannot be set.
? 2015-2016 microchip technology inc. ds60001320d-page 185 pic32mz embedded connectivity with floating point unit (ef) family register 10-5: dcrcdata: dma crc data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 dcrcdata<31:0>: crc data register bits writing to this register will seed the crc generator. reading from this register will return the current value of the crc. bits greater than plen will return 0 on any read. when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): only the lower 16 bits contain ip header checksum information. the upper 16 bits are always 0 . data written to this register is converted and read back in 1s complement form (i.e., current ip header checksum value). when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): bits greater than plen will return 0 on any read. register 10-6: dcrcxor: dma crcxor enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 dcrcxor<31:0>: crc xor register bits when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): this register is unused. when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): 1 = enable the xor input to the shift register 0 = disable the xor input to the shift register; data is shifted in directly from the previous stage in the register
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 186 ? 2015-2016 microchip technology inc. register 10-7: dchxcon: dma channel x control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chpign<7:0> 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 u-0 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 chbusy c h i p g n e n chpatlen chchns (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r-0 r/w-0 r/w-0 chen (2) chaed chchn chaen chedet chpri<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 chpign<7:0>: channel register data bits pattern terminate mode: any byte matching these bits during a pattern match may be ignored during the pattern match determina- tion when the chpignen bit is set. if a byte is read that is identical to this data byte, the pattern match logic will treat it as a dont care when the pattern matching logic is enabled and the chpigen bit is set. bit 23-16 unimplemented: read as 0 bit 15 chbusy: channel busy bit 1 = channel is active or has been enabled 0 = channel is inactive or has been disabled bit 14 unimplemented: read as 0 bit 13 chpignen: enable pattern ignore byte bit 1 = treat any byte that matches the chpign<7:0> bits as a dont care when pattern matching is enabled 0 = disable this feature bit 12 unimplemented: read as 0 bit 11 chpatlen: pattern length bit 1 = 2 byte length 0 = 1 byte length bit 10-9 unimplemented: read as 0 bit 8 chchns: chain channel selection bit (1) 1 = chain to channel lower in natural priority (ch1 will be enabled by ch2 transfer complete) 0 = chain to channel higher in natural priority (ch1 will be enabled by ch0 transfer complete) bit 7 chen: channel enable bit (2) 1 = channel is enabled 0 = channel is disabled bit 6 chaed: channel allow events if disabled bit 1 = channel start/abort events will be registered, even if the channel is disabled 0 = channel start/abort events will be ignored if the channel is disabled bit 5 chchn: channel chain enable bit 1 = allow channel to be chained 0 = do not allow channel to be chained note 1: the chain selection bit takes effect when chaining is enabled (i.e., chchn = 1 ). 2: when the channel is suspended by clearing this bit, the user application should poll the chbusy bit (if available on the device variant) to see when the channel is suspended, as it may take some clock c ycles to complete a current transaction before the channel is suspended.
? 2015-2016 microchip technology inc. ds60001320d-page 187 pic32mz embedded connectivity with floating point unit (ef) family bit 4 chaen: channel automatic enable bit 1 = channel is continuously enabled, and not automatically disabled after a block transfer is complete 0 = channel is disabled on block transfer complete bit 3 unimplemented: read as 0 bit 2 chedet: channel event detected bit 1 = an event has been detected 0 = no events have been detected bit 1-0 chpri<1:0>: channel priority bits 11 = channel has priority 3 (highest) 10 = channel has priority 2 01 = channel has priority 1 00 = channel has priority 0 register 10-7: dchxcon: dma channel x control register (continued) note 1: the chain selection bit takes effect when chaining is enabled (i.e., chchn = 1 ). 2: when the channel is suspended by clearing this bit, the user application should poll the chbusy bit (if available on the device variant) to see when the channel is suspended, as it may take some clock c ycles to complete a current transaction before the channel is suspended.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 188 ? 2015-2016 microchip technology inc. register 10-8: dchxecon: dma channel x event control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 chairq<7:0> (1) 15:8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 chsirq<7:0> (1) 7:0 s-0 s-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 cforce cabort paten sirqen airqen legend: s = settable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as 0 bit 23-16 chairq<7:0>: channel transfer abort irq bits (1) 11111111 = interrupt 255 will abort any transfers in progress and set chaif flag 00000001 = interrupt 1 will abort any transfers in progress and set chaif flag 00000000 = interrupt 0 will abort any transfers in progress and set chaif flag bit 15-8 chsirq<7:0>: channel transfer start irq bits (1) 11111111 = interrupt 255 will initiate a dma transfer 00000001 = interrupt 1 will initiate a dma transfer 00000000 = interrupt 0 will initiate a dma transfer bit 7 cforce: dma forced transfer bit 1 = a dma transfer is forced to begin when this bit is written to a 1 0 = this bit always reads 0 bit 6 cabort: dma abort transfer bit 1 = a dma transfer is aborted when this bit is written to a 1 0 = this bit always reads 0 bit 5 paten: channel pattern match abort enable bit 1 = abort transfer and clear chen on pattern match 0 = pattern match is disabled bit 4 sirqen: channel start irq enable bit 1 = start channel cell transfer if an interrupt matching chsirq occurs 0 = interrupt number chsirq is ignored and does not start a transfer bit 3 airqen: channel abort irq enable bit 1 = channel transfer is aborted if an interrupt matching chairq occurs 0 = interrupt number chairq is ignored and does not terminate a transfer bit 2-0 unimplemented: read as 0 note 1: see table 7-2: interrupt irq, vector, and bit location for the list of available interrupt irq sources.
? 2015-2016 microchip technology inc. ds60001320d-page 189 pic32mz embedded connectivity with floating point unit (ef) family register 10-9: dchxint: dma channel x interrupt control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chsdie chshie chddie chdhie chb cie chccie chtaie cherie 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as 0 bit 23 chsdie: channel source done interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 22 chshie: channel source half empty interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 21 chddie: channel destination done interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 20 chdhie: channel destination half full interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 19 chbcie: channel block transfer complete interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 18 chccie: channel cell transfer complete interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 17 chtaie: channel transfer abort interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 16 cherie: channel address error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 15-8 unimplemented: read as 0 bit 7 chsdif: channel source done interrupt flag bit 1 = channel source pointer has reached end of source (chsptr = chssiz) 0 = no interrupt is pending bit 6 chshif: channel source half empty interrupt flag bit 1 = channel source pointer has reached midpoint of source (chsptr = chssiz/2) 0 = no interrupt is pending
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 190 ? 2015-2016 microchip technology inc. bit 5 chddif: channel destination done interrupt flag bit 1 = channel destination pointer has reached end of destination (chdptr = chdsiz) 0 = no interrupt is pending bit 4 chdhif: channel destination half full interrupt flag bit 1 = channel destination pointer has reached midpoint of destination (chdptr = chdsiz/2 ) 0 = no interrupt is pending bit 3 chbcif: channel block transfer complete interrupt flag bit 1 = a block transfer has been completed (the larger of chssiz/chdsiz bytes has been transferred), or a pattern match event occurs 0 = no interrupt is pending bit 2 chccif: channel cell transfer complete interrupt flag bit 1 = a cell transfer has been completed (chcsiz bytes have been transferred) 0 = no interrupt is pending bit 1 chtaif: channel transfer abort interrupt flag bit 1 = an interrupt matching chairq has been detected and the dma transfer has been aborted 0 = no interrupt is pending bit 0 cherif: channel address error interrupt flag bit 1 = a channel address error has been detected ? either the source or the destination address is invalid. 0 = no interrupt is pending register 10-9: dchxint: dma channel x in terrupt control register (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 191 pic32mz embedded connectivity with floating point unit (ef) family register 10-10: dchxssa: dma channel x source start address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 chssa<31:0> channel source start address bits channel source start address. note: this must be the physical address of the source. register 10-11: dchxdsa: dma channel x destination start address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 chdsa<31:0>: channel destination start address bits channel destination start address. note: this must be the physical address of the destination.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 192 ? 2015-2016 microchip technology inc. register 10-12: dchxssiz: dma channel x source size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssiz<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssiz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 chssiz<15:0>: channel source size bits 1111111111111111 = 65,535 byte source size 0000000000000010 = 2 byte source size 0000000000000001 = 1 byte source size 0000000000000000 = 65,536 byte source size register 10-13: dchxdsiz: dma channel x destination size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsiz<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsiz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 chdsiz<15:0>: channel destination size bits 1111111111111111 = 65,535 byte destination size 0000000000000010 = 2 byte destination size 0000000000000001 = 1 byte destination size 0000000000000000 = 65,536 byte destination size
? 2015-2016 microchip technology inc. ds60001320d-page 193 pic32mz embedded connectivity with floating point unit (ef) family register 10-14: dchxsptr: dma channel x source pointer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chsptr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chsptr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 chsptr<15:0>: channel source pointer bits 1111111111111111 = points to byte 65,535 of the source 0000000000000001 = points to byte 1 of the source 0000000000000000 = points to byte 0 of the source note: when in pattern detect mode, this register is reset on a pattern detect. register 10-15: dchxdptr: dma channel x destination pointer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chdptr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chdptr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 chdptr<15:0>: channel destination pointer bits 1111111111111111 = points to byte 65,535 of the destination 0000000000000001 = points to byte 1 of the destination 0000000000000000 = points to byte 0 of the destination
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 194 ? 2015-2016 microchip technology inc. register 10-16: dchxcsiz: dma channel x cell-size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chcsiz<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chcsiz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 chcsiz<15:0>: channel cell-size bits 1111111111111111 = 65,535 bytes transferred on an event 0000000000000010 = 2 bytes transferred on an event 0000000000000001 = 1 byte transferred on an event 0000000000000000 = 65,536 bytes transferred on an event register 10-17: dchxcptr: dma channel x cell pointer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chcptr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chcptr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 chcptr<15:0>: channel cell progress pointer bits 1111111111111111 = 65,535 bytes have been transferred since the last event 0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event note: when in pattern detect mode, this register is reset on a pattern detect.
? 2015-2016 microchip technology inc. ds60001320d-page 195 pic32mz embedded connectivity with floating point unit (ef) family register 10-18: dchxdat: dma channel x pattern data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chpdat<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chpdat<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 chpdat<15:0>: channel data register bits pattern terminate mode: data to be matched must be stored in this register to allow terminate on match. all other modes: unused.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 196 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 197 pic32mz embedded connectivity with floating point unit (ef) family 11.0 hi-speed usb with on- the-go (otg) the universal serial bus (usb) module contains analog and digital components to provide a usb 2.0 embedded host, device, or otg implementation with a minimum of external components. the module supports hi-speed, full-speed, or low- speed in any of the operating modes. this module in host mode is intended for use as an embedded host and therefore does not implement a uhci or ohci controller. the usb module consists of the ram controller, packet encode/decode, utm synchronization, end - point control, a dedicated usb dma controller, pull-up and pull-down resistors, and the register interface. a block diagram of the pic32 usb otg module is presented in figure 11-1 . the usb module includes the following features: usb hi-speed, full-speed, and low-speed support for host and device usb otg support with one or more hi-speed, full-speed, or low-speed device integrated signaling resistors integrated analog comparators for v bus monitoring integrated usb transceiver transaction handshaking performed by hardware integrated 8-channel dma to access system ram and flash seven transmit endpoints and seven receive endpoints, in addition to endpoint 0 session request protocol (srp) and host negotiation protocol (hnp) support suspend and resume signaling support dynamic fifo sizing integrated ram for the fifos, eliminating the need for system ram for the fifos link power management support note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 51. hi-speed usb with on-the-go (otg) (ds60001326) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). note 1: the implementation and use of the usb specifications, as well as other third party specifications or technologies, may require licensing; including, but not limited to, usb implementers forum, inc. (also referred to as usb-if). the user is fully responsible for investigating and satisfying any applicable licensing obligations. 2: if the usb module is used, the primary oscillator (p osc ) is limited to either 12 mhz or 24 mhz.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 198 ? 2015-2016 microchip technology inc. figure 11-1: pic32mz ef family usb interface diagram endpoint control ep0 control host epo control function ep1 - ep7 control host transaction scheduler interrupt control ep reg decoder common regs cycle control fifo decoder ram packet encode/decode link power management combine endpoints packet encode packet decode crc gen/check data sync hs negotiation hnp/srp timers usb 2.0 hs phy utm synchronization dma requests interrupts system bus slave mode transmit receive ram controller rx buff tx buff cycle control rx buff tx buff usb pll p osc (12 mhz or 24 mhz only) upllfsel usbclk d+ d- usbid v usb 3 v 3 v bus
? 2015-2016 microchip technology inc. ds60001320d-page 199 pic32mz embedded connectivity with floating point unit (ef) family 11.1 usb otg control registers table 11-1: usb register map 1 virtual address (bf8e_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 usbcsr0 31:16 ep7txif ep6txif ep5txif ep4txif ep3txif ep2txif ep1txif ep0if 0000 15:0 isoupd (1) soft conn (1) hsen hsmode reset resume susp mode suspen func<6:0> (1) 2000 (2) (2) (2) (2) (2) (2) (2) (2) (2) 3004 usbcsr1 31:16 ep7txie ep6txie ep5txie ep4txie ep3txie ep2txie ep1txie ep0ie 00ff 15:0 ep7rxif ep6rxif ep5rxif ep4rxif ep3rxif ep2rxif ep1rxif 0000 3008 usbcsr2 31:16 vbuserrie sessrqie disconie connie sofie resetie resumeie suspie vbuserrif sessreqif disconif connif sofif resetif resumeif suspif 0600 15:0 ep7rxie ep6rxie ep5rxie ep4rxie ep3rxie ep2rxie ep1rxie 00fe 300c usbcsr3 31:16 forcehst fifoacc forcefs forcehs packet testk testj nak endpoint<3:0> 0000 15:0 rfrmnum<10:0> 0000 3010 usb ie0csr0 (3) 31:16 (1) (1) (1) flshfifo svc setend (1) svcrpr (1) send stall (1) setup end (1) dataend (1) sent stall (1) txpkt rdy rxpkt rdy 0000 disping (2) dtwren (2) data tggl (2) nak tmout (2) statpkt (2) reqpkt (2) error (2) setup pkt (2) rxstall (2) 0000 15:0 0000 3018 usb ie0csr2 (3) 31:16 naklim<4:0> (2) speed<1:0> (2) 0000 15:0 rxcnt<6:0> 0000 301c usb ie0csr3 (3) 31:16 mprxen mptxen bigend hbrxen hbtxen dynfifos softcone utmidwid xx00 15:0 0000 3010 usb iencsr0 (4) 31:16 autoset iso (1) mode dma reqen frc dattg dma reqmd (1) (1) incomp tx (1) clrdt sent stall (1) send stall (1) flush under run (1) fifone txpkt rdy 0000 dtwren (2) data tggl (2) nak tmout (2) rxstall (2) setuppkt (2) error (2) 0000 15:0 mult<4:0> txmaxp<10:0> 0000 3014 usb iencsr1 (4) 31:16 autoclr iso (1) dma reqen disnyet (1) dma reqmd (1) (1) incom prx clrdt sentstall (1) sendstall (1) flush dataerr (1) overrun (1) fifofull rxpkt rdy 0000 autorq (2) piderr (2) data twen (2) data tggl (2) rxstall (2) reqpkt (2) derr - nakt (1) error (2) 0000 15:0 mult<4:0> rxmaxp<10:0> 0000 3018 usb iencsr2 (4) 31:16 txinterv<7:0> (2) speed<1:0> (2) protocol<1:0> tep<3:0> 0000 15:0 rxcnt<13:0> 0000 301c usb iencsr3 (1,3) 31:16 rxfifosz<3:0> txfifosz<3:0> 0000 15:0 rxinterv<7:0> speed<1:0> protocol<1:0> tep<3:0> 0000 3020 usb fifo0 31:16 data<31:16> 0000 15:0 data<15:0> 0000 3024 usb fifo1 31:16 data<31:16> 0000 15:0 data<15:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: device mode. 2: host mode. 3: definition for endpoint 0 (endpoint<3:0> (usbcsr<19:16>) = 0). 4: definition for endpoints 1-7 (endpoint<3:0> (usbcsr<19:16>) = 1 through 7).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 200 ? 2015-2016 microchip technology inc. 3028 usb fifo2 31:16 data<31:16> 0000 15:0 data<15:0> 0000 302c usb fifo3 31:16 data<31:16> 0000 15:0 data<15:0> 0000 3030 usb fifo4 31:16 data<31:16> 0000 15:0 data<15:0> 0000 3034 usb fifo5 31:16 data<31:16> 0000 15:0 data<15:0> 0000 3038 usb fifo6 31:16 data<31:16> 0000 15:0 data<15:0> 0000 303c usb fifo7 31:16 data<31:16> 0000 15:0 data<15:0> 0000 3060 usbotg 31:16 rxdpb rxfifosz<3:0> txdpb txfifosz<3:0> 0000 15:0 txedma rxedma bdev fsdev lsdev vbus<1:0> hostmode hostreq session 0080 3064 usb fifoa 31:16 rxfifoad<12:0> 0000 15:0 txfifoad<12:0> 0000 306c usb hwver 31:16 0000 15:0 rc vermajor<4:0> verminor<9:0> 0800 3078 usb info 31:16 vplen<7:0> wtcon<3:0> wtid<3:0> 3c5c 15:0 dmachans<3:0> rambits<3:0> rxendpts<3:0> txendpts<3:0> 8c77 307c usb eofrst 31:16 nrstx nrst lseof<7:0> 0072 15:0 fseof<7:0> hseof<7:0> 7780 3080 usb e0txa 31:16 txhubprt<6:0> multtran txhubadd<6:0> 0000 15:0 txfaddr<6:0> 0000 3084 usb e0rxa 31:16 rxhubprt<6:0> multtran rxhubadd<6:0> 0000 15:0 0000 3088 usb e1txa 31:16 txhubprt<6:0> multtran txhubadd<6:0> 0000 15:0 txfaddr<6:0> 0000 308c usb e1rxa 31:16 rxhubprt<6:0> multtran rxhubadd<6:0> 0000 15:0 rxfaddr<6:0> 0000 3090 usb e2txa 31:16 txhubprt<6:0> multtran txhubadd<6:0> 0000 15:0 txfaddr<6:0> 0000 3094 usb e2rxa 31:16 rxhubprt<6:0> multtran rxhubadd<6:0> 0000 15:0 rxfaddr<6:0> 0000 3098 usb e3txa 31:16 txhubprt<6:0> multtran txhubadd<6:0> 0000 15:0 txfaddr<6:0> 0000 table 11-1: usb register map 1 (continued) virtual address (bf8e_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: device mode. 2: host mode. 3: definition for endpoint 0 (endpoint<3:0> (usbcsr<19:16>) = 0). 4: definition for endpoints 1-7 (endpoint<3:0> (usbcsr<19:16>) = 1 through 7).
? 2015-2016 microchip technology inc. ds60001320d-page 201 pic32mz embedded connectivity with floating point unit (ef) family 309c usb e3rxa 31:16 rxhubprt<6:0> multtran rxhubadd<6:0> 0000 15:0 rxfaddr<6:0> 0000 30a0 us be4txa 31:16 txhubprt<6:0> multtran txhubadd<6:0> 0000 15:0 txfaddr<6:0> 0000 30a4 usb e4rxa 31:16 rxhubprt<6:0> multtran rxhubadd<6:0> 0000 15:0 rxfaddr<6:0> 0000 30a8 usb e5txa 31:16 txhubprt<6:0> multtran txhubadd<6:0> 0000 15:0 txfaddr<6:0> 0000 30ac usb e5rxa 31:16 rxhubprt<6:0> multtran rxhubadd<6:0> 0000 15:0 rxfaddr<6:0> 0000 30b0 usb e6txa 31:16 txhubprt<6:0> multtran txhubadd<6:0> 0000 15:0 txfaddr<6:0> 0000 30b4 usb e6rxa 31:16 rxhubprt<6:0> multtran rxhubadd<6:0> 0000 15:0 rxfaddr<6:0> 0000 30b8 usb e7txa 31:16 txhubprt<6:0> multtran txhubadd<6:0> 0000 15:0 txfaddr<6:0> 0000 30bc usb e7rxa 31:16 rxhubprt<6:0> multtran rxhubadd<6:0> 0000 15:0 rxfaddr<6:0> 0000 3100 usb e0csr0 31:16 indexed by the same bits in usbie0csr0 0000 15:0 0000 3108 usb e0csr2 31:16 indexed by the same bits in usbie0csr2 0000 15:0 0000 310c usb e0csr3 31:16 indexed by the same bits in usbie0csr3 0000 15:0 0000 3110 usb e1csr0 31:16 indexed by the same bits in usbie1csr0 0000 15:0 0000 3114 usb e1csr1 31:16 indexed by the same bits in usbie1csr1 0000 15:0 0000 3118 usb e1csr2 31:16 indexed by the same bits in usbie1csr2 0000 15:0 0000 311c usb e1csr3 31:16 indexed by the same bits in usbie1csr3 0000 15:0 0000 3120 usb e2csr0 31:16 indexed by the same bits in usbie2csr0 0000 15:0 0000 3124 usb e2csr1 31:16 indexed by the same bits in usbie2csr1 0000 15:0 0000 table 11-1: usb register map 1 (continued) virtual address (bf8e_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: device mode. 2: host mode. 3: definition for endpoint 0 (endpoint<3:0> (usbcsr<19:16>) = 0). 4: definition for endpoints 1-7 (endpoint<3:0> (usbcsr<19:16>) = 1 through 7).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 202 ? 2015-2016 microchip technology inc. 3128 usb e2csr2 31:16 indexed by the same bits in usbie2csr2 0000 15:0 0000 312c usb e2csr3 31:16 indexed by the same bits in usbie2csr3 0000 15:0 0000 3130 usb e3csr0 31:16 indexed by the same bits in usbie3csr0 0000 15:0 0000 3134 usb e3csr1 31:16 indexed by the same bits in usbie3csr1 0000 15:0 0000 3138 usb e3csr2 31:16 indexed by the same bits in usbie3csr2 0000 15:0 0000 313c usb e3csr3 31:16 indexed by the same bits in usbie3csr3 0000 15:0 0000 3140 usb e4csr0 31:16 indexed by the same bits in usbie4csr0 0000 15:0 0000 3144 usb e4csr1 31:16 indexed by the same bits in usbie4csr1 0000 15:0 0000 3148 usb e4csr2 31:16 indexed by the same bits in usbie4csr2 0000 15:0 0000 314c usb e4csr3 31:16 indexed by the same bits in usbie4csr3 0000 15:0 0000 3150 usb e5csr0 31:16 indexed by the same bits in usbie5csr0 0000 15:0 0000 3154 usb e5csr1 31:16 indexed by the same bits in usbie5csr1 0000 15:0 0000 3158 usb e5csr2 31:16 indexed by the same bits in usbie5csr2 0000 15:0 0000 315c usb e5csr3 31:16 indexed by the same bits in usbie5csr3 0000 15:0 0000 3160 usb e6csr0 31:16 indexed by the same bits in usbie6csr0 0000 15:0 0000 3164 usb e6csr1 31:16 indexed by the same bits in usbie6csr1 0000 15:0 0000 3168 usb e6csr2 31:16 indexed by the same bits in usbie6csr2 0000 15:0 0000 316c usb e6csr3 31:16 indexed by the same bits in usbie6csr3 0000 15:0 0000 table 11-1: usb register map 1 (continued) virtual address (bf8e_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: device mode. 2: host mode. 3: definition for endpoint 0 (endpoint<3:0> (usbcsr<19:16>) = 0). 4: definition for endpoints 1-7 (endpoint<3:0> (usbcsr<19:16>) = 1 through 7).
? 2015-2016 microchip technology inc. ds60001320d-page 203 pic32mz embedded connectivity with floating point unit (ef) family 3170 usb e7csr0 31:16 indexed by the same bits in usbie7csr0 0000 15:0 0000 3174 usb e7csr1 31:16 indexed by the same bits in usbie7csr1 0000 15:0 0000 3178 usb e7csr2 31:16 indexed by the same bits in usbie7csr2 0000 15:0 0000 317c usb e7csr3 31:16 indexed by the same bits in usbie7csr3 0000 15:0 0000 3200 usb dmaint 31:16 0000 15:0 dma8if dma7if dma6if dma5if dma4if dma3if dma2if dma1if 0000 3204 usb dma1c 31:16 0000 15:0 dmabrstm<1:0> dmaerr dmaep<3:0> dmaie dmamode dmadir dmaen 0000 3208 usb dma1a 31:16 dmaaddr<31:16> 0000 15:0 dmaaddr<15:0> 0000 320c usb dma1n 31:16 dmacount<31:16> 0000 15:0 dmacount<15:0> 0000 3214 usb dma2c 31:16 0000 15:0 dmabrstm<1:0> dmaerr dmaep<3:0> dmaie dmamode dmadir dmaen 0000 3218 usb dma2a 31:16 dmaaddr<31:16> 0000 15:0 dmaaddr<15:0> 0000 321c usb dma2n 31:16 dmacount<31:16> 0000 15:0 dmacount<15:0> 0000 3224 usb dma3c 31:16 0000 15:0 dmabrstm<1:0> dmaerr dmaep<3:0> dmaie dmamode dmadir dmaen 0000 3228 usb dma3a 31:16 dmaaddr<31:16> 0000 15:0 dmaaddr<15:0> 0000 322c usb dma3n 31:16 dmacount<31:16> 0000 15:0 dmacount<15:0> 0000 3234 usb dma4c 31:16 0000 15:0 dmabrstm<1:0> dmaerr dmaep<3:0> dmaie dmamode dmadir dmaen 0000 3238 usb dma4a 31:16 dmaaddr<31:16> 0000 15:0 dmaaddr<15:0> 0000 323c usb dma4n 31:16 dmacount<31:16> 0000 15:0 dmacount<15:0> 0000 3244 usb dma5c 31:16 0000 15:0 dmabrstm<1:0> dmaerr dmaep<3:0> dmaie dmamode dmadir dmaen 0000 table 11-1: usb register map 1 (continued) virtual address (bf8e_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: device mode. 2: host mode. 3: definition for endpoint 0 (endpoint<3:0> (usbcsr<19:16>) = 0). 4: definition for endpoints 1-7 (endpoint<3:0> (usbcsr<19:16>) = 1 through 7).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 204 ? 2015-2016 microchip technology inc. 3248 usb dma5a 31:16 dmaaddr<31:16> 0000 15:0 dmaaddr<15:0> 0000 324c usb dma5n 31:16 dmacount<31:16> 0000 15:0 dmacount<15:0> 0000 3254 usb dma6c 31:16 0000 15:0 dmabrstm<1:0> dmaerr dmaep<3:0> dmaie dmamode dmadir dmaen 0000 3258 usb dma6a 31:16 dmaaddr<31:16> 0000 15:0 dmaaddr<15:0> 0000 325c usb dma6n 31:16 dmacount<31:16> 0000 15:0 dmacount<15:0> 0000 3264 usb dma7c 31:16 0000 15:0 dmabrstm<1:0> dmaerr dmaep<3:0> dmaie dmamode dmadir dmaen 0000 3268 usb dma7a 31:16 dmaaddr<31:16> 0000 15:0 dmaaddr<15:0> 0000 326c usb dma7n 31:16 dmacount<31:16> 0000 15:0 dmacount<15:0> 0000 3274 usb dma8c 31:16 0000 15:0 dmabrstm<1:0> dmaerr dmaep<3:0> dmaie dmamode dmadir dmaen 0000 3278 usb dma8a 31:16 dmaaddr<31:16> 0000 15:0 dmaaddr<15:0> 0000 327c usb dma8n 31:16 dmacount<31:16> 0000 15:0 dmacount<15:0> 0000 3304 usb e1rpc 31:16 0000 15:0 rqpktcnt<15:0> 0000 3308 usb e2rpc 31:16 0000 15:0 rqpktcnt<15:0> 0000 330c usb e3rpc 31:16 0000 15:0 rqpktcnt<15:0> 0000 3310 usb e4rpc 31:16 0000 15:0 rqpktcnt<15:0> 0000 3314 usb e5rpc 31:16 0000 15:0 rqpktcnt<15:0> 0000 3318 usb e6rpc 31:16 0000 15:0 rqpktcnt<15:0> 0000 331c usb e7rpc 31:16 0000 15:0 rqpktcnt<15:0> 0000 table 11-1: usb register map 1 (continued) virtual address (bf8e_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: device mode. 2: host mode. 3: definition for endpoint 0 (endpoint<3:0> (usbcsr<19:16>) = 0). 4: definition for endpoints 1-7 (endpoint<3:0> (usbcsr<19:16>) = 1 through 7).
? 2015-2016 microchip technology inc. ds60001320d-page 205 pic32mz embedded connectivity with floating point unit (ef) family 3340 usb dpbfd 31:16 ep7txd ep6txd ep5txd ep4txd ep3txd ep2txd ep1txd 0000 15:0 ep7rxd ep6rxd ep5rxd ep4rxd ep3rxd ep2rxd ep1rxd 0000 3344 usb tmcon1 31:16 thhsrtn<15:0> 05e6 15:0 tuch<15:0> 4074 3348 usb tmcon2 31:16 0000 15:0 thsbt<3:0> 0000 3360 usb lpmr1 31:16 lpm errie lpm resie lpmackie lpmnyie lpmstie lpmtoie lpmnak (1) lpmen<1:0> lpmres lpmxmt 0000 (2) (2) (2) 0000 15:0 endpoint<3:0> rmtwak hird<3:0> lnkstate<3:0> 0000 3364 usb lpmr2 31:16 0000 15:0 lpmfaddr<6:0> lpmerr (1) lpmres lpmnc lpmack lpmny lpmst 0000 (2) 0000 table 11-1: usb register map 1 (continued) virtual address (bf8e_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: device mode. 2: host mode. 3: definition for endpoint 0 (endpoint<3:0> (usbcsr<19:16>) = 0). 4: definition for endpoints 1-7 (endpoint<3:0> (usbcsr<19:16>) = 1 through 7). table 11-2: usb register map 2 virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 4000 usb crcon 31:16 usbif usbrf usbwkup 0100 15:0 usb idoven usb idval phyiden vbus monen asval monen bsval monen send monen usbie usbrie usb wkupen 8000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 206 ? 2015-2016 microchip technology inc. register 11-1: usbcsr0: usb control status register 0 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 r-0, hs r-0, hs r-0, hs r-0, hs r-0, hs r-0, hs r-0, hs r-0, hs ep7txif ep6txif ep5txif ep4txif ep3txif ep2txif ep1txif ep0if 15:8 r/w-0 r/w-0 r/w-1 r-0, hs r-0 r/w-0 r-0, hc r/w-0 isoupd softconn hsen hsmode reset resume suspmode suspen 7:0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 func<6:0> legend: hs = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as 0 bit 23-17 ep7txif:ep1txif: endpoint n tx interrupt flag bit 1 = endpoint has a transmit interrupt to be serviced 0 = no interrupt event bit 16 ep0if: endpoint 0 interrupt bit 1 = endpoint 0 has an interrupt to be serviced 0 = no interrupt event all epxtx and ep0 bits are cleared when the byte is read. therefore, these bits must be read independently from the remaining bits in this register to avoid accidental clearing. bit 15 isoupd: iso update bit ( device mode only; unimplemented in host mode ) 1 = usb module will wait for a sof token from the time txpktrdy is set before sending the packet 0 = no change in behavior this bit only affects endpoints performing isochronous transfers when in device mode . this bit is unimplemented in host mode . bit 14 softconn: soft connect/disconnect feature selection bit 1 = the usb d+/d- lines are enabled and active 0 = the usb d+/d- lines are disabled and are tri-stated this bit is only available in device mode . bit 13 hsen: hi-speed enable bit 1 = the usb module will negotiate for hi-speed mode when the device is reset by the hub 0 = module only operates in full-speed mode bit 12 hsmode: hi-speed mode status bit 1 = hi-speed mode successfully negotiated during usb reset 0 = module is not in hi-speed mode in device mode , this bit becomes valid when a usb reset completes. in host mode , it becomes valid when the reset bit is cleared. bit 11 reset: module reset status bit 1 = reset signaling is present on the bus 0 = normal module operation in device mode , this bit is read-only. in host mode , this bit is read/write.
? 2015-2016 microchip technology inc. ds60001320d-page 207 pic32mz embedded connectivity with floating point unit (ef) family bit 10 resume: resume from suspend control bit 1 = generate resume signaling when the device is in suspend mode 0 = stop resume signaling in device mode , the software should clear this bit after 10 ms (a maximum of 15 ms) to end resume signal- ing. in host mode , the software should clear this bit after 20 ms. bit 9 suspmode: suspend mode status bit 1 = the usb module is in suspend mode 0 = the usb module is in normal operations this bit is read-only in device mode. in host mode, it can be set by software, and is cleared by hardware. bit 8 suspen: suspend mode enable bit 1 = suspend mode is enabled 0 = suspend mode is not enabled bit 7 unimplemented: read as 0 bit 6-0 func<6:0>: device function address bits these bits are only available in device mode . this field is written with the address received through a set_address command, which will then be used for decoding the function address in subsequent token packets. register 11-1: usbcsr0: usb contro l status register 0 (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 208 ? 2015-2016 microchip technology inc. register 11-2: usbcsr1: usb control status register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 ep7txie ep6txie ep5txie ep4txie ep3txie ep2txie ep1txie ep0ie 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r-0, hs r-0, hs r-0, hs r-0, hs r-0, hs r-0, hs r-0, hs u-0 ep7rxif ep6rxif ep5rxif ep4rxif ep3rxif ep2rxif ep1rxif legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as 0 bit 23-17 ep7txie:ep1txie: endpoint n transmit interrupt enable bits 1 = endpoint transmit interrupt events are enabled 0 = endpoint transmit interrupt events are not enabled bit 16 ep0ie: endpoint 0 interrupt enable bit 1 = endpoint 0 interrupt events are enabled 0 = endpoint 0 interrupt events are not enabled bit 15-8 unimplemented: read as 0 bit 7-1 ep7rxif:ep1rxif: endpoint n rx interrupt bit 1 = endpoint has a receive event to be serviced 0 = no interrupt event bit 0 unimplemented: read as 0
? 2015-2016 microchip technology inc. ds60001320d-page 209 pic32mz embedded connectivity with floating point unit (ef) family register 11-3: usbcsr2: usb control status register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 vbuserrie sessrqie disconie connie sofie resetie resumeie suspie 23:16 r-0, hs r-0, hs r-0, hs r-0, hs r-0, hs r-0, hs r-0, hs r-0, hs vbuserrif sessrqif disconif connif sofif resetif resumeif suspif 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 u-0 ep7rxie ep6rxie ep5rxie ep4rxie ep3rxie ep2rxie ep1rxie legend: hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 vbuserrie: v bus error interrupt enable bit 1 =v bus error interrupt is enabled 0 =v bus error interrupt is disabled bit 30 sessrqie: session request interrupt enable bit 1 = session request interrupt is enabled 0 = session request interrupt is disabled bit 29 disconie: device disconnect interrupt enable bit 1 = device disconnect interrupt is enabled 0 = device disconnect interrupt is disabled bit 28 connie: device connection interrupt enable bit 1 = device connection interrupt is enabled 0 = device connection interrupt is disabled bit 27 sofie: start of frame interrupt enable bit 1 = start of frame event interrupt is enabled 0 = start of frame event interrupt is disabled bit 26 resetie: reset/babble interrupt enable bit 1 = interrupt when reset ( device mode ) or babble ( host mode ) is enabled 0 = reset/babble interrupt is disabled bit 25 resumeie: resume interrupt enable bit 1 = resume signaling interrupt is enabled 0 = resume signaling interrupt is disabled bit 24 suspie: suspend interrupt enable bit 1 = suspend signaling interrupt is enabled 0 = suspend signaling interrupt is disabled bit 23 vbuserrif: v bus error interrupt bit 1 =v bus has dropped below the v bus valid threshold during a session 0 = no interrupt bit 22 sessrqif: session request interrupt bit 1 = session request signaling has been detected 0 = no session request detected bit 21 disconif: device disconnect interrupt bit 1 =in host mode , indicates when a device disconnect is detected. in device mode , indicates when a session ends. 0 = no device disconnect detected bit 20 connif: device connection interrupt bit 1 =in host mode , indicates when a device connection is detected 0 = no device connection detected
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 210 ? 2015-2016 microchip technology inc. bit 19 sofif: start of frame interrupt bit 1 = a new frame has started 0 = no start of frame detected bit 18 resetif: reset/babble interrupt bit 1 =in host mode , indicates babble is detected. in device mode , indicates reset signaling is detected on the bus. 0 = no reset/babble detected bit 17 resumeif: resume interrupt bit 1 = resume signaling is detected on the bus while usb module is in suspend mode 0 = no resume signaling detected bit 16 suspif: suspend interrupt bit 1 = suspend signaling is detected on the bus (device mode) 0 = no suspend signaling detected bit 15-8 unimplemented: read as 0 bit 7-1 ep7rxie:ep1rxie: endpoint n receive interrupt enable bit 1 = receive interrupt is enabled for this endpoint 0 = receive interrupt is not enabled bit 0 unimplemented: read as 0 register 11-3: usbcsr2: usb contro l status register 2 (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 211 pic32mz embedded connectivity with floating point unit (ef) family register 11-4: usbcsr3: usb control status register 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 forcehst fifoacc forcefs forcehs packet testk testj nak 23:16 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 endpoint<3:0> 15:8 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 rfrmum<10:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rfrmnum<7:0> legend: hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 forcehst: test mode force host select bit 1 = forces usb module into host mode , regardless of whether it is connected to any peripheral 0 = normal operation bit 30 fifoacc: test mode endpoint 0 fifo transfer force bit 1 = transfers the packet in the endpoint 0 tx fifo to the endpoint 0 rx fifo 0 = no transfer bit 29 forcefs: test mode force full-speed mode select bit this bit is only active if forcehst = 1 . 1 = forces usb module into full-speed mode. undefined behavior if forcehs = 1 . 0 = if forcehs = 0 , places usb module into low-speed mode. bit 28 forcehs: test mode force hi-speed mode select bit this bit is only active if forcehst = 1 . 1 = forces usb module into hi-speed mode. undefined behavior if forcefs = 1 . 0 = if forcefs = 0 , places usb module into low-speed mode. bit 27 packet: test_packet test mode select bit this bit is only active if module is in hi-speed mode. 1 = the usb module repetitively transmits on the bus a 53-byte test packet. test packet must be loaded into the endpoint 0 fifo before the test mode is entered. 0 = normal operation bit 26 testk: test_k test mode select bit 1 = enters test_k test mode. the usb module transmits a continuous k on the bus. 0 = normal operation this bit is only active if the usb module is in hi-speed mode. bit 25 testj: test_j test mode select bit 1 = enters test_j test mode. the usb module transmits a continuous j on the bus. 0 = normal operation this bit is only active if the usb module is in hi-speed mode. bit 24 nak: test_se0_nak test mode select bit 1 = enter test_se0_nak test mode. the usb module remains in hi-speed mode but responds to any valid in token with a nak 0 = normal operation this mode is only active if module is in hi-speed mode. bit 23-20 unimplemented: read as 0
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 212 ? 2015-2016 microchip technology inc. bit 19-16 endpoint<3:0>: endpoint registers select bits 1111 = reserved 1000 = reserved 0111 = endpoint 7 0000 = endpoint 0 these bits select which endpoint registers are accessed through addresses 3010-301f. bit 15-11 unimplemented: read as 0 bit 10-0 rfrmnum<10:0>: last received frame number bits register 11-4: usbcsr3: usb contro l status register 3 (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 213 pic32mz embedded connectivity with floating point unit (ef) family register 11-5: usbie0csr0: usb indexed endpoint control status register 0 (endpoint 0) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 r/w-0 r/w-0, hc r/w-0 r/w-0, hc flshfifo disping dtwren datatggl 23:16 r/w-0, hc r/w-0, hc r/w-0, hc r/c-0, hs r/w-0, hs r-0, hs r-0 r-0 svcsetend svcrpr sendstall setupend dataend sentstall txpktrdy rxpktrdy naktmout statpkt reqpkt error setuppkt rxstall 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: hc = hardware cleared hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-28 unimplemented: read as 0 bit 27 disping: disable ping tokens control bit ( host mode ) 1 = usb module will not issue ping tokens in data and status phases of a hi-speed control transfer 0 = ping tokens are issued bit 26 dtwren: data toggle write enable bit ( host mode ) 1 = enable the current state of the endpoint 0 data toggle to be written. automatically cleared. 0 = disable data toggle write bit 25 datatggl: data toggle bit ( host mode ) when read, this bit indicates the current state of the endpoint 0 data toggle. if dtwren = 1 , this bit is writable with the desired setting. if dtwren = 0 , this bit is read-only. bit 24 flshfifo: flush fifo control bit 1 = flush the next packet to be transmitted/read from the endpoint 0 fifo. the fifo pointer is reset and the txpktrdy/rxpktrdy bit is cleared. automatically cleared when the operation completes. should only be used when txpktrdy/rxpktrdy = 1 . 0 = no flush operation bit 23 svcsetend: clear setupend control bit ( device mode ) 1 = clear the setupend bit in this register. this bit is automatically cleared. 0 = do not clear naktmout: nak time-out control bit ( host mode ) 1 = endpoint 0 is halted following the receipt of nak responses for longer than the time set by the naklim<4:0> bits (usbicsr<28:24>) 0 = allow the endpoint to continue bit 22 svcrpr: serviced rxpktrdy clear control bit ( device mode ) 1 = clear the rxpktrdy bit in this register. this bit is automatically cleared. 0 = do not clear statpkt: status stage transaction control bit ( host mode ) 1 = when set at the same time as the txpktrdy or reqpkt bit is set, performs a status stage transaction 0 = do not perform a status stage transaction
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 214 ? 2015-2016 microchip technology inc. bit 21 sendstall: send stall control bit ( device mode ) 1 = terminate the current transaction and transmit a stall handshake. this bit is automatically cleared. 0 = do not send stall handshake. reqpkt: in transaction request control bit ( host mode ) 1 = request an in transaction. this bit is cleared when the rxpktrdy bit is set. 0 = do not request an in transaction bit 20 setupend: early control transaction end status bit ( device mode ) 1 = a control transaction ended before the dataend bit has been set. an interrupt will be generated and the fifo flushed at this time. 0 = normal operation this bit is cleared by writing a 1 to the svcsetend bit in this register. error: no response error status bit ( host mode ) 1 = three attempts have been made to perform a transaction with no response from the peripheral. an inter- rupt is generated. 0 = clear this flag. software must write a 0 to this bit to clear it. bit 19 dataend: end of data control bit ( device mode ) the software sets this bit when: setting txpktrdy for the last data packet clearing rxpktrdy after unloading the last data packet setting txpktrdy for a zero length data packet hardware clears this bit. setuppkt: send a setup token control bit ( host mode ) 1 = when set at the same time as the txpktrdy bit is set, the module sends a setup token instea d of an out token for the transaction 0 = normal out token operation setting this bit also clears the data toggle. bit 18 sentstall: stall sent status bit ( device mode ) 1 = stall handshake has been transmitted 0 = software clear of bit rxstall: stall handshake received status bit ( host mode ) 1 = stall handshake was received 0 = software clear of bit bit 17 txpktrdy: tx packet ready control bit 1 = data packet has been loaded into the fifo. it is cleared automatically. 0 = no data packet is ready for transmit bit 16 rxpktrdy: rx packet ready status bit 1 = data packet has been received. interrupt is generated (when enabled) when this bit is set. 0 = no data packet has been received this bit is cleared by setting the svcrpr bit. bit 15-0 unimplemented: read as 0 register 11-5: usbie0csr0: usb indexed endpoint control status register 0 (endpoint 0) (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 215 pic32mz embedded connectivity with floating point unit (ef) family register 11-6: usbie0csr2: usb indexed endpoint control status register 2 (endpoint 0) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 naklim<4:0> 23:16 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 speed<1:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r x c n t < 6 : 0 > legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28-24 naklim<4:0>: endpoint 0 nak limit bits the number of frames/microframes (hi-speed transfers) afte r which endpoint 0 should time-out on receiving a stream of nak responses. bit 23-22 speed<1:0>: operating speed control bits 11 = low-speed 10 = full-speed 01 = hi-speed 00 = reserved bit 21-7 unimplemented: read as 0 bit 6-0 rxcnt<6:0>: receive count bits the number of received data bytes in the endpoint 0 fifo. the value returned changes as the contents of the fifo change and is only valid while rxpktrdy is set.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 216 ? 2015-2016 microchip technology inc. register 11-7: usbie0csr3: usb indexed endpoint control status register 3 (endpoint 0) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-x r-x r-0 r-x r-x r-x r-1 r-0 mprxen mptxen bigend hbrxen hbtxen dynfifos softcone utmidwid 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 mprxen: automatic amalgamation option bit 1 = automatic amalgamation of bulk packets is done 0 = no automatic amalgamation bit 30 mptxen: automatic splitting option bit 1 = automatic splitting of bulk packets is done 0 = no automatic splitting bit 29 bigend: byte ordering option bit 1 = big endian ordering 0 = little endian ordering bit 28 hbrxen: high-bandwidth rx iso option bit 1 = high-bandwidth rx iso endpoint support is selected 0 = no high-bandwidth rx iso support bit 27 hbtxen: high-bandwidth tx iso option bit 1 = high-bandwidth tx iso endpoint support is selected 0 = no high-bandwidth tx iso support bit 26 dynfifos: dynamic fifo sizing option bit 1 = dynamic fifo sizing is supported 0 = no dynamic fifo sizing bit 25 softcone: soft connect/disconnect option bit 1 = soft connect/disconnect is supported 0 = soft connect/disconnect is not supported bit 24 utmidwid: utmi+ data width option bit always 0 , indicating 8-bit utmi+ data width bit 23-0 unimplemented: read as 0
? 2015-2016 microchip technology inc. ds60001320d-page 217 pic32mz embedded connectivity with floating point unit (ef) family register 11-8: usbiencsr0: usb indexed endpoint control status register 0 (endpoint 1-7) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 autoset iso mode dmareqen frcdattg dmareqmd d a t a w e n d a t a t g g l 23:16 r/w-0, hs r/w-0, hc r/w-0, hs r/w-0 r/w-0 r/w-0, hs r/w-0 r/w-0, hc incomptx clrdt sentstall sendstall flush underrun fifone txpktrdy naktmout rxstall setuppkt error 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mult<4:0> txmaxp<10:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txmaxp<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 autoset: auto set control bit 1 = txpktrdy will be automatically set when data of the maximum packet size (val ue in txmaxp) is loaded into the tx fifo. if a packet of less than the maximum packet size is loaded, then txpktrdy will hav e to be set manually. 0 = txpktrdy must be set manually for all packet sizes bit 30 iso: isochronous tx endpoint enable bit (device mode) 1 = enables the endpoint for isochronous transfers 0 = disables the endpoint for isochronous transfers and enables it for bulk or interrupt transfers. this bit only has an effect in device mode. in host mode, it always returns zero. bit 29 mode: endpoint direction control bit 1 = endpoint is tx 0 = endpoint is rx this bit only has any effect where the same endpoint fifo is used for both tx and rx transactions. bit 28 dmareqen: endpoint dma request enable bit 1 = dma requests are enabled for this endpoint 0 = dma requests are disabled for this endpoint bit 27 frcdattg: force endpoint data toggle control bit 1 = forces the endpoint data toggle to switch and the data packet to be cleared from the fifo, regardle ss of whether an ack was received. 0 = no forced behavior bit 26 dmareqmd: endpoint dma request mode control bit 1 = dma request mode 1 0 = dma request mode 0 this bit must not be cleared either before or in the same cycle as the above dmareqen bit is cleared. bit 25 datawen: data toggle write enable bit (host mode) 1 = enable the current state of the tx endpoint data toggle (datatggl) to be written 0 = disables writing the datatggl bit bit 24 datatggl: data toggle control bit (host mode) when read, this bit indicates the current state of the tx endpoint data toggle. if datawen = 1, this bit may be written with the required setting of the data toggle. if datawen = 0, any value written to this bit is ig nored.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 218 ? 2015-2016 microchip technology inc. bit 23 incomptx: incomplete tx status bit (device mode) 1 = for high-bandwidth isochronous endpoint, a large packet has been split into 2 or 3 packets for transmission but insufficient in tokens have been received to send all the parts 0 = normal operation in anything other than isochronous transfers, this bit will always return 0. naktmout: nak time-out status bit (host mode) 1 = tx endpoint is halted following the receipt of nak responses for longer than the naklim setting 0 = written by software to clear this bit bit 22 clrdt: clear data toggle control bit 1 = resets the endpoint data toggle to 0 0 = do not clear the data toggle bit 21 sentstall: stall handshake transmission status bit (device mode) 1 = stall handshake is transmitted. the fifo is flushed and the txpktrdy bit is cleared. 0 = written by software to clear this bit rxstall: stall receipt bit (host mode) 1 = stall handshake is received. any dma request in progress is stopped, the fifo is completely flushed and the txpktrdy bit is cleared. 0 = written by software to clear this bit bit 20 sendstall: stall handshake transmission control bit (device mode) 1 = issue a stall handshake to an in token 0 = terminate stall condition this bit has no effect when the endpoint is being used for isochronous transfers. setuppkt: definition bit (host mode) 1 = when set at the same time as the txpktrdy bit is set, send a setup token instead of an out token for the transaction. this also clears the data toggle. 0 = normal out token for the transaction bit 19 flush: fifo flush control bit 1 = flush the latest packet from the endpoint tx fifo. the fifo pointer is reset, txpktrdy is cleared and an interrupt is generated. 0 = do not flush the fifo bit 18 underrun: underrun status bit (device mode) 1 = an in token has been received when txpktrdy is not set. 0 = written by software to clear this bit. error: handshake failure status bit (host mode) 1 = three attempts have been made to send a packet and no handshake packet has been received 0 = written by software to clear this bit. bit 17 fifone: fifo not empty status bit 1 = there is at least 1 packet in the tx fifo 0 = tx fifo is empty bit 16 txpktrdy: tx packet ready control bit the software sets this bit after loading a data packet into the fifo. it is cleared automatically when a data packet has been transmitted. this bit is also automatically cleared prior to loading a second packet into a dou- ble-buffered fifo. register 11-8: usbiencsr0: usb indexed endpoint control status register 0 (endpoint 1-7) (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 219 pic32mz embedded connectivity with floating point unit (ef) family bit 15-11 mult<4:0>: multiplier control bits for isochronous/interrupt endpoints or of packet splitti ng on bulk endpoints, mult iplies txmaxp by mult+1 for the payload size. for bulk endpoints, mult can be up to 32 and defines the number of usb packets of the specified pa yload into which a single data packet placed in the fifo should be split, prior to transfer. the data packet is required to be an exact multiple of the payload specified by txmaxp. for isochronous/interrupts endpoints operating in hi-speed mode, mult may be either 2 or 3 and specifies the maximum number of such transactions that can take place in a single microframe. bit 10-0 txmaxp<10:0>: maximum tx payload per transaction control bits this field sets the maximum payload (in bytes) transmitted in a single transactio n. the value is subject to the constraints placed by the usb specification on packet sizes for bulk, interrupt and isochronous transfers in full-speed and hi-speed operations. txmaxp must be set to an even number of bytes for proper interrupt generation in dma mode 1. register 11-8: usbiencsr0: usb indexed endpoint control status register 0 (endpoint 1-7) (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 220 ? 2015-2016 microchip technology inc. register 11-9: usbiencsr1: usb indexed endpoint control status register 1 (endpoint 1-7) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0, hc r-0 r/w-0 autoclr iso dmareqen disnyet dmareqmd incomprx autorq piderr datatwen datatggl 23:16 r/w-0, hc r/w-0, hs r/w-0 r/w-0, hc r-0, hs r/w-0, hs r-0, hs, hc r/w-0, hs clrdt sentstall sendstall flush dataerr overrun fifofull rxpktrdy rxstall reqpkt derrnakt error 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mult<4:0> rxmaxp<10:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxmaxp<7:0> legend: hc = hardware cleared hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 autoclr: rxpktrdy automatic clear control bit 1 = rxpktrdy will be automatically cleared when a packet of rxmaxp bytes has been unloaded from the rx fifo. when packets of less than the maximum pa cket size are unloaded, rxpktrdy will have to be cleared manually. when using a dma to unload the rx fifo, data is read from the rx fifo in 4-byte chunks regardless of the rxmaxp. 0 = no automatic clearing of rxpktrdy this bit should not be set for high-bandwidth isochronous endpoints. bit 30 iso: isochronous endpoint control bit ( device mode ) 1 = enable the rx endpoint for isochronous transfers 0 = enable the rx endpoint for bulk/interrupt transfers autorq: automatic packet request control bit ( host mode ) 1 = reqpkt will be automatically set when rxpktrdy bit is cleared. 0 = no automatic packet request this bit is automatically cleared when a short packet is received. bit 29 dmareqen: dma request enable control bit 1 = enable dma requests for the rx endpoint. 0 = disable dma requests for the rx endpoint. bit 28 disnyet: disable nyet handshakes control/pid error status bit ( device mode ) 1 = in bulk/interrupt transactions, disables the sending of nyet handshakes. all successfully received rx packets are acked including at the point at which the fifo becomes full. 0 = normal operation. in bulk/interrupt transactions, this bit only has any effect in hi-speed mode, in which mode it should be set for all interrupt endpoints. piderr: pid error status bit ( host mode ) 1 = in iso transactions, this indicates a pid error in the received packet. 0 = no error bit 27 dmareqmd: dma request mode selection bit 1 = dma request mode 1 0 = dma request mode 0
? 2015-2016 microchip technology inc. ds60001320d-page 221 pic32mz embedded connectivity with floating point unit (ef) family bit 26 datatwen: data toggle write enable control bit ( host mode ) 1 = datatggl can be written 0 = datatggl is not writable bit 25 datatggl: data toggle bit ( host mode ) when read, this bit indicates the current state of the endpoint data toggl e. if datatwen = 1 , this bit may be written with the required setting of the data toggle. if datatwen = 0 , any value written to this bit is ignored. bit 24 incomprx: incomplete packet status bit 1 = the packet in the rx fifo during a high-bandwidth isochronous/interrupt transfer is incomplete because parts of the data were not received 0 = written by then software to clear this bit in anything other than isochronous transfer, this bit will always return 0. bit 23 clrdt: clear data toggle control bit 1 = reset the endpoint data toggle to 0 0 = leave endpoint data toggle alone bit 22 sentstall: stall handshake status bit ( device mode ) 1 = stall handshake is transmitted 0 = written by the software to clear this bit rxstall: stall handshake receive status bit ( host mode ) 1 = a stall handshake has been received. an interrupt is generated. 0 = written by the software to clear this bit bit 21 sendstall: stall handshake control bit ( device mode ) 1 = issue a stall handshake 0 = terminate stall condition reqpkt: in transaction request control bit ( host mode ) 1 = request an in transaction. 0 = no request this bit is cleared when rxpktrdy is set. bit 20 flush: flush fifo control bit 1 = flush the next packet to be read from the endpoint rx fifo. the fifo pointer is reset and the rxpktrdy bit is cleared. this should only be used when rxpktrdy is set. if the fifo is double- buffered, flush may need to be set twice to completely clear the fifo. 0 = normal fifo operation this bit is automatically cleared. bit 19 dataerr: data packet error status bit ( device mode ) 1 = the data packet has a crc or bit-stuff error. 0 = no data error this bit is cleared when rxpktrdy is cleared. this bit is only valid when the endpoint is operatin g in iso mode. in bulk mode, it always returns zero. derrnakt: data error/nak time-out status bit ( host mode ) 1 = the data packet has a crc or bit-stuff error. in bulk mode, the rx endpoint is halted fo llowing the receipt of nak responses for longer than the time set as the nak limit. 0 = no data or nak time-out error register 11-9: usbiencsr1: usb indexed endpoint control status register 1 (endpoint 1-7) (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 222 ? 2015-2016 microchip technology inc. bit 18 overrun: data overrun status bit ( device mode ) 1 = an out packet cannot be loaded into the rx fifo. 0 = written by software to clear this bit this bit is only valid when the endpoint is operating in iso mode. in bulk mode, it always returns zero. error: no data packet received status bit ( host mode ) 1 = three attempts have been made to receive a packet and no data packet has been received. an interrupt is generated. 0 = written by the software to clear this bit. this bit is only valid when the rx endpoint is operating in bulk or inte rrupt mode. in iso mode, it always returns zero. bit 17 fifofull: fifo full status bit 1 = no more packets can be loaded into the rx fifo 0 = the rx fifo has at least one free space bit 16 rxpktrdy: data packet reception status bit 1 = a data packet has been received. an interrupt is generated. 0 = written by software to clear this bit when the packet has been unloaded from the rx fifo. bit 15-11 mult<4:0>: multiplier control bits for isochronous/interrupt endpoints or of packet splitting on bulk endpoints, multi plies txmaxp by mult+1 for the payload size. for bulk endpoints, mult can be up to 32 and defines the number of usb packets of the specified payload into which a single data packet placed in the fifo should be split, prior to transfer. the data packet is re quired to be an exact multiple of the payload specified by txmaxp. for isochronous/interrupts endpoints operating in hi-speed mode, mult may be either 2 or 3 and specifies the maximum number of such transactions that can take place in a single microframe. bit 10-0 rxmaxp<10:0>: maximum rx payload per transaction control bits this field sets the maximum payload (in bytes) transmitted in a single transaction. the value is subjec t to the constraints placed by the usb specification on packet sizes for bulk, interrupt and isochronous transfers in full-speed and hi-speed operations. rxmaxp must be set to an even number of bytes for proper interrupt generation in dma mode 1. register 11-9: usbiencsr1: usb indexed endpoint control status register 1 (endpoint 1-7) (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 223 pic32mz embedded connectivity with floating point unit (ef) family register 11-10: usbiencsr2: usb indexed endpoint control status register 2 (endpoint 1-7) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txinterv<7:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 speed<1:0> protocol<1:0> tep<3:0> 15:8 u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 rxcnt<13:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxcnt<7:0> legend: hc = hardware cleared hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 txinterv<7:0>: endpoint tx polling interval/nak limit bits ( host mode ) for interrupt and isochronous transfers, this field defines the polling interval for the endpoint. for bulk endpoints, this field sets the number of frames/microframes after which t he endpoint should time out on receiving a stream of nak responses. the following table describes the valid values and interpretation for these bits: bit 23-22 speed<1:0>: tx endpoint operating speed control bits ( host mode ) 11 = low-speed 10 = full-speed 01 = hi-speed 00 = reserved bit 21-20 protocol<1:0>: tx endpoint protocol control bits 11 = interrupt 10 = bulk 01 = isochronous 00 = control bit 19-16 tep<3:0>: tx target endpoint number bits this value is the endpoint number contained in the tx endpoint descriptor returned to the usb module during device enumeration. bit 15-14 unimplemented: read as 0 bit 13-0 rxcnt<13:0>: receive count bits the number of received data bytes in the endpoint rx fifo. the value returned changes as the contents of the fifo change and is only valid while rxpktrdy is set. transfer type speed valid values (m) interpretation interrupt low/full 0x01 to 0xff polling interval is m frames. high 0x01 to 0x10 polling interval is 2 (m-1) frames. isochronous full or high 0x01 to 0x10 polling interval is 2 (m-1) frames/microframes. bulk full or high 0x02 to 0x10 nak limit is 2 (m-1) frames/microframes. a value of 0 or 1 disables the nak time-out function.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 224 ? 2015-2016 microchip technology inc. register 11-11: usbiencsr3: usb indexed endpoint control status register 3 (endpoint 1-7) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-x r-x r-x r-x r-x r-x r-x r-x rxfifosz<3:0> txfifosz<3:0> 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxinterv<7:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 speed<1:0> protocol<1:0> tep<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-28 rxfifosz<3:0>: receive fifo size bits 1111 = reserved 1110 = reserved 1101 = 8192 bytes 1100 = 4096 bytes 0011 = 8 bytes 0010 = reserved 0001 = reserved 0000 = reserved or endpoint has not been configured this register only has this interpretation when dynamic sizing is not selected. it is not va lid where dynamic fifo sizing is used. bit 27-24 txfifosz<3:0>: transmit fifo size bits 1111 = reserved 1110 = reserved 1101 = 8192 bytes 1100 = 4096 bytes 0011 = 8 bytes 0010 = reserved 0001 = reserved 0000 = reserved or endpoint has not been configured this register only has this interpretation when dynamic sizing is not selected. it is not va lid where dynamic fifo sizing is used. bit 23-16 unimplemented: read as 0
? 2015-2016 microchip technology inc. ds60001320d-page 225 pic32mz embedded connectivity with floating point unit (ef) family bit 15-8 rxinterv<7:0>: endpoint rx polling interval/nak limit bits for interrupt and isochronous transfers, this field defines the polling interval for the endpoint. for bulk e nd- points, this field sets the number of frames/microframes after which the endpoint should time out on receiving a stream of nak responses. the following table describes the valid values and meaning for this field: bit 7-6 speed<1:0>: rx endpoint operating speed control bits 11 = low-speed 10 = full-speed 01 = hi-speed 00 = reserved bit 5-4 protocol<1:0>: rx endpoint protocol control bits 11 = interrupt 10 = bulk 01 = isochronous 00 = control bit 3-0 tep<3:0>: rx target endpoint number bits this value is the endpoint number contained in the tx endpoint descriptor returned to the usb module during device enumeration. register 11-11: usbiencsr3: usb indexed endpoint control status register 3 (endpoint 1-7) (continued) transfer type speed valid values (m) interpretation interrupt low/full 0x01 to 0xff polling interval is m frames. high 0x01 to 0x10 polling interval is 2 (m-1) frames. isochronous full or high 0x01 to 0x10 polling interval is 2 (m-1) frames/microframes. bulk full or high 0x02 to 0x10 nak limit is 2 (m-1) frames/microframes. a value of 0 or 1 disables the nak time-out function.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 226 ? 2015-2016 microchip technology inc. register 11-12: usbfifox: usb fifo data register x (x = 0-7) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 data<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 data<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 data<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 data<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 data<31:0>: usb transmit/receive fifo data bits writes to this register loads data into the txfifo for the corresponding endpoint. reading from this register unloads data from the rxfifo for the corresponding endpoint. transfers may be 8-bit, 16-bit or 32-bit as required, and any combination of access is allowed provided th e data accessed is contiguous. however, all transfers associated with one pac ket must be of the same width so that data is consistently byte-, word- or double-word aligned. the last transfer may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word transfer.
? 2015-2016 microchip technology inc. ds60001320d-page 227 pic32mz embedded connectivity with floating point unit (ef) family register 11-13: usbotg: usb ot g control/status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxdpb rxfifosz<3:0> 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txdpb txfifosz<3:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 txedma rxedma 7:0 r-1 r-0 r-0 r-0 r-0 r-0 r/w-0, hc r/w-0 bdev fsdev lsdev vbus<1:0> hostmode hostreq session legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28 rxdpb: rx endpoint double-packet buffering control bit 1 = double-packet buffer is supported. this doubles the size set in rxfifosz. 0 = double-packet buffer is not supported bit 27-24 rxfifosz<3:0>: rx endpoint fifo packet size bits the maximum packet size to allowed for (before any splitting within the fifo of bulk/high-bandwidth packets prior to transmission) 1111 = reserved 1010 = reserved 1001 = 4096 bytes 1000 = 2048 bytes 0111 = 1024 bytes 0110 = 512 bytes 0101 = 256 bytes 0100 = 128 bytes 0011 = 64 bytes 0010 = 32 bytes 0001 = 16 bytes 0000 = 8 bytes bit 23-21 unimplemented: read as 0 bit 20 txdpb: tx endpoint double-packet buffering control bit 1 = double-packet buffer is supported. this doubles the size set in txfifosz. 0 = double-packet buffer is not supported
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 228 ? 2015-2016 microchip technology inc. bit 19-16 txfifosz<3:0>: tx endpoint fifo packet size bits the maximum packet size to allowed for (before any splitting within the fifo of bulk/high-bandwidth packets prior to transmission) 1111 = reserved 1010 = reserved 1001 = 4096 bytes 1000 = 2048 bytes 0111 = 1024 bytes 0110 = 512 bytes 0101 = 256 bytes 0100 = 128 bytes 0011 = 64 bytes 0010 = 32 bytes 0001 = 16 bytes 0000 = 8 bytes bit 15-10 unimplemented: read as 0 bit 9 txedma: tx endpoint dma assertion control bit 1 = dma_req signal for all in endpoints will be deasserted when maxp-8 bytes have been written to an endpoint. this is early mode. 0 = dma_req signal for all in endpoints will be deasserted when maxp bytes have been written to an endpoint. this is late mode. bit 8 rxedma: rx endpoint dma assertion control bit 1 = dma_req signal for all out endpoints will be deasserted when maxp-8 bytes have been written to an endpoint. this is early mode. 0 = dma_req signal for all out endpoints will be deasserted when maxp bytes have been written to an endpoint. this is late mode. bit 7 bdev: usb device type bit 1 = usb is operating as a b device 0 = usb is operating as an a device bit 6 fsdev: full-speed/hi-speed device detection bit ( host mode ) 1 = a full-speed or hi-speed device has been detected being connected to the port 0 = no full-speed or hi-speed device detected bit 5 lsdev: low-speed device detection bit ( host mode ) 1 = a low-speed device has been detected being connected to the port 0 = no low-speed device detected bit 4-3 vbus<1:0>: v bus level detection bits 11 = above v bus valid 10 = above avalid, below v bus valid 01 = above session end, below avalid 00 = below session end bit 2 hostmode: host mode bit 1 = usb module is acting as a host 0 = usb module is not acting as a host bit 1 hostreq: host request control bit b device only: 1 = usb module initiates the host negotiation when suspend mode is entered. this bit is cleared when host negotiation is completed. 0 = host negotiation is not taking place register 11-13: usbotg: usb otg cont rol/status register (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 229 pic32mz embedded connectivity with floating point unit (ef) family bit 0 session: active session control/status bit a device: 1 = start a session 0 = end a session b device: 1 = (read) session has started or is in progress, (write) initiate the session request protocol 0 = when usb module is in suspend mode, clearing this bit will cause a software disconnect clearing this bit when the usb module is not suspended will result in undefined behavior. register 11-13: usbotg: usb otg cont rol/status register (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 230 ? 2015-2016 microchip technology inc. register 11-14: usbfifoa: usb fifo address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxfifoad<12:8> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxfifoad<7:0> 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txfifoad<12:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txfifoad<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28-16 rxfifoad<12:0>: receive endpoint fifo address bits start address of the endpoint fifo in units of 8 bytes as follows: 1111111111111 = 0xfff8 0000000000010 = 0x0010 0000000000001 = 0x0008 0000000000000 = 0x0000 bit 15-13 unimplemented: read as 0 bit 12-0 txfifoad<12:0>: transmit endpoint fifo address bits start address of the endpoint fifo in units of 8 bytes as follows: 1111111111111 = 0xfff8 0000000000010 = 0x0010 0000000000001 = 0x0008 0000000000000 = 0x0000
? 2015-2016 microchip technology inc. ds60001320d-page 231 pic32mz embedded connectivity with floating point unit (ef) family register 11-15: usbhwver: usb hardware version register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r-0 r-0 r-0 r-0 r-1 r-0 r-0 r-0 rc vermajor<4:0> verminor<9:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 verminor<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 rc: release candidate bit 1 = usb module was created using a release candidate 0 = usb module was created using a full release bit 14-10 vermajor<4:0>: usb module major version number bits this read-only number is the major version number for the usb module. bit 9-0 verminor<9:0>: usb module minor version number bits this read-only number is the minor version number for the usb module.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 232 ? 2015-2016 microchip technology inc. register 11-16: usbinfo: usb information register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 vplen<7:0> 23:16 r/w-0 r/w-1 r/w-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 wtcon<3:0> wtid<3:0> 15:8 r-1 r-0 r-0 r-0 r-1 r-1 r-0 r-0 dmachans<3:0> rambits<3:0> 7:0 r-0 r-1 r-1 r-1 r-0 r-1 r-1 r-1 rxendpts<3:0> txendpts<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 vplen<7:0>: v bus pulsing charge length bits sets the duration of the v bus pulsing charge in units of 546.1 s. (the default setting corresponds to 32. 77 ms.) bit 23-20 wtcon<3:0>: connect/disconnect filter control bits sets the wait to be applied to allow for the connect/disconnect filter in units of 533.3 ns. the default setting corresponds to 2.667 s. bit 19-6 wtid<3:0>: id delay valid control bits sets the delay to be applied from idpullup being asserted to iddig being considered valid in units of 4.369ms. the default setting corresponds to 52.43ms. bit 15-12 dmachans<3:0>: dma channels bits these read-only bits provide the number of dma channels in the usb module. for the pic32mz ef family, this number is 8. bit 11-8 rambits<3:0>: ram address bus width bits these read-only bits provide the width of the ram address bus. for the pic32mz ef family, this number is 12. bit 7-4 rxendpts<3:0>: included rx endpoints bits this read-only register gives the number of rx endpoints in the design. for the pic32mz ef family, th is number is 7. bit 3-0 txendpts<3:0>: included tx endpoints bits these read-only bits provide the number of tx endpoints in the design. for the pic32mz ef famil y, this number is 7.
? 2015-2016 microchip technology inc. ds60001320d-page 233 pic32mz embedded connectivity with floating point unit (ef) family register 11-17: usbeofrst: usb end-of -frame/soft reset control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 nrstx nrst 23:16 r/w-0 r/w-1 r/w-1 r/w-1 r/w-0 r.w-0 r/w-1 r/w-0 lseof<7:0> 15:8 r/w-0 r/w-1 r/w-1 r/w-1 r/w-0 r.w-1 r/w-1 r/w-1 fseof<7:0> 7:0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r.w-0 r/w-0 r/w-0 hseof<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-26 unimplemented: read as 0 bit 25 nrstx: reset of xclk domain bit 1 = reset the xclk domain, which is clock recovered from the received data by the phy 0 = normal operation bit 24 nrst: reset of clk domain bit 1 = reset the clk domain, which is clock recovered from the peripheral bus 0 = normal operation bit 23-16 lseof<7:0>: low-speed eof bits these bits set the low-speed transaction in units of 1.067 s (default setting is 121.6 s) prior to the eo f to stop new transactions from beginning. bit 15-8 fseof<7:0>: full-speed eof bits these bits set the full-speed transaction in units of 533.3 s (default setting is 63.46 s) prior to the eof to stop new transactions from beginning. bit 7-0 hseof<7:0>: hi-speed eof bits these bits set the hi-speed transaction in units of 133.3 s (default setting is 17.07s) prior to the eof to stop new transactions from beginning.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 234 ? 2015-2016 microchip technology inc. register 11-18: usbextxa: usb endpoint x transmit address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txhubprt<6:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 multtran txhubadd<6:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txfaddr<6:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 unimplemented: read as 0 bit 30-24 txhubprt<6:0>: tx hub port bits ( host mode ) when a low-speed or full-speed device is connected to this endpoint through a hi-speed usb 2.0 hub, this field records the port number of that usb 2.0 hub. bit 23 multtran: tx hub multiple translators bit ( host mode ) 1 = the usb 2.0 hub has multiple transaction translators 0 = the usb 2.0 hub has a single transaction translator bit 22-16 txhubadd<6:0>: tx hub address bits ( host mode ) when a low-speed or full-speed device is connected to this endpoint through a hi-speed usb 2.0 hub, these bits record the address of the usb 2.0 hub. bit 15-7 unimplemented: read as 0 bit 6-0 txfaddr<6:0>: tx functional address bits ( host mode ) specifies the address for the target function that is be accessed through the associated endpoint. it needs to be defined for each tx endpoint that is used.
? 2015-2016 microchip technology inc. ds60001320d-page 235 pic32mz embedded connectivity with floating point unit (ef) family register 11-19: usbexrxa: usb endpoint x receive address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxhubprt<6:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 multtran rxhubadd<6:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxfaddr<6:0> legend: hc = hardware cleared hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 unimplemented: read as 0 bit 30-24 rxhubprt<6:0>: rx hub port bits ( host mode ) when a low-speed or full-speed device is connected to this endpoint via a hi-speed u sb 2.0 hub, this field records the port number of that usb 2.0 hub. bit 23 multtran: rx hub multiple translators bit ( host mode ) 1 = the usb 2.0 hub has multiple transaction translators 0 = the usb 2.0 hub has a single transaction translator bit 22-16 txhubadd<6:0>: rx hub address bits ( host mode ) when a low-speed or full-speed device is connected to this endpoint via a hi-speed usb 2.0 hub, these bits record the address of the usb 2.0 hub. bit 15-7 unimplemented: read as 0 bit 6-0 rxfaddr<6:0>: rx functional address bits ( host mode ) specifies the address for the target function that is be accessed through the associated endpoint. it needs to be defined for each rx endpoint that is used.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 236 ? 2015-2016 microchip technology inc. register 11-20: usbdmaint: usb dma interrupt register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs dma8if dma7if dma6if dma5if dma4if dma3if dma2if dma1if legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as 0 bit 7-0 dmaxif: dma channel x interrupt bit 1 = the dma channel has an interrupt event 0 = no interrupt event all bits are cleared on a read of the register.
? 2015-2016 microchip technology inc. ds60001320d-page 237 pic32mz embedded connectivity with floating point unit (ef) family register 11-21: usbdmaxc: usb dma channel x control register (x = 1-8) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 dmabrstm<1:0> dmaerr 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dmaep<3:0> dmaie dmamode dmadir dmaen legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-11 unimplemented: read as 0 bit 10-9 dmabrstm<1:0>: dma burst mode selection bit 11 = burst mode 3: incr16, incr8, incr4 or unspecified length 10 = burst mode 2: incr8, incr4 or unspecified length 01 = burst mode 1: incr4 or unspecified length 00 = burst mode 0: bursts of unspecified length bit 8 dmaerr: bus error bit 1 = a bus error has been observed on the input 0 = the software writes this to clear the error bit 7-4 dmaep<3:0>: dma endpoint assignment bits these bits hold the endpoint that the dma channel is assigned to. valid values are 0-7. bit 3 dmaie: dma interrupt enable bit 1 = interrupt is enabled for this channel 0 = interrupt is disabled for this channel bit 2 dmamode: dma transfer mode bit 1 = dma mode1 transfers 0 = dma mode0 transfers bit 1 dmadir: dma transfer direction bit 1 = dma read (tx endpoint) 0 = dma write (rx endpoint) bit 0 dmaen: dma enable bit 1 = enable the dma transfer and start the transfer 0 = disable the dma transfer
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 238 ? 2015-2016 microchip technology inc. register 11-22: usbdmaxa: usb dma channel x memory address register (x = 1-8) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dmaaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dmaaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dmaaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 dmaaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 dmaaddr<31:0>: dma memory address bits this register identifies the current memory address of the corresponding dma channel. the initial memory address written to this register during initialization must have a value such that its modulo 4 value is equal to 0 . the lower two bits of this register are read only and cannot be set by software. as the dma transfer progresses, the memory address will increment as bytes are transferred. register 11-23: usbdmaxn: usb dma channel x count register (x = 1-8) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dmacount<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dmacount<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dmacount<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dmacount<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 dmacount<31:0>: dma transfer count bits this register identifies the current dma count of the transfer. software will set the initial count of the transfer which identifies the entire transfer length. as the count progresses this count is decremented as bytes are transferred.
? 2015-2016 microchip technology inc. ds60001320d-page 239 pic32mz embedded connectivity with floating point unit (ef) family register 11-24: usbexrpc: usb endpoint x request packet count register (host mode only) (x = 1-7) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rqpktcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rqpktcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 rqpktcnt<15:0>: request packet count bits sets the number of packets of size maxp that are to be transferred in a block transfer. this regi ster is only available in host mode when autoreq is set. register 11-25: usbdpbfd: usb double packet buffer disable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 ep7txd ep6txd ep5txd ep4txd ep3txd ep2txd ep1txd 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 ep7rxd ep6rxd ep5rxd ep4rxd ep3rxd ep2rxd ep1rxd legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-17 ep7txd:ep1txd: tx endpoint x double packet buffer disable bits 1 = tx double packet buffering is disabled for endpoint x 0 = tx double packet buffering is enabled for endpoint x bit 16 unimplemented: read as 0 bit 15-1 ep7rxd:ep1rxd: rx endpoint x double packet buffer disable bits 1 = rx double packet buffering is disabled for endpoint x 0 = rx double packet buffering is enabled for endpoint x bit 0 unimplemented: read as 0
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 240 ? 2015-2016 microchip technology inc. register 11-26: usbtmcon1: usb timing control register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 thhsrtn<15:8> 23:16 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 thhsrtn<7:0> 15:8 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tuch<15:8> 7:0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-1 r/w-0 r/w-0 tuch<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 thhsrtn:<15:0>: hi-speed resume signaling delay bits these bits set the delay from the end of hi-speed resume signaling (acting as a host) to enable the utm normal operating mode. bit 15-0 tuch<15:0>: chirp time-out bits these bits set the chirp time-out. this number, when multiplied by 4, represents the number of usb module clock cycles before the time-out occurs. note: use of this register will allow the hi-speed time-out to be set to values that are greater than the maximu m specified in the usb 2.0 specification, making the usb module non-compliant. register 11-27: usbtmcon2: us b timing control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 thbst<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as 0 bit 3-0 thbst<3:0>: high speed time-out adder bits these bits represent the value to be added to the minimum high speed time-out period of 736 bit times. the time-out period can be increased in increments of 64 hi-speed bit times (133 ns). note: use of this register will allow the hi-speed time-out to be set to values that are greater than the maximum specified in the usb 2.0 specification, making the usb module non-compliant.
? 2015-2016 microchip technology inc. ds60001320d-page 241 pic32mz embedded connectivity with floating point unit (ef) family register 11-28: usblpmr1: usb link power management control ? register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lpmerrie lpmresie lpmackie lpmnyie lpmstie lpmtoie 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0, hc r/w-0, hc lpmnak lpmen<1:0> lpmres lpmxmt 15:8 r-0 r-0 r-0 r-0 u-0 u-0 u-0 r-0 endpoint<3:0> r m t w a k 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 hird<3:0> lnkstate<3:0> legend: hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-30 unimplemented: read as 0 bit 29 lpmerrie: lpm error interrupt enable bit 1 = lpmerr interrupt is enabled 0 = lpmerr interrupt is disabled bit 28 lpmresie: lpm resume interrupt enable bit 1 = lpmres interrupt is enabled 0 = lpmres interrupt is disabled bit 27 lpmackie: lpm acknowledge interrupt enable bit 1 = enable the lpmack interrupt 0 = disable the lpmack interrupt bit 26 lpmnyie: lpm nyet interrupt enable bit 1 = enable the lpmnyet interrupt 0 = disable the lpmnyet interrupt bit 25 lpmstie: lpm stall interrupt enable bit 1 = enable the lpmst interrupt 0 = disable the lpmst interrupt bit 24 lpmtoie: lpm time-out interrupt enable bit 1 = enable the lpmto interrupt 0 = disable the lpmto interrupt bit 23-21 unimplemented: read as 0 bit 20 lpmnak: lpm-only transaction setting bit 1 = all endpoints will respond to all transactions other than a lpm transaction with a nak 0 = normal transaction operation setting this bit to 1 will only take effect after the usb module as been lpm suspended. bit 19-18 lpmen<1:0>: lpm enable bits ( device mode ) 11 = lpm extended transactions are supported 10 = lpm and extended transactions are not supported 01 = lpm mode is not supported but extended transactions are supported 00 = lpm extended transactions are supported bit 17 lpmres: lpm resume bit 1 = initiate resume (remote wake-up). resume signaling is asserted for 50 s. 0 = no resume operation this bit is self-clearing.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 242 ? 2015-2016 microchip technology inc. bit 16 lpmxmt: lpm transition to the l1 state bit when in device mode : 1 = usb module will transition to the l1 state upon the receipt of the next lpm transaction. lpmen must be set to 0b11 . both lpmxmt and lpmen must be set in the same cycle. 0 = maintain current state when lpmxmt and lpmen are set, the usb module can respond in the following ways: if no data is pending (all tx fifos are empty), the usb module will respond with an ack. the bit will self clear and a software interrupt will be generated. if data is pending (data resides in at least one tx fifo), the usb module will respond with a nyet. in this case, the bit will not self clear however a software interrupt will be generated. when in host mode : 1 = usb module will transmit an lpm transaction. this bit is self clearing, and w ill be immediately cleared upon receipt of any token or three time-outs have occurred. 0 = maintain current state bit 15-12 endpoint<3:0>: lpm token packet endpoint bits this is the endpoint in the token packet of the lpm transaction. bit 11-9 unimplemented: read as 0 bit 8 rmtwak: remote wake-up enable bit this bit is applied on a temporary basis only and is only applied to the current suspend state. 1 = remote wake-up is enabled 0 = remote wake-up is disabled bit 7-4 hird<3:0>: host initiated resume duration bits the minimum time the host will drive resume on the bus. the value in this register corresponds to an actual resume time of: resume time = 50 s + hird * 75 s. the resulting range is 50 s to 1200 s. bit 3-0 lnkstate<3:0>: link state bits this value is provided by the host to the peripheral to indicate what state the peripheral must transiti on to after the receipt and acceptance of a lpm transaction. the only valid value for this register is 1 for sleep state (l1). all other values are reserved. register 11-28: usblpmr1: usb link power management control ? register 1 (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 243 pic32mz embedded connectivity with floating point unit (ef) family register 11-29: usblpmr2: usb link po wer management cont rol register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lpmfaddr<6:0> 7:0 u-0 u-0 r-0 r-0, hs r-0, hs r-0, hs r-0, hs r-0, hs lpmerrif lpmresif lpmncif lpmackif lpmnyif lpmstif legend: hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as 0 bit 14-8 lpmfaddr<6:0>: lpm payload function address bits these bits contain the address of the lpm payload function. bit 7-6 unimplemented: read as 0 bit 5 lpmerrif: lpm error interrupt flag bit ( device mode ) 1 = an lpm transaction was received that had a linkstate field that is not supported. the response will be a stall. 0 = no error condition bit 4 lpmresif: lpm resume interrupt flag bit 1 = the usb module has resumed (for any reason) 0 = no resume condition bit 3 lpmncif: lpm nc interrupt flag bit when in device mode : 1 = the usb module received a lpm transaction and responded with a nyet due to data pending in the rx fifos. 0 = no nc interrupt condition when in host mode : 1 = a lpm transaction is transmitted and the device responded with an ack 0 = no nc interrupt condition bit 2 lpmackif: lpm ack interrupt flag bit when in device mode : 1 = a lpm transaction was received and the usb module responded with an ack 0 = no ack interrupt condition when in host mode : 1 = the lpm transaction is transmitted and the device responds with an ack 0 = no ack interrupt condition bit 1 lpmnyif: lpm nyet interrupt flag bit when in device mode : 1 = a lpm transaction is received and the usb module responded with a nyet 0 = no nyet interrupt flag when in host mode : 1 = a lpm transaction is transmitted and the device responded with an nyet 0 = no nyet interrupt flag
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 244 ? 2015-2016 microchip technology inc. bit 0 lpmstif: lpm stall interrupt flag bit when in device mode : 1 = a lpm transaction was received and the usb module responded with a stall 0 = no stall condition when in host mode : 1 = a lpm transaction was transmitted and the device responded with a stall 0 = no stall condition register 11-29: usblpmr2: usb link po wer management cont rol register 2 (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 245 pic32mz embedded connectivity with floating point unit (ef) family register 11-30: usbcrcon: usb clock/reset control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 r-0, hs, hc r-0, hs, hc r/w-1, hs usbif usbrf usbwkup 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r-1 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 usb idoven usb idval 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phyiden vbus monen asval monen bsval monen send monen usbie usbrie usb wkupen legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-27 unimplemented: read as 0 bit 26 usbif: usb general interrupt flag bit 1 = an event on the usb bus has occurred 0 = no interrupt from usb module or interrupts have not been enabled bit 25 usbrf: usb resume flag bit 1 = resume from suspend state. device wake-up activity can be started. 0 = no resume activity detected during suspend, or not in suspend state bit 24 usbwk: usb activity status bit 1 = connect, disconnect, or other activity on usb detected since last clear ed 0 = no activity detected on usb note: this bit should be cleared just prior to entering sleep, but it should be checked that no activity has already occurred on usb before actually entering sleep. bit 23-14 unimplemented: read as 0 bit 15 reserved: read as 1 bit 14-10 unimplemented: read as 0 bit 9 usbidoven: usb id override enable bit 1 = enable use of usbidval bit 0 = disable use of usbidval and instead use the phy value bit 8 usbidval: usb id value bit 1 = id override value is 1 0 = id override value is 0 bit 7 phyiden: phy id monitoring enable bit 1 = enable monitoring of the id bit from the usb phy 0 = disable monitoring of the id bit from the usb phy bit 6 vbusmonen: v bus monitoring for otg enable bit 1 = enable monitoring for v bus in vbus valid range (between 4.4v and 4.75v) 0 = disable monitoring for v bus in vbus valid range bit 5 asvalmonen: a-device v bus monitoring for otg enable bit 1 = enable monitoring for v bus in session valid range for a-device (between 0.8v and 2.0v) 0 = disable monitoring for v bus in session valid range for a-device bit 4 bsvalmonen: b-device v bus monitoring for otg enable bit 1 = enable monitoring for v bus in session valid range for b-device (between 0.8v and 4.0v) 0 = disable monitoring for v bus in session valid range for b-device
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 246 ? 2015-2016 microchip technology inc. bit 3 sendmonen: session end v bus monitoring for otg enable bit 1 = enable monitoring for v bus in session end range (between 0.2v and 0.8v) 0 = disable monitoring for v bus in session end range bit 2 usbie: usb general interrupt enable bit 1 = enables general interrupt from usb module 0 = disables general interrupt from usb module bit 1 usbrie: usb resume interrupt enable bit 1 = enable remote resume from suspend interrupt 0 = disable interrupt to a remote devices usb resume signaling bit 0 usbwkupen: usb activity detection interrupt enable bit 1 = enable interrupt for detection of activity on usb bus in sleep mode 0 = disable interrupt for detection of activity on usb bus in sleep mode register 11-30: usbcrcon: usb clock/ reset control register (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 247 pic32mz embedded connectivity with floating point unit (ef) family 12.0 i/o ports general purpose i/o pins are the simplest of peripherals. they allow the pic32mz ef family device to monitor and control other devices. to add flexibility and functionality, some pins are multiplexed with alternate function(s). these functions depend on which peripheral features are on the device. in general, when a peripheral is functioning, that pin may not be used as a general purpose i/o pin. some of the key features of the i/o ports are: individual output pin open-drain enable/disable individual input pin weak pull-up and pull-down monitor selective inputs and generate interrupt when change in pin state is detected operation during sleep and idle modes fast bit manipulation using clr, set and inv registers figure 12-1 illustrates a block diagram of a typical multiplexed i/o port. figure 12-1: block diagram of a typical multiplexed port structure note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive refer - ence source. to complement the informa - tion in this data sheet, refer to section 12. i/o ports (ds60001120) in the ?pic32 family reference manual? , which is avail - able from the microchip web site ( www.microchip.com/pic32 ). peripheral output data peripheral module peripheral output enable pio module peripheral module enable wr lat i/o pin wr port data bus rd lat rd port rd tris wr tris 01 rd odc pbclk4 q d ck en q q d ck en q q d ck en q q d ck q qd ck q 0 1 pbclk4 wr odc odc tris lat sleep 10 10 output multiplexers i/o cell synchronization r peripheral input legend: r = peripheral input buffer types may vary. refer to table 1-1 for peripheral details. note: this block diagram is a general representation of a shared port/ peripheral structure for illustration purposes only. the actual structure for any specific port/peripheral combination may be different than i t is shown here. peripheral input buffer port control pbclk4
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 248 ? 2015-2016 microchip technology inc. 12.1 parallel i/o (pio) ports all port pins have up to 14 registers directly associated with their operation as digital i/o. the data direction register (trisx) determines whether the pin is an input or an output. if the data direction bit is a 1 , then the pin is an input. all port pins are defined as inputs after a reset. reads from the latch (latx) read the latch. writes to the latch write the latch. reads from the port (portx) read the port pins, while writes to the port pins write the latch. 12.1.1 open-drain configuration in addition to the portx, latx, and trisx registers for data control, some port pins can also be individually configured for either digital or open-drain output. this is controlled by the open-drain control register, odcx, associated with each port. setting any of the bits con - figures the corresponding pin to act as an open-drain output. the open-drain feature allows the generation of out - puts higher than v dd (e.g., 5v) on any desired 5v-tol - erant pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification. refer to the pin name tables ( ta b l e 2 through ta bl e 5 ) for the available pins and their functionality. 12.1.2 configuring analog and digital port pins the anselx register controls the operation of the analog port pins. the port pins that are to function as analog inputs must have their corresponding ansel and tris bits set. in order to use port pins for i/o functionality with digital modules, such as timers, uarts, etc., the corresponding anselx bit must be cleared. the anselx register has a default value of 0xffff; therefore, all pins that share analog functions are analog (not digital) by default. if the tris bit is cleared (output) while the anselx bit is set, the digital output level (v oh or v ol ) is converted by an analog peripheral, such as the adc module or comparator module. when the port register is read, all pins configured as analog input channels are read as cleared (a low level). pins configured as digital inputs do not convert an analog input. analog levels on any pin defined as a digital input (including the anx pins) can cause the input buffer to consume current that exceeds the device specifications. 12.1.3 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically this instruction would be an nop . 12.1.4 input change notification the input change notification function of the i/o ports allows the pic32mz ef devices to generate interrupt requests to the processor in response to a change-of- state on selected input pins. this feature can detect input change-of-states even in sleep mode, when the clocks are disabled. every i/o port pin can be selected (enabled) for generating an interrupt request on a change-of-state. seven control registers are associated with the cn functionality of each i/o port. the cnenx/cnnex registers contain the cn interrupt enable control bits for each of the input pins. setting any of these bits enables a cn interrupt for the corresponding pins. cnenx enables a mismatch cn interrupt condition when the edgedetect bit (cnconx<11>) is not set. when the edgedetect bit is set, cnnex controls the negative edge while cnenx controls the positive. the cnstatx/cnfx registers indicate the status of change notice based on the setting of the edgedetect bit. if the edgedetect bit is set to 0, the cnstatx register indicates whether a change occurred on the corresponding pin since the last read of the portx bit. if the edgedetect bit is set to 1 , the cnfx register indicates whether a change has occurred and through the cnnex/cnenx registers the edge type of the change that occurred is also indicated. each i/o pin also has a weak pull-up and a weak pull-down connected to it. the pull-ups act as a current source or sink source connected to the pin, and eliminate the need for external resistors when push-button or keypad devices are connected. the pull-ups and pull-downs are enabled separately using the cnpux and the cnpdx registers, which contain the control bits for each of the pins. setting any of the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins. an additional control register (cnconx) is shown in register 12-3 . note: pull-ups and pull-downs on change notification pins should always be disabled when the port pin is configured as a digital output.
? 2015-2016 microchip technology inc. ds60001320d-page 249 pic32mz embedded connectivity with floating point unit (ef) family 12.2 registers for slew rate control some i/o pins can be configured for various types of slew rate control on its associated port. this is controlled by the slew rate control bits in the srcon1x and srcon0x registers that are associated with each i/o port. the slew rate control is configured using the corresponding bit in each register, as shown in table 12-1 . as an example, writing 0x0001, 0x0000 to srcon1a and srcon0a, respectively, will enable slew rate control on the ra0 pin and sets the slew rate to the slow edge rate. table 12-1: slew rate control bit settings 12.3 clr, set, and inv registers every i/o module register has a corresponding clr (clear), set (set) and inv (invert) register designed to provide fast atomic bit manipulations. as the name of the register implies, a value written to a set, clr or inv register effectively performs the implied operation, but only on the corresponding base register and only bits specified as 1 are modified. bits specified as 0 are not modified. reading set, clr and inv registers returns undefined values. to see the affects of a write operation to a set, clr or inv register, the base register must be read. 12.4 peripheral pin select (pps) a major challenge in general purpose devices is provid - ing the largest possible set of peripheral features while minimizing the conflict of features on i/o pins. the chal - lenge is even greater on low pin-count devices. in an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only option. pps configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of i/o pins. by increasing the pinout options available on a particular device, users can better tailor the device to their entire application, rather than trimming the application to fit the device. the pps configuration feature operates over a fixed subset of digital i/o pins. users may independently map the input and/or output of most digital peripherals to these i/o pins. pps is performed in software and generally does not require the device to be repro - grammed. hardware safeguards are included that pre - vent accidental or spurious changes to the peripheral mapping once it has been established. 12.4.1 available pins the number of available pins is dependent on the particular device and its pin count. pins that support the pps feature include the designation rpn in their full pin designation, where rp designates a remappable peripheral and n is the remappable port number. 12.4.2 available peripherals the peripherals managed by the pps are all digital- only peripherals. these include general serial communications (uart, spi, and can), general pur - pose timer clock inputs, timer-related peripherals (input capture and output compare), interrupt-on-change inputs, and reference clocks (input and output). in comparison, some digital-only peripheral modules are never included in the pps feature. this is because the peripherals function requires special i/o circuitry on a specific port and cannot be easily connected to multiple pins. these modules include i 2 c among oth - ers. a similar requirement excludes all modules with analog inputs, such as the analog-to-digital converter (adc). a key difference between remappable and non-remap - pable peripherals is that remappable peripherals are not associated with a default i/o pin. the peripheral must always be assigned to a specific i/o pin before it can be used. in contrast, non-remappable peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. when a remappable peripheral is active on a given i/o pin, it takes priority over all other digital i/o and digital communication peripherals associated with the pin. priority is given regardless of the type of peripheral that is mapped. remappable peripherals never take priority over any analog functions associated with the pin. srcon1x srcon0x description 1 1 slew rate control is enabled and is set to the slowest edge rate. 1 0 slew rate control is enabled and is set to the slow edge rate. 0 1 slew rate control is enabled and is set to the medium edge rate. 0 0 slew rate control is disabled and is set to the fastest edge rate. note: by default, all of the port pins are set to the fastest edge rate.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 250 ? 2015-2016 microchip technology inc. 12.4.3 controlling pps pps features are controlled through two sets of sfrs: one to map peripheral inputs, and one to map outputs. because they are separately controlled, a particular peripherals input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. the association of a peripheral to a peripheral-select - able pin is handled in two different ways, depending on whether an input or output is being mapped. 12.4.4 input mapping the inputs of the pps options are mapped on the basis of the peripheral. that is, a control register associated with a peripheral dictates the pin it will be mapped to. the [ pin name ] r registers, where [ pin name ] refers to the peripheral pins listed in ta b l e 12-2 , are used to config - ure peripheral input mapping (see register 12-1 ). each register contains sets of 4 bit fields. programming these bit fields with an appropriate value maps the rpn pin with the corresponding value to that peripheral. for any given device, the valid range of values for any bit field is shown in table 12-2 . for example, figure 12-2 illustrates the remappable pin selection for the u1rx input. figure 12-2: remappable input example for u1rx rpd2 rpg8 rpf4 0 12 u1rx input u1rxr<3:0> to peripheral rpn n note: for input only, pps functionality does not have priority over trisx settings. therefore, when configuring rpn pin for input, the corresponding bit in the trisx register must also be configured for input (set to 1 ).
? 2015-2016 microchip technology inc. ds60001320d-page 251 pic32mz embedded connectivity with floating point unit (ef) family table 12-2: input pin selection peripheral pin [ pin name ]r sfr [ pin name ]r bits [ pin name ]r value to rpn pin selection int3 int3r int3r<3:0> 0000 = rpd2 ? 0001 = rpg8 ? 0010 = rpf4 ? 0011 = rpd10 ? 0100 = rpf1 ? 0101 = rpb9 ? 0110 = rpb10 ? 0111 = rpc14 ? 1000 = rpb5 ? 1001 = reserved ? 1010 = rpc1 (1) ? 1011 = rpd14 (1) ? 1100 = rpg1 (1) ? 1101 = rpa14 (1) ? 1110 = rpd6 (2) ? 1111 = reserved t2ck t2ckr t2ckr<3:0> t6ck t6ckr t6ckr<3:0> ic3 ic3r ic3r<3:0> ic7 ic7r ic7r<3:0> u1rx u1rxr u1rxr<3:0> u2cts u2ctsr u2ctsr<3:0> u5rx u5rxr u5rxr<3:0> u6cts u6ctsr u6ctsr<3:0> sdi1 sdi1r sdi1r<3:0> sdi3 sdi3r sdi3r<3:0> sdi5 (1) sdi5r (1) sdi5r<3:0> (1) ss6 (1) ss6r (1) ss6r<3:0> (1) refclki1 refclki1r refclki1r<3:0> int4 int4r int4r<3:0> 0000 = rpd3 ? 0001 = rpg7 ? 0010 = rpf5 ? 0011 = rpd11 ? 0100 = rpf0 ? 0101 = rpb1 ? 0110 = rpe5 ? 0111 = rpc13 ? 1000 = rpb3 ? 1001 = reserved ? 1010 = rpc4 (1) ? 1011 = rpd15 (1) ? 1100 = rpg0 (1) ? 1101 = rpa15 (1) ? 1110 = rpd7 (2) ? 1111 = reserved t5ck t5ckr t5ckr<3:0> t7ck t7ckr t7ckr<3:0> ic4 ic4r ic4r<3:0> ic8 ic8r ic8r<3:0> u3rx u3rxr u3rxr<3:0> u4cts u4ctsr u4ctsr<3:0> sdi2 sdi2r sdi2r<3:0> sdi4 sdi4r sdi4r<3:0> c1rx (3) c1rxr (3) c1rxr<3:0> (3) refclki4 refclki4r refclki4r<3:0> int2 int2r int2r<3:0> 0000 = rpd9 ? 0001 = rpg6 ? 0010 = rpb8 ? 0011 = rpb15 ? 0100 = rpd4 ? 0101 = rpb0 ? 0110 = rpe3 ? 0111 = rpb7 ? 1000 = reserved ? 1001 = rpf12 (1) ? 1010 = rpd12 (1) ? 1011 = rpf8 (1) ? 1100 = rpc3 (1) ? 1101 = rpe9 (1) ? 1110 = reserved ? 1111 = reserved t3ck t3ckr t3ckr<3:0> t8ck t8ckr t8ckr<3:0> ic2 ic2r ic2r<3:0> ic5 ic5r ic5r<3:0> ic9 ic9r ic9r<3:0> u1cts u1ctsr u1ctsr<3:0> u2rx u2rxr u2rxr<3:0> u5cts u5ctsr u5ctsr<3:0> ss1 ss1r ss1r<3:0> ss3 ss3r ss3r<3:0> ss4 ss4r ss4r<3:0> ss5 (1) ss5r (1) ss5r<3:0> (1) c2rx (3) c2rxr (3) c2rxr<3:0> (3) note 1: this selection is not available on 64-pin devices. 2: this selection is not available on 64-pin or 100-pin devices. 3: this selection is not available on devices without a can module.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 252 ? 2015-2016 microchip technology inc. int1 int1r int1r<3:0> 0000 = rpd1 ? 0001 = rpg9 ? 0010 = rpb14 ? 0011 = rpd0 ? 0100 = reserved ? 0101 = rpb6 ? 0110 = rpd5 ? 0111 = rpb2 ? 1000 = rpf3 ? 1001 = rpf13 (1) ? 1010 = no connect ? 1011 = rpf2 (1) ? 1100 = rpc2 (1) ? 1101 = rpe8 (1) ? 1110 = reserved ? 1111 = reserved t4ck t4ckr t4ckr<3:0> t9ck t9ckr t9ckr<3:0> ic1 ic1r ic1r<3:0> ic6 ic6r ic6r<3:0> u3cts u3ctsr u3ctsr<3:0> u4rx u4rxr u4rxr<3:0> u6rx u6rxr u6rxr<3:0> ss2 ss2r ss2r<3:0> sdi6 (1) sdi6r (1) sdi6r<3:0> (1) ocfa ocfar ocfar<3:0> refclki3 refclki3r refclki3r<3:0> table 12-2: input pin selection (continued) peripheral pin [ pin name ]r sfr [ pin name ]r bits [ pin name ]r value to rpn pin selection note 1: this selection is not available on 64-pin devices. 2: this selection is not available on 64-pin or 100-pin devices. 3: this selection is not available on devices without a can module.
? 2015-2016 microchip technology inc. ds60001320d-page 253 pic32mz embedded connectivity with floating point unit (ef) family 12.4.5 output mapping in contrast to inputs, the outputs of the pps options are mapped on the basis of the pin. in this case, a control register associated with a particular pin dictates the peripheral output to be mapped. the rpnr registers ( register 12-2 ) are used to control output mapping. like the [ pin name ]r registers, each register contains sets of 4 bit fields. the value of the bit field corresponds to one of the peripherals, and that peripherals output is mapped to the pin (see table 12-3 and figure 12-3 ). a null output is associated with the output register reset value of 0 . this is done to ensure that remappable outputs remain disconnected from all output pins by default. figure 12-3: example of multiplexing of remappable output for rpf0 12.4.6 controlling configuration changes because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. pic32mz ef devices include two features to prevent alterations to the peripheral map: control register lock sequence configuration bit select lock 12.4.6.1 control register lock under normal operation, writes to the rpnr and [ pin name ]r registers are not allowed. attempted writes appear to execute normally, but the contents of the registers remain unchanged. to change these regis - ters, they must be unlocked in hardware. the regis - ter lock is controlled by the iolock configuration bit (cfgcon<13>). setting iolock prevents writes to the control registers; clearing iolock allows writes. to set or clear the iolock bit, an unlock sequence must be executed. refer to section 42. oscillators with enhanced pll in the ?pic32 family reference manual? for details. 12.4.6.2 configuration bit select lock as an additional level of safety, the device can be configured to prevent more than one write session to the rpnr and [ pin name ]r registers. the iol1way configuration bit (devcfg3<29>) blocks the iolock bit from being cleared after it has been set once. if iolock remains set, the register unlock procedure does not execute, and the pps control registers cannot be written to. the only way to clear the bit and re- enable peripheral remapping is to perform a device reset. in the default (unprogrammed) state, iol1way is set, restricting users to one write session. rpf0r<3:0> 0 15 1 default u1tx output u2rts output 2 14 output data rpf0 refclko1
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 254 ? 2015-2016 microchip technology inc. table 12-3: output pin selection rpn port pin rpnr sfr rpnr bits rpnr value to peripheral selection rpd2 rpd2r rpd2r<3:0> 0000 = no connect 0001 = u3tx 0010 = u4rts 0011 = reserved 0100 = reserved 0101 = sdo1 0110 = sdo2 0111 = sdo3 1000 = reserved 1001 = sdo5 (1) 1010 = ss6 (1) 1011 = oc3 1100 = oc6 1101 = refclko4 1110 = c2out 1111 = c1tx (3) rpg8 rpg8r rpg8r<3:0> rpf4 rpf4r rpf4r<3:0> rpd10 rpd10r rpd10r<3:0> rpf1 rpf1r rpf1r<3:0> rpb9 rpb9r rpb9r<3:0> rpb10 rpb10r rpb10r<3:0> rpc14 rpc14r rpc14r<3:0> rpb5 rpb5r rpb5r<3:0> rpc1 (1) rpc1r (1) rpc1r<3:0> (1) rpd14 (1) rpd14r (1) rpd14r<3:0> (1) rpg1 (1) rpg1r (1) rpg1r<3:0> (1) rpa14 (1) rpa14r (1) rpa14r<3:0> (1) rpd6 (2) rpd6r (2) rpd6r<3:0> (2) rpd3 rpd3r rpd3r<3:0> 0000 = no connect 0001 = u1tx 0010 = u2rts 0011 = u5tx 0100 = u6rts 0101 = sdo1 0110 = sdo2 0111 = sdo3 1000 = sdo4 1001 = sdo5 (1) 1010 = reserved 1011 = oc4 1100 = oc7 1101 = reserved 1110 = reserved 1111 = refclko1 rpg7 rpg7r rpg7r<3:0> rpf5 rpf5r rpf5r<3:0> rpd11 rpd11r rpd11r<3:0> rpf0 rpf0r rpf0r<3:0> rpb1 rpb1r rpb1r<3:0> rpe5 rpe5r rpe5r<3:0> rpc13 rpc13r rpc13r<3:0> rpb3 rpb3r rpb3r<3:0> rpc4 (1) rpc4r (1) rpc4r<3:0> (1) rpd15 (1) rpd15r (1) rpd15r<3:0> (1) rpg0 (1) rpg0r (1) rpg0r<3:0> (1) rpa15 (1) rpa15r (1) rpa15r<3:0> (1) rpd7 (2) rpd7r (2) rpd7r<3:0> (2) rpd9 rpd9r rpd9r<3:0> 0000 = no connect 0001 = u3rts 0010 = u4tx 0011 = reserved 0100 = u6tx 0101 = ss1 0110 = reserved 0111 = ss3 1000 = ss4 1001 = ss5 (1) 1010 = sdo6 (1) 1011 = oc5 1100 = oc8 1101 = reserved 1110 = c1out 1111 = refclko3 rpg6 rpg6r rpg6r<3:0> rpb8 rpb8r rpb8r<3:0> rpb15 rpb15r rpb15r<3:0> rpd4 rpd4r rpd4r<3:0> rpb0 rpb0r rpb0r<3:0> rpe3 rpe3r rpe3r<3:0> rpb7 rpb7r rpb7r<3:0> rpf12 (1) rpf12r (1) rpf12r<3:0> (1) rpd12 (1) rpd12r (1) rpd12r<3:0> (1) rpf8 (1) rpf8r (1) rpf8r<3:0> (1) rpc3 (1) rpc3r (1) rpc3r<3:0> (1) rpe9 (1) rpe9r (1) rpe9r<3:0> (1) note 1: this selection is not available on 64-pin devices. 2: this selection is not available on 64-pin or 100-pin devices. 3: this selection is not available on devices without a can module.
? 2015-2016 microchip technology inc. ds60001320d-page 255 pic32mz embedded connectivity with floating point unit (ef) family rpd1 rpd1r rpd1r<3:0> 0000 = no connect 0001 = u1rts 0010 = u2tx 0011 = u5rts 0100 = u6tx 0101 = reserved 0110 = ss2 0111 = reserved 1000 = sdo4 1001 = reserved 1010 = sdo6 (1) 1011 = oc2 1100 = oc1 1101 = oc9 1110 = reserved 1111 = c2tx (3) rpg9 rpg9r rpg9r<3:0> rpb14 rpb14r rpb14r<3:0> rpd0 rpd0r rpd0r<3:0> rpb6 rpb6r rpb6r<3:0> rpd5 rpd5r rpd5r<3:0> rpb2 rpb2r rpb2r<3:0> rpf3 rpf3r rpf3r<3:0> rpf13 (1) rpf13r (1) rpf13r<3:0> (1) rpc2 (1) rpc2r (1) rpc2r<3:0> (1) rpe8 (1) rpe8r (1) rpe8r<3:0> (1) rpf2 (1) rpf2r (1) rpf2r<3:0> (1) table 12-3: output pin selection (continued) rpn port pin rpnr sfr rpnr bits rpnr value to peripheral selection note 1: this selection is not available on 64-pin devices. 2: this selection is not available on 64-pin or 100-pin devices. 3: this selection is not available on devices without a can module.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 256 ? 2015-2016 microchip technology inc. 12.5 i/o ports control registers table 12-4: porta register map for 100-pin, 124-pin, and 144-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0000 ansela 31:16 0000 15:0 ansa10 ansa9 ansa5 ansa1 ansa0 0623 0010 trisa 31:16 0000 15:0 trisa15 trisa14 trisa10 trisa9 trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 c6ff 0020 porta 31:16 0000 15:0 ra15 ra14 ra10 ra9 ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 0030 lata 31:16 0000 15:0 lata15 lata14 lata10 lata9 lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 xxxx 0040 odca 31:16 0000 15:0 odca15 odca14 odca10 odca9 odca7 odca6 odca5 odca4 odca3 odca2 odca1 odca0 0000 0050 cnpua 31:16 0000 15:0 cnpua15 cnpua14 cnpua10 cnpua9 cnpua7 cnpua6 cnpua5 cnpua4 cnpua3 cnpua2 cnpua1 cnpua0 0000 0060 cnpda 31:16 0000 15:0 cnpda15 cnpda14 cnpda10 cnpda9 cnpda7 cnpda6 cnpda5 cnpda4 cnpda3 cnpda2 cnpda1 cnpda0 0000 0070 cncona 31:16 0000 15:0 on edgedetect 0000 0080 cnena 31:16 0000 15:0 cnena15 cnena14 cnena10 cnena9 cnena7 cnena6 cnena5 cnena4 cnena3 cnena2 cnena1 cnena0 0000 0090 cnstata 31:16 0000 15:0 cn stata15 cn stata14 cn stata10 cn stata9 cn stata7 cn stata6 cn stata5 cn stata4 cn stata3 cn stata2 cn stata1 cn stata0 0000 00a0 cnnea 31:16 0000 15:0 cnnea15 cnnea14 cnnea10 cnnea9 cnnea7 cnnea6 cnnea5 cnnea4 cnnea3 cnnea2 cnnea1 cnnea0 0000 00b0 cnfa 31:16 0000 15:0 cnfa15 cnfa14 cnfa10 cnfa9 cnfa7 cnfa76 cnfa5 cnfa4 cnfa3 cnfa2 cnfa71 cnfa0 0000 00c0 srcon0a 31:16 0000 15:0 sr0a7 sr0a6 0000 00d0 srcon1a 31:16 0000 15:0 sr1a7 sr0a6 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual add ress, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 257 pic32mz embedded connectivity with floating point unit (ef) family table 12-5: portb register map virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0100 anselb 31:16 0000 15:0 ansb15 ansb14 ansb13 ansb12 ansb11 ansb10 ansb9 ansb8 ansb7 ansb6 ansb5 ansb41 ansb3 ansb2 ansb1 ansb0 ffff 0110 trisb 31:16 0000 15:0 trisb15 trisb14 trisb13 trisb12 trisb11 trisb10 trisb9 trisb8 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 ffff 0120 portb 31:16 0000 15:0 rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx 0130 latb 31:16 0000 15:0 latb15 latb14 latb13 latb12 latb11 latb10 latb9 latb8 latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx 0140 odcb 31:16 0000 15:0 odcb15 odcb14 odcb13 odcb12 odcb11 odcb10 odcb9 odcb8 odcb7 odcb6 odcb5 odcb4 odcb3 odcb2 odcb1 odcb0 0000 0150 cnpub 31:16 0000 15:0 cnpub15 cnpub14 cnpub13 cnpub12 cnpub11 cnpub10 cnpub9 cnpub8 cnpub7 cnpub6 cnpub5 cnpub4 cnpub3 cnpub2 cnpub1 cnpub0 0000 0160 cnpdb 31:16 0000 15:0 cnpdb15 cnpdb14 cnpdb13 cnpdb12 cnpdb11 cnpdb10 cnpdb9 cnpdb8 cnpdb7 cnpdb6 cnpdb5 cnpdb4 cnpdb3 cnpdb2 cnpdb1 cnpdb0 0000 0170 cnconb 31:16 0000 15:0 on edge detect 0000 0180 cnenb 31:16 0000 15:0 cnenb15 cnenb14 cnenb13 cnenb12 cnenb11 cnenb10 cnenb9 cnenb8 cnenb7 cnenb6 cnenb5 cnenb4 cnenb3 cnenb2 cnenb1 cnenb0 0000 0190 cnstatb 31:16 0000 15:0 cn statb15 cn statb14 cn statb13 cn statb12 cn statb11 cn statb10 cn statb9 cn statb8 cn statb7 cn statb6 cn statb5 cn statb4 cn statb3 cn statb2 cn statb1 cn statb0 0000 01a0 cnneb 31:16 0000 15:0 cnneb15 cnneb14 cnneb13 cnneb12 cnneb11 cnneb10 cnneb9 cnneb8 cnneb7 cnneb6 cnneb5 cnneb4 cnneb3 cnneb2 cnneb1 cnneb0 0000 01b0 cnfb 31:16 0000 15:0 cnfb15 cnfb14 cnfb13 cnfb12 cnfb11 cnfb10 cnfb9 cnfb8 cnfb7 cnfb6 cnfb5 cnfb4 cnfb3 cnfb2 cnfb1 cnfb0 0000 01c0 srcon0b 31:16 0000 15:0 sr0b14 sr0b10 sr0b9 sr0b8 sr0b5 sr0b3 0000 01d0 srcon1b 31:16 0000 15:0 sr1b14 sr1b10 sr1b9 sr1b8 sr1b5 sr1b3 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual addr ess, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 258 ? 2015-2016 microchip technology inc. table 12-6: portc register map for 100-pin, 124-pin, and 144-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0200 anselc 31:16 0000 15:0 ansc4 ansc3 ansc2 ansc1 001e 0210 trisc 31:16 0000 15:0 trisc15 trisc14 trisc13 trisc12 trisc4 trisc3 trisc2 trisc1 f01e 0220 portc 31:16 0000 15:0 rc15 rc14 rc13 rc12 rc4 rc3 rc2 rc1 xxxx 0230 latc 31:16 0000 15:0 latc15 latc14 latc13 latc12 latc4 latc3 latc2 latc1 xxxx 0240 odcc 31:16 0000 15:0 odcc15 odcc14 odcc13 odcc12 odcc4 odcc3 odcc2 odcc1 0000 0250 cnpuc 31:16 0000 15:0 cnpuc15 cnpuc14 cnpuc13 cnpuc12 cnpuc4 cnpuc3 cnpuc2 cnpuc1 0000 0260 cnpdc 31:16 0000 15:0 cnpdc15 cnpdc14 cnpdc13 cnpdc12 cnpdc4 cnpdc3 cnpdc2 cnpdc1 0000 0270 cnconc 31:16 0000 15:0 on edge detect 0000 0280 cnenc 31:16 0000 15:0 cnenc15 cnenc14 cnenc13 cnenc12 cnenc4 cnenc3 cnenc2 cnenc1 0000 0290 cnstatc 31:16 0000 15:0 cnstatc15 cnstatc14 cnstatc13 cnstatc12 cnstatc4 cnstatc3 cnstatc2 cnstatc1 0000 02a0 cnnec 31:16 0000 15:0 cnnec15 cnnec14 cnnec13 cnnec12 cnnec4 cnnec3 cnnec2 cnnec1 0000 02b0 cnfc 31:16 0000 15:0 cnfc15 cnfc14 cnfc13 cnfc12 cnfc4 cnfc3 cnfc2 cnfc1 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual add ress, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 259 pic32mz embedded connectivity with floating point unit (ef) family table 12-7: portc register map for 64-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0210 trisc 31:16 0000 15:0 trisc15 trisc14 trisc13 trisc12 f000 0220 portc 31:16 0000 15:0 rc15 rc14 rc13 rc12 xxxx 0230 latc 31:16 0000 15:0 latc15 latc14 latc13 latc12 xxxx 0240 odcc 31:16 0000 15:0 odcc15 odcc14 odcc13 odcc12 xxxx 0250 cnpuc 31:16 0000 15:0 cnpuc15 cnpuc14 cnpuc13 cnpuc12 0000 0260 cnpdc 31:16 0000 15:0 cnpdc15 cnpdc14 cnpdc13 cnpdc12 0000 0270 cnconc 31:16 0000 15:0 on edge detect 0000 0280 cnenc 31:16 0000 15:0 cnenc15 cnenc14 cnenc13 cnenc12 0000 0290 cnstatc 31:16 0000 15:0 cnstatc15 cnstatc14 cnstatc13 cnstatc12 0000 02a0 cnnec 31:16 0000 15:0 cnnec15 cnnec14 cnnec13 cnnec12 0000 02b0 cnfc 31:16 0000 15:0 cnfc15 cnfc14 cnfc13 cnfc12 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual add ress, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 260 ? 2015-2016 microchip technology inc. table 12-8: portd register map for 124-pin and 144-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0300 anseld 31:16 0000 15:0 ansd15 ansd14 c000 0310 trisd 31:16 0000 15:0 trisd15 trisd14 trisd13 trisd12 trisd11 trisd10 trisd9 trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 feff 0320 portd 31:16 0000 15:0 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx 0330 latd 31:16 0000 15:0 latd15 latd14 latd13 latd12 latd11 latd10 latd9 latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx 0340 odcd 31:16 0000 15:0 odcd15 odcd14 odcd13 odcd12 odcd11 odcd10 odcd9 odcd7 odcd6 odcd5 odcd4 odcd3 odcd2 odcd1 odcd0 0000 0350 cnpud 31:16 0000 15:0 cnpud15 cnpud14 cnpud13 cnpud12 cnpud11 cnpud10 cnpud9 cnpud7 cnpud6 cnpud5 cnpud4 cnpud3 cnpud2 cnpud1 cnpud0 0000 0360 cnpdd 31:16 0000 15:0 cnpdd15 cnpdd14 cnpdd13 cnpdd12 cnpdd11 cnpdd10 cnpdd9 cnpdd7 cnpdd6 cnpdd5 cnpdd4 cnpdd3 cnpdd2 cnpdd1 cnpdd0 0000 0370 cncond 31:16 0000 15:0 on edge detect 0000 0380 cnend 31:16 0000 15:0 cnend15 cnend14 cnend13 cnend12 cnend11 cnend10 cnend9 cnend7 cnend6 cnend5 cnend4 cnend3 cnend2 cnend1 cnend0 0000 0390 cnstatd 31:16 0000 15:0 cn statd15 cn statd14 cn statd13 cn statd12 cn statd11 cn statd10 cn statd9 cn statd7 cn statd6 cn statd5 cn statd4 cn statd3 cn statd2 cn statd1 cn statd0 0000 03a0 cnned 31:16 0000 15:0 cnned15 cnned14 cnned13 cnned12 cnned11 cnned10 cnned9 cnned7 cnned6 cnned5 cnned4 cnned3 cnned2 cnned1 cnned0 0000 03b0 cnfd 31:16 0000 15:0 cnfd15 cnfd14 cnfd13 cnfd12 cnfd11 cnfd10 cnfd9 cnfd7 cnfd6 cnfd5 cnfd4 cnfd3 cnfd2 cnfd1 cnfd0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 261 pic32mz embedded connectivity with floating point unit (ef) family table 12-9: portd register map for 100-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0300 anseld 31:16 0000 15:0 ansd15 ansd14 c000 0310 trisd 31:16 0000 15:0 trisd15 trisd14 trisd13 trisd12 trisd11 trisd10 trisd9 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 fe3f 0320 portd 31:16 0000 15:0 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd5 rd4 rd3 rd2 rd1 rd0 xxxx 0330 latd 31:16 0000 15:0 latd15 latd14 latd13 latd12 latd11 latd10 latd9 latd5 latd4 latd3 latd2 latd1 latd0 xxxx 0340 odcd 31:16 0000 15:0 odcd15 odcd14 odcd13 odcd12 odcd11 odcd10 odcd9 odcd5 odcd4 odcd3 odcd2 odcd1 odcd0 0000 0350 cnpud 31:16 0000 15:0 cnpud15 cnpud14 cnpud13 cnpud12 cnpud11 cnpud10 cnpud9 cnpud5 cnpud4 cnpud3 cnpud2 cnpud1 cnpud0 0000 0360 cnpdd 31:16 0000 15:0 cnpdd15 cnpdd14 cnpdd13 cnpdd12 cnpdd11 cnpdd10 cnpdd9 cnpdd5 cnpdd4 cnpdd3 cnpdd2 cnpdd1 cnpdd0 0000 0370 cncond 31:16 0000 15:0 on edge detect 0000 0380 cnend 31:16 0000 15:0 cnend15 cnend14 cnend13 cnend12 cnend11 cnend10 cnend9 cnend5 cnend4 cnend3 cnend2 cnend1 cnend0 0000 0390 cnstatd 31:16 0000 15:0 cn statd15 cn statd14 cn statd13 cn statd12 cn statd11 cn statd10 cn statd9 cn statd5 cn statd4 cn statd3 cn statd2 cn statd1 cn statd0 0000 03a0 cnned 31:16 0000 15:0 cnned15 cnned14 cnned13 cnned12 cnned11 cnned10 cnned9 cnned5 cnned4 cnned3 cnned2 cnned1 cnned0 0000 03b0 cnfd 31:16 0000 15:0 cnfd15 cnfd14 cnfd13 cnfd12 cnfd11 cnfd10 cnfd9 cnfd5 cnfd4 cnfd3 cnfd2 cnfd1 cnfd0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its vi rtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 262 ? 2015-2016 microchip technology inc. table 12-10: portd register map for 64-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0310 trisd 31:16 0000 15:0 trisd11 trisd10 trisd9 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 0e3f 0320 portd 31:16 0000 15:0 rd11 rd10 rd9 rd5 rd4 rd3 rd2 rd1 rd0 xxxx 0330 latd 31:16 0000 15:0 latd11 latd10 latd9 latd5 latd4 latd3 latd2 latd1 latd0 xxxx 0340 odcd 31:16 0000 15:0 odcd11 odcd10 odcd9 odcd5 odcd4 odcd3 odcd2 odcd1 odcd0 0000 0350 cnpud 31:16 0000 15:0 cnpud11 cnpud10 cnpud9 cnpud5 cnpud4 cnpud3 cnpud2 cnpud1 cnpud0 0000 0360 cnpdd 31:16 0000 15:0 cnpdd11 cnpdd10 cnpdd9 cnpdd5 cnpdd4 cnpdd3 cnpdd2 cnpdd1 cnpdd0 0000 0370 cncond 31:16 0000 15:0 on edge detect 0000 0380 cnend 31:16 0000 15:0 cnend11 cnend10 cnend9 cnend5 cnend4 cnend3 cnend2 cnend1 cnend0 0000 0390 cnstatd 31:16 0000 15:0 cn statd11 cn statd10 cn statd9 cn statd5 cn statd4 cn statd3 cn statd2 cn statd1 cn statd0 0000 03a0 cnned 31:16 0000 15:0 cnned11 cnned10 cnned9 cnned5 cnned4 cnned3 cnned2 cnned1 cnned0 0000 03b0 cnfd 31:16 0000 15:0 cnfd11 cnfd10 cnfd9 cnfd5 cnfd4 cnfd3 cnfd2 cnfd1 cnfd0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual add ress, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 263 pic32mz embedded connectivity with floating point unit (ef) family table 12-11: porte register map for 100-pin, 124-pin, and 144-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0400 ansele 31:16 0000 15:0 anse9 anse8 anse7 anse6 anse5 anse4 03f0 0410 trise 31:16 0000 15:0 trise9 trise8 trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 03ff 0420 porte 31:16 0000 15:0 re9 re8 re7 re6 re5 re4 re3 re2 re1 re0 xxxx 0430 late 31:16 0000 15:0 late9 late8 late7 late6 late5 late4 late3 late2 late1 late0 xxxx 0440 odce 31:16 0000 15:0 odce9 odce8 odce7 odce6 odce5 odce4 odce3 odce2 odce1 odce0 0000 0450 cnpue 31:16 0000 15:0 cnpue9 cnpue8 cnpue7 cnpue6 cnpue5 cnpue4 cnpue3 cnpue2 cnpue1 cnpue0 0000 0460 cnpde 31:16 0000 15:0 cnpde9 cnpde8 cnpde7 cnpde6 cnpde5 cnpde4 cnpde3 cnpde2 cnpde1 cnpde0 0000 0470 cncone 31:16 0000 15:0 on edge detect 0000 0480 cnene 31:16 0000 15:0 cnene9 cnene8 cnene7 cnene6 cnene5 cnene4 cnene3 cnene2 cnene1 cnene0 0000 0490 cnstate 31:16 0000 15:0 cn state9 cn state8 cn state7 cn state6 cn state5 cn state4 cn state3 cn state2 cn state1 cn state0 0000 04a0 cnnee 31:16 0000 15:0 cnnee9 cnnee8 cnnee7 cnnee6 cnnee5 cnnee4 cnnee3 cnnee2 cnnee1 cnnee0 0000 04b0 cnfe 31:16 0000 15:0 cnfe9 cnfe8 cnfe7 cnfe6 cnfe5 cnfe4 cnfe3 cnfe2 cnfe1 cnfe0 0000 04c0 srcon0e 31:16 0000 15:0 sr0e3 sr0e2 sr0e1 sr0e0 0000 04d0 srcon1e 31:16 0000 15:0 sr1e3 sr1e2 sr1e1 sr1e0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual add ress, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 264 ? 2015-2016 microchip technology inc. table 12-12: porte register map for 64-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0400 ansele 31:16 0000 15:0 anse7 anse6 anse5 anse4 00f0 0410 trise 31:16 0000 15:0 trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 00ff 0420 porte 31:16 0000 15:0 re7 re6 re5 re4 re3 re2 re1 re0 xxxx 0430 late 31:16 0000 15:0 late7 late6 late5 late4 late3 late2 late1 late0 xxxx 0440 odce 31:16 0000 15:0 odce7 odce6 odce5 odce4 odce3 odce2 odce1 odce0 0000 0450 cnpue 31:16 0000 15:0 cnpue7 cnpue6 cnpue5 cnpue4 cnpue3 cnpue2 cnpue1 cnpue0 0000 0460 cnpde 31:16 0000 15:0 cnpde7 cnpde6 cnpde5 cnpde4 cnpde3 cnpde2 cnpde1 cnpde0 0000 0470 cncone 31:16 0000 15:0 on edge detect 0000 0480 cnene 31:16 0000 15:0 cnene7 cnene6 cnene5 cnene4 cnene3 cnene2 cnene1 cnene0 0000 0490 cnstate 31:16 0000 15:0 cn state7 cn state6 cn state5 cn state4 cn state3 cn state2 cn state1 cn state0 0000 04a0 cnnee 31:16 0000 15:0 cnnee7 cnnee6 cnnee5 cnnee4 cnnee3 cnnee2 cnnee1 cnnee0 0000 04b0 cnfe 31:16 0000 15:0 cnfe7 cnfe6 cnfe5 cnfe4 cnfe3 cnfe2 cnfe1 cnfe0 0000 04c0 srcon0e 31:16 0000 15:0 sr0e3 sr0e2 sr0e1 sr0e0 0000 04d0 srcon1e 31:16 0000 15:0 sr1e3 sr1e2 sr1e1 sr1e0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual add ress, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 265 pic32mz embedded connectivity with floating point unit (ef) family table 12-13: portf register map for 100-pin, 124-pin, and 144-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0500 anself 31:16 0000 15:0 ansf13 ansf12 3000 0510 trisf 31:16 0000 15:0 trisf13 trisf12 trisf8 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 313f 0520 portf 31:16 0000 15:0 rf13 rf12 rf8 rf5 rf4 rf3 rf2 rf1 rf0 xxxx 0530 latf 31:16 0000 15:0 latf13 latf12 latf8 latf5 latf4 latf3 latf2 latf1 latf0 xxxx 0540 odcf 31:16 0000 15:0 odcf13 odcf12 odcf8 odcf5 odcf4 odcf3 odcf2 odcf1 odcf0 0000 0550 cnpuf 31:16 0000 15:0 cnpuf13 cnpuf12 cnpuf8 cnpuf5 cnpuf4 cnpuf3 cnpuf2 cnpuf1 cnpuf0 0000 0560 cnpdf 31:16 0000 15:0 cnpdf13 cnpdf12 cnpdf8 cnpdf5 cnpdf4 cnpdf3 cnpdf2 cnpdf1 cnpdf0 0000 0570 cnconf 31:16 0000 15:0 on edge detect 0000 0580 cnenf 31:16 0000 15:0 cnenf13 cnenf12 cnenf8 cnenf5 cnenf4 cnenf3 cnenf2 cnenf1 cnenf0 0000 0590 cnstatf 31:16 0000 15:0 cn statf13 cn statf12 cn statf8 cn statf5 cn statf4 cn statf3 cn statf2 cn statf1 cn statf0 0000 05a0 cnnef 31:16 0000 15:0 cnnef13 cnnef12 cnnef8 cnnef5 cnnef4 cnnef3 cnnef2 cnnef1 cnnef0 0000 05b0 cnff 31:16 0000 15:0 cnff13 cnff12 cnff8 cnff5 cnff4 cnff3 cnff2 cnff1 cnff0 0000 05c0 srcon0f 31:16 0000 15:0 sr0f1 sr0f0 0000 05d0 srcon1f 31:16 0000 15:0 sr1f1 sr1f0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual add ress, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 266 ? 2015-2016 microchip technology inc. table 12-14: portf register map for 64-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0510 trisf 31:16 0000 15:0 trisf5 trisf4 trisf3 trisf1 trisf0 003b 0520 portf 31:16 0000 15:0 rf5 rf4 rf3 rf1 rf0 xxxx 0530 latf 31:16 0000 15:0 latf5 latf4 latf3 latf1 latf0 xxxx 0540 odcf 31:16 0000 15:0 odcf5 odcf4 odcf3 odcf1 odcf0 0000 0550 cnpuf 31:16 0000 15:0 cnpuf5 cnpuf4 cnpuf3 cnpuf1 cnpuf0 0000 0560 cnpdf 31:16 0000 15:0 cnpdf5 cnpdf4 cnpdf3 cnpdf1 cnpdf0 0000 0570 cnconf 31:16 0000 15:0 on edge detect 0000 0580 cnenf 31:16 0000 15:0 cnenf5 cnenf4 cnenf3 cnenf1 cnenf0 0000 0590 cnstatf 31:16 0000 15:0 cn statf5 cn statf4 cn statf3 cn statf1 cn statf0 0000 05a0 cnnef 31:16 0000 15:0 cnnef5 cnnef4 cnnef3 cnnef1 cnnef0 0000 05b0 cnff 31:16 0000 15:0 cnff5 cnff4 cnff3 cnff1 cnff0 0000 05c0 srcon0f 31:16 0000 15:0 sr0f1 sr0f0 0000 05d0 srcon1f 31:16 0000 15:0 sr1f1 sr2f0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual add ress, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 267 pic32mz embedded connectivity with floating point unit (ef) family table 12-15: portg register map for 100- pin, 124-pin, and 144-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0600 anselg 31:16 0000 15:0 ansg15 ansg9 ansg8 ansg7 ansg6 83c0 0610 trisg 31:16 0000 15:0 trisg15 trisg14 trisg13 trisg12 trisg9 trisg8 trisg7 trisg6 trisg1 trisg0 f3c3 0620 portg 31:16 0000 15:0 rg15 rg14 rg13 rg12 rg9 rg8 rg7 rg6 rg1 rg0 xxxx 0630 latg 31:16 0000 15:0 latg15 latg14 latg13 latg12 latg9 latg8 latg7 latg6 latg1 latg0 xxxx 0640 odcg 31:16 0000 15:0 odcg15 odcg14 odcg13 odcg12 odcg9 odcg8 odcg7 odcg6 odcg1 odcg0 0000 0650 cnpug 31:16 0000 15:0 cnpug15 cnpug14 cnpug13 cnpug12 cnpug9 cnpug8 cnpug7 cnpug6 cnpug1 cnpug0 0000 0660 cnpdg 31:16 0000 15:0 cnpdg15 cnpdg14 cnpdg13 cnpdg12 cnpdg9 cnpdg8 cnpdg7 cnpdg6 cnpdg1 cnpdg0 0000 0670 cncong 31:16 0000 15:0 on edge detect 0000 0680 cneng 31:16 0000 15:0 cneng15 cneng14 cneng13 cneng12 cneng9 cneng8 cneng7 cneng6 cneng1 cneng0 0000 0690 cnstatg 31:16 0000 15:0 cn statg15 cn statg14 cn statg13 cn statg12 cn statg9 cn statg8 cn statg7 cn statg6 cn statg1 cn statg0 0000 06a0 cnneg 31:16 0000 15:0 cnneg15 cnneg14 cnneg13 cnneg12 cnneg9 cnneg8 cnneg7 cnneg6 cnneg1 cnneg0 0000 06b0 cnfg 31:16 0000 15:0 cnfg15 cnfg14 cnfg13 cnfg12 cnfg9 cnfg8 cnfg7 cnfg6 cnfg1 cnfg0 0000 06c0 srcon0g 31:16 0000 15:0 sr0g14 sr0g13 sr0g12 sr0g9 sr0g6 0000 06d0 srcon1g 31:16 0000 15:0 sr1g14 sr1g13 sr1g12 sr1g9 sr1g6 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual add ress, plus an offset of 0x4, 0x8, a nd 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 268 ? 2015-2016 microchip technology inc. table 12-16: portg register map for 64-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0600 anselg 31:16 0000 15:0 ansg9 ansg8 ansg7 ansg6 03c0 0610 trisg 31:16 0000 15:0 trisg9 trisg8 trisg7 trisg6 03c0 0620 portg 31:16 0000 15:0 rg9 rg8 rg7 rg6 xxxx 0630 latg 31:16 0000 15:0 latg9 latg8 latg7 latg6 xxxx 0640 odcg 31:16 0000 15:0 odcg9 odcg8 odcg7 odcg6 0000 0650 cnpug 31:16 0000 15:0 cnpug9 cnpug8 cnpug7 cnpug6 0000 0660 cnpdg 31:16 0000 15:0 cnpdg9 cnpdg8 cnpdg7 cnpdg6 0000 0670 cncong 31:16 0000 15:0 on edge detect 0000 0680 cneng 31:16 0000 15:0 cneng9 cneng8 cneng7 cneng6 0000 0690 cnstatg 31:16 0000 15:0 cn statg9 cn statg8 cn statg7 cn statg6 0000 06a0 cnneg 31:16 0000 15:0 cnneg9 cnneg8 cnneg7 cnneg6 0000 06b0 cnfg 31:16 0000 15:0 cnfg9 cnfg8 cnfg7 cnfg6 0000 06c0 srcon0g 31:16 0000 15:0 sr0g9 sr0g6 0000 06d0 srcon1g 31:16 0000 15:0 sr1g9 sr1g6 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual add ress, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 269 pic32mz embedded connectivity with floating point unit (ef) family table 12-17: porth register map for 124-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0700 anselh 31:16 0000 15:0 ansh6 ansh5 ansh4 ansh1 ansh0 0073 0710 trish 31:16 0000 15:0 trish13 trish12 trish10 trish9 trish8 trish6 trish5 trish4 trish1 trish0 3773 0720 porth 31:16 0000 15:0 rh13 rh12 rh10 rh9 rh8 rh6 rh5 rh4 rh1 rh0 xxxx 0730 lath 31:16 0000 15:0 lath13 lath12 lath10 lath9 lath8 lath6 lath5 lath4 lath1 lath0 xxxx 0740 odch 31:16 0000 15:0 odch13 odch12 odch10 odch9 odch8 odch6 odch5 odch4 odch1 odch0 0000 0750 cnpuh 31:16 0000 15:0 cnpuh13 cnpuh12 cnpuh10 cnpuh9 cnpuh8 cnpuh6 cnpuh5 cnpuh4 cnpuh1 cnpuh0 0000 0760 cnpdh 31:16 0000 15:0 cnpdh13 cnpdh12 cnpdh10 cnpdh9 cnpdh8 cnpdh6 cnpdh5 cnpdh4 cnpdh1 cnpdh0 0000 0770 cnconh 31:16 0000 15:0 on edge detect 0000 0780 cnenh 31:16 0000 15:0 cnenh13 cnenh12 cnenh10 cnenh9 cnenh8 cnenh6 cnenh5 cnenh4 cnenh1 cnenh0 0000 0790 cnstath 31:16 0000 15:0 cn stath13 cn stath12 cn stath10 cn stath9 cn stath8 cn stath6 cn stath5 cn stath4 cn stath1 cn stath0 0000 07a0 cnneh 31:16 0000 15:0 cnneh13 cnneh12 cnneh10 cnneh9 cnneh8 cnneh6 cnneh5 cnneh4 cnneh1 cnneh0 0000 07b0 cnfh 31:16 0000 15:0 cnfh13 cnfh12 cnfh10 cnfh9 cnfh8 cnfh6 cnfh5 cnfh4 cnfh1 cnfh0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual addr ess, plus an offset of 0x4, 0x8, a nd 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 270 ? 2015-2016 microchip technology inc. table 12-18: porth register map for 144-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0700 anselh 31:16 0000 15:0 ansh6 ansh5 ansh4 ansh1 ansh0 0073 0710 trish 31:16 0000 15:0 trish15 trish14 trish13 trish12 trish11 trish10 trish9 trish8 trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 ffff 0720 porth 31:16 0000 15:0 rh15 rh14 rh13 rh12 rh11 rh10 rh9 rh8 rh7 rh6 rh5 rh4 rh3 rh2 rh1 rh0 xxxx 0730 lath 31:16 0000 15:0 lath15 lath14 lath13 lath12 lath11 lath10 lath9 lath8 lath7 lath6 lath5 lath4 lath3 lath2 lath1 lath0 xxxx 0740 odch 31:16 0000 15:0 odch15 odch14 odch13 odch12 odch11 odch10 odch9 odch8 odch7 odch6 odch5 odch4 odch3 odch2 odch1 odch0 0000 0750 cnpuh 31:16 0000 15:0 cnpuh15 cnpuh14 cnpuh13 cnpuh12 cnpuh11 cnpuh10 cnpuh9 cnpuh8 cnpuh7 cnpuh6 cnpuh5 cnpuh4 cnpuh3 cnpuh2 cnpuh1 cnpuh0 0000 0760 cnpdh 31:16 0000 15:0 cnpdh15 cnpdh14 cnpdh13 cnpdh12 cnpdh11 cnpdh10 cnpdh9 cnpdh8 cnpdh7 cnpdh6 cnpdh5 cnpdh4 cnpdh3 cnpdh2 cnpdh1 cnpdh0 0000 0770 cnconh 31:16 0000 15:0 on edge detect 0000 0780 cnenh 31:16 0000 15:0 cnenh15 cnenh14 cnenh13 cnenh12 cnenh11 cnenh10 cnenh9 cnenh8 cnenh7 cnenh6 cnenh5 cnenh4 cnenh3 cnenh2 cnenh1 cnenh0 0000 0790 cnstath 31:16 0000 15:0 cn stath15 cn stath14 cn stath13 cn stath12 cn stath11 cn stath10 cn stath9 cn stath8 cn stath7 cn stath6 cn stath5 cn stath4 cn stath3 cn stath2 cn stath1 cn stath0 0000 07a0 cnneh 31:16 0000 15:0 cnneh15 cnneh14 cnneh13 cnneh12 cnneh11 cnneh10 cnneh9 cnneh8 cnneh7 cnneh6 cnneh5 cnneh4 cnneh3 cnneh2 cnneh1 cnneh0 0000 07b0 cnfh 31:16 0000 15:0 cnfh15 cnfh14 cnfh13 cnfh12 cnfh11 cnfh10 cnfh9 cnfh8 cnfh7 cnfh6 cnfh5 cnfh4 cnfh3 cnfh2 cnfh1 cnfh0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual addr ess, plus an offset of 0x4, 0x8, a nd 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 271 pic32mz embedded connectivity with floating point unit (ef) family table 12-19: portj register map for 124-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0800 anselj 31:16 0000 15:0 ansj11 ansj9 ansj8 0b00 0810 trisj 31:16 0000 15:0 trisj11 trisj9 trisj8 trisj4 trisj2 trisj1 trisj0 0b17 0820 portj 31:16 0000 15:0 rj11 rj9 rj8 rj4 rj2 rj1 rj0 xxxx 0830 latj 31:16 0000 15:0 latj11 latj9 latj8 latj4 latj2 latj1 latj0 xxxx 0840 odcj 31:16 0000 15:0 odcj11 odcj9 odcj8 odcj4 odcj2 odcj1 odcj0 0000 0850 cnpuj 31:16 0000 15:0 cnpuj11 cnpuj9 cnpuj8 cnpuj4 cnpuj2 cnpuj1 cnpuj0 0000 0860 cnpdj 31:16 0000 15:0 cnpdj11 cnpdj9 cnpdj8 cnpdj4 cnpdj2 cnpdj1 cnpdj0 0000 0870 cnconj 31:16 0000 15:0 on edge detect 0000 0880 cnenj 31:16 0000 15:0 cnenj11 cnenj9 cnenj8 cnenj4 cnenj2 cnenj1 cnenj0 0000 0890 cnstatj 31:16 0000 15:0 cn statj11 cn statj9 cn statj8 cn statj4 cn statj2 cn statj1 cn statj0 0000 08a0 cnnej 31:16 0000 15:0 cnnej11 cnnej9 cnnej8 cnnej4 cnnej2 cnnej1 cnnej0 0000 08b0 cnfj 31:16 0000 15:0 cnfj11 cnfj9 cnfj8 cnfj4 cnfj2 cnfj1 cnfj0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual a ddress, plus an offset of 0x4, 0x8, a nd 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 272 ? 2015-2016 microchip technology inc. table 12-20: portj register map for 144-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0800 anselj 31:16 0000 15:0 ansj11 ansj9 ansj8 0b00 0810 trisj 31:16 0000 15:0 trisj15 trisj14 trisj13 trisj12 trisj11 trisj10 trisj9 trisj8 trisj7 trisj6 trisj5 trisj4 trisj3 trisj2 trisj1 trisj0 ffff 0820 portj 31:16 0000 15:0 rj15 rj14 rj13 rj12 rj11 rj10 rj9 rj8 rj7 rj6 rj5 rj4 rj3 rj2 rj1 rj0 xxxx 0830 latj 31:16 0000 15:0 latj15 latj14 latj13 latj12 latj11 latj10 latj9 latj8 latj7 latj6 latj5 latj4 latj3 latj2 latj1 latj0 xxxx 0840 odcj 31:16 0000 15:0 odcj15 odcj14 odcj13 odcj12 odcj11 odcj10 odcj9 odcj18 odcj7 odcj6 odcj5 odcj4 odcj3 odcj2 odcj1 odcj0 0000 0850 cnpuj 31:16 0000 15:0 cnpuj15 cnpuj14 cnpuj13 cnpuj12 cnpuj11 cnpuj10 cnpuj9 cnpuj8 cnpuj7 cnpuj6 cnpuj5 cnpuj4 cnpuj3 cnpuj2 cnpuj1 cnpuj0 0000 0860 cnpdj 31:16 0000 15:0 cnpdj15 cnpdj14 cnpdj13 cnpdj12 cnpdj11 cnpdj10 cnpdj9 cnpdj8 cnpdj7 cnpdj6 cnpdj5 cnpdj4 cnpdj3 cnpdj2 cnpdj1 cnpdj0 0000 0870 cnconj 31:16 0000 15:0 on edge detect 0000 0880 cnenj 31:16 0000 15:0 cnenj15 cnenj14 cnenj13 cnenj12 cnenj11 cnenj10 cnenj9 cnenj8 cnenj7 cnenj6 cnenj5 cnenj4 cnenj3 cnenj2 cnenj1 cnenj0 0000 0890 cnstatj 31:16 0000 15:0 cn statj15 cn statj14 cn statj13 cn statj12 cn statj11 cn statj10 cn statj9 cn statj8 cn statj7 cn statj6 cn statj5 cn statj4 cn statj3 cn statj2 cn statj1 cn statj0 0000 08a0 cnnej 31:16 0000 15:0 cnnej15 cnnej14 cnnej13 cnnej12 cnnej11 cnnej10 cnnej9 cnnej8 cnnej7 cnnej6 cnnej5 cnnej4 cnnej3 cnnej2 cnnej1 cnnej0 0000 08b0 cnfj 31:16 0000 15:0 cnfj15 cnfj14 cnfj13 cnfj12 cnfj11 cnfj10 cnfj9 cnfj8 cnfj7 cnfj6 cnfj5 cnfj4 cnfj3 cnfj2 cnfj1 cnfj0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual a ddress, plus an offset of 0x4, 0x8, a nd 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 273 pic32mz embedded connectivity with floating point unit (ef) family table 12-21: portk register map for 144-pin devices only virtual address (bf86_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0910 trisk 31:16 0000 15:0 trisk7 trisk6 trisk5 trisk4 trisk3 trisk2 trisk1 trisk0 00ff 0920 portk 31:16 0000 15:0 rk7 rk6 rk5 rk4 rk3 rk2 rk1 rk0 xxxx 0930 latk 31:16 0000 15:0 latk7 latk6 latk5 latk4 latk3 latk2 latk1 latk0 xxxx 0940 odck 31:16 0000 15:0 odck7 odck6 odck5 odck4 odck3 odck2 odck1 odck0 0000 0950 cnpuk 31:16 0000 15:0 cnpuk7 cnpuk6 cnpuk5 cnpuk4 cnpuk3 cnpuk2 cnpuk1 cnpuk0 0000 0960 cnpdk 31:16 0000 15:0 cnpdk7 cnpdk6 cnpdk5 cnpdk4 cnpdk3 cnpdk2 cnpdk1 cnpdk0 0000 0970 cnconk 31:16 0000 15:0 on edge detect 0000 0980 cnenk 31:16 0000 15:0 cnenk7 cnenk6 cnenk5 cnenk4 cnenk3 cnenk2 cnenk1 cnenk0 0000 0990 cnstatk 31:16 0000 15:0 cn statk7 cn statk6 cn statk5 cn statk4 cn statk3 cn statk2 cn statk1 cn statk0 0000 09a0 cnnek 31:16 0000 15:0 cnnek7 cnnek6 cnnek5 cnnek4 cnnek3 cnnek2 cnnek1 cnnek0 0000 09b0 cnfk 31:16 0000 15:0 cnfk7 cnfk6 cnfk5 cnfk4 cnfk3 cnfk2 cnfk1 cnfk0 0000 legend: x = unknown value on reset; = unimplemented, read as 0 ; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual addr ess, plus an offset of 0x4, 0x8, a nd 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 274 ? 2015-2016 microchip technology inc. table 12-22: peripheral pin select input register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1404 int1r 31:16 0000 15:0 i n t 1 r < 3 : 0 > 0000 1408 int2r 31:16 0000 15:0 i n t 2 r < 3 : 0 > 0000 140c int3r 31:16 0000 15:0 i n t 3 r < 3 : 0 > 0000 1410 int4r 31:16 0000 15:0 i n t 4 r < 3 : 0 > 0000 1418 t2ckr 31:16 0000 15:0 t 2 c k r < 3 : 0 > 0000 141c t3ckr 31:16 0000 15:0 t 3 c k r < 3 : 0 > 0000 1420 t4ckr 31:16 0000 15:0 t 4 c k r < 3 : 0 > 0000 1424 t5ckr 31:16 0000 15:0 t 5 c k r < 3 : 0 > 0000 1428 t6ckr 31:16 0000 15:0 t 6 c k r < 3 : 0 > 0000 142c t7ckr 31:16 0000 15:0 t 7 c k r < 3 : 0 > 0000 1430 t8ckr 31:16 0000 15:0 t 8 c k r < 3 : 0 > 0000 1434 t9ckr 31:16 0000 15:0 t 9 c k r < 3 : 0 > 0000 1438 ic1r 31:16 0000 15:0 ic1r<3:0> 0000 143c ic2r 31:16 0000 15:0 ic2r<3:0> 0000 1440 ic3r 31:16 0000 15:0 ic3r<3:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register is not available on 64-pin devices. 2: this register is not available on devices without a can module.
? 2015-2016 microchip technology inc. ds60001320d-page 275 pic32mz embedded connectivity with floating point unit (ef) family 1444 ic4r 31:16 0000 15:0 ic4r<3:0> 0000 1448 ic5r 31:16 0000 15:0 ic5r<3:0> 0000 144c ic6r 31:16 0000 15:0 ic6r<3:0> 0000 1450 ic7r 31:16 0000 15:0 ic7r<3:0> 0000 1454 ic8r 31:16 0000 15:0 ic8r<3:0> 0000 1458 ic9r 31:16 0000 15:0 ic9r<3:0> 0000 1460 ocfar 31:16 0000 15:0 o c f a r < 3 : 0 > 0000 1468 u1rxr 31:16 0000 15:0 u 1 r x r < 3 : 0 > 0000 146c u1ctsr 31:16 0000 15:0 u1ctsr<3:0> 0000 1470 u2rxr 31:16 0000 15:0 u 2 r x r < 3 : 0 > 0000 1474 u2ctsr 31:16 0000 15:0 u2ctsr<3:0> 0000 1478 u3rxr 31:16 0000 15:0 u 3 r x r < 3 : 0 > 0000 147c u3ctsr 31:16 0000 15:0 u3ctsr<3:0> 0000 1480 u4rxr 31:16 0000 15:0 u 4 r x r < 3 : 0 > 0000 1484 u4ctsr 31:16 0000 15:0 u4ctsr<3:0> 0000 table 12-22: peripheral pin select input register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register is not available on 64-pin devices. 2: this register is not available on devices without a can module.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 276 ? 2015-2016 microchip technology inc. 1488 u5rxr 31:16 0000 15:0 u 5 r x r < 3 : 0 > 0000 148c u5ctsr 31:16 0000 15:0 u5ctsr<3:0> 0000 1490 u6rxr 31:16 0000 15:0 u 6 r x r < 3 : 0 > 0000 1494 u6ctsr 31:16 0000 15:0 u6ctsr<3:0> 0000 149c sdi1r 31:16 0000 15:0 s d i 1 r < 3 : 0 > 0000 14a0 ss1r 31:16 0000 15:0 ss1r<3:0> 0000 14a8 sdi2r 31:16 0000 15:0 s d i 2 r < 3 : 0 > 0000 14ac ss2r 31:16 0000 15:0 ss2r<3:0> 0000 14b4 sdi3r 31:16 0000 15:0 s d i 3 r < 3 : 0 > 0000 14b8 ss3r 31:16 0000 15:0 ss3r<3:0> 0000 14c0 sdi4r 31:16 0000 15:0 s d i 4 r < 3 : 0 > 0000 14c4 ss4r 31:16 0000 15:0 ss4r<3:0> 0000 14cc sdi5r (1) 31:16 0000 15:0 s d i 5 r < 3 : 0 > 0000 14d0 ss5r (1) 31:16 0000 15:0 ss5r<3:0> 0000 14d8 sdi6r (1) 31:16 0000 15:0 s d i 6 r < 3 : 0 > 0000 table 12-22: peripheral pin select input register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register is not available on 64-pin devices. 2: this register is not available on devices without a can module.
? 2015-2016 microchip technology inc. ds60001320d-page 277 pic32mz embedded connectivity with floating point unit (ef) family 14dc ss6r (1) 31:16 0000 15:0 ss6r<3:0> 0000 14e0 c1rxr (2) 31:16 0000 15:0 c 1 r x r < 3 : 0 > 0000 14e4 c2rxr (2) 31:16 0000 15:0 c 2 r x r < 3 : 0 > 0000 14e8 refclki1r 31:16 0000 15:0 refclki1r<3:0> 0000 14f0 refclki3r 31:16 0000 15:0 refclki3r<3:0> 0000 14f4 refclki4r 31:16 0000 15:0 refclki4r<3:0> 0000 table 12-22: peripheral pin select input register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register is not available on 64-pin devices. 2: this register is not available on devices without a can module.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 278 ? 2015-2016 microchip technology inc. table 12-23: peripheral pin select output register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 1 6/0 1538 rpa14r (1) 31:16 0000 15:0 rpa14r<3:0> 0000 153c rpa15r (1) 31:16 0000 15:0 rpa15r<3:0> 0000 1540 rpb0r 31:16 0000 15:0 rpb0r<3:0> 0000 1544 rpb1r 31:16 0000 15:0 rpb1r<3:0> 0000 1548 rpb2r 31:16 0000 15:0 rpb2r<3:0> 0000 154c rpb3r 31:16 0000 15:0 rpb3r<3:0> 0000 1554 rpb5r 31:16 0000 15:0 rpb5r<3:0> 0000 1558 rpb6r 31:16 0000 15:0 rpb6r<3:0> 0000 155c rpb7r 31:16 0000 15:0 rpb7r<3:0> 0000 1560 rpb8r 31:16 0000 15:0 rpb8r<3:0> 0000 1564 rpb9r 31:16 0000 15:0 rpb9r<3:0> 0000 1568 rpb10r 31:16 0000 15:0 rpb10r<3:0> 0000 1578 rpb14r 31:16 0000 15:0 rpb14r<3:0> 0000 157c rpb15r 31:16 0000 15:0 rpb15r<3:0> 0000 1584 rpc1r (1) 31:16 0000 15:0 r p c 1 r < 3 : 0 > 0000 1588 rpc2r (1) 31:16 0000 15:0 r p c 2 r < 3 : 0 > 0000 158c rpc3r (1) 31:16 0000 15:0 r p c 3 r < 3 : 0 > 0000 1590 rpc4r (1) 31:16 0000 15:0 r p c 4 r < 3 : 0 > 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register is not available on 64-pin devices. 2: this register is not available on 64-pin and 100-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 279 pic32mz embedded connectivity with floating point unit (ef) family 15b4 rpc13r 31:16 0000 15:0 rpc13r<3:0> 0000 15b8 rpc14r 31:16 0000 15:0 rpc14r<3:0> 0000 15c0 rpd0r 31:16 0000 15:0 r p d 0 r < 3 : 0 > 0000 15c4 rpd1r 31:16 0000 15:0 r p d 1 r < 3 : 0 > 0000 15c8 rpd2r 31:16 0000 15:0 r p d 2 r < 3 : 0 > 0000 15cc rpd3r 31:16 0000 15:0 r p d 3 r < 3 : 0 > 0000 15d0 rpd4r 31:16 0000 15:0 r p d 4 r < 3 : 0 > 0000 15d4 rpd5r 31:16 0000 15:0 r p d 5 r < 3 : 0 > 0000 15d8 rpd6r (2) 31:16 0000 15:0 r p d 6 r < 3 : 0 > 0000 15dc rpd7r (2) 31:16 0000 15:0 r p d 7 r < 3 : 0 > 0000 15e4 rpd9r 31:16 0000 15:0 r p d 9 r < 3 : 0 > 0000 15e8 rpd10r 31:16 0000 15:0 rpd10r<3:0> 0000 15ec rpd11r 31:16 0000 15:0 r p d 1 1 r < 3 : 0 > 0000 15f0 rpd12r (1) 31:16 0000 15:0 rpd12r<3:0> 0000 15f8 rpd14r (1) 31:16 0000 15:0 rpd14r<3:0> 0000 15fc rpd15r (1) 31:16 0000 15:0 rpd15r<3:0> 0000 160c rpe3r 31:16 0000 15:0 rpe3r<3:0> 0000 1614 rpe5r 31:16 0000 15:0 rpe5r<3:0> 0000 table 12-23: peripheral pin select output register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 1 6/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register is not available on 64-pin devices. 2: this register is not available on 64-pin and 100-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 280 ? 2015-2016 microchip technology inc. 1620 rpe8r (1) 31:16 0000 15:0 rpe8r<3:0> 0000 1624 rpe9r (1) 31:16 0000 15:0 rpe9r<3:0> 0000 1640 rpf0r 31:16 0000 15:0 r p f 0 r < 3 : 0 > 0000 1644 rpf1r 31:16 0000 15:0 r p f 1 r < 3 : 0 > 0000 1648 rpf2r (1) 31:16 0000 15:0 r p f 2 r < 3 : 0 > 0000 164c rpf3r 31:16 0000 15:0 r p f 3 r < 3 : 0 > 0000 1650 rpf4r 31:16 0000 15:0 r p f 4 r < 3 : 0 > 0000 1654 rpf5r 31:16 0000 15:0 r p f 5 r < 3 : 0 > 0000 1660 rpf8r (1) 31:16 0000 15:0 r p f 8 r < 3 : 0 > 0000 1670 rpf12r (1) 31:16 0000 15:0 rpg12r<3:0> 0000 1674 rpf13r (1) 31:16 0000 15:0 r p g 0 r < 3 : 0 > 0000 1680 rpg0r (1) 31:16 0000 15:0 r p g 1 r < 3 : 0 > 0000 1684 rpg1r (1) 31:16 0000 15:0 r p g 1 r < 3 : 0 > 0000 1698 rpg6r 31:16 0000 15:0 r p g 6 r < 3 : 0 > 0000 169c rpg7r 31:16 0000 15:0 r p g 7 r < 3 : 0 > 0000 16a0 rpg8r 31:16 0000 15:0 r p g 8 r < 3 : 0 > 0000 16a4 rpg9r 31:16 0000 15:0 r p g 9 r < 3 : 0 > 0000 table 12-23: peripheral pin select output register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 1 6/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register is not available on 64-pin devices. 2: this register is not available on 64-pin and 100-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 281 pic32mz embedded connectivity with floating point unit (ef) family register 12-1: [ pin name ]r: peripheral pin select input register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 [ pin name ]r<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as 0 bit 3-0 [ pin name ]r<3:0>: peripheral pin select input bits where [ pin name ] refers to the pins that are used to configure peripheral input mapping. see table 12-2 for input pin selection values. note: register values can only be changed if the iolock configuration bit (cfgcon<13>) = 0 . register 12-2: rpnr: peripheral pin select output register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 rpnr<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as 0 bit 3-0 rpnr<3:0>: peripheral pin select output bits see table 12-3 for output pin selection values. note: register values can only be changed if the iolock configuration bit (cfgcon<13>) = 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 282 ? 2015-2016 microchip technology inc. register 12-3: cnconx: change notice cont rol for portx register (x = a C k) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 u-0 u-0 u-0 r/w-0 u-0 u-0 u-0 on edgedetect 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 on: change notice (cn) control on bit 1 = cn is enabled 0 = cn is disabled bit 14-12 unimplemented: read as 0 bit 11 edgedetect: change notification style bit 1 = edge style. detect edge transitions (cnfx used for cn event). 0 = mismatch style. detect change from last portx read (cnstatx used for cn event). bit 10-0 unimplemented: read as 0
? 2015-2016 microchip technology inc. ds60001320d-page 283 pic32mz embedded connectivity with floating point unit (ef) family 13.0 timer1 pic32mz ef devices feature one synchronous/asyn - chronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. this timer can also be used with the low-power secondary oscillator (s osc ) for real-time clock applications. the following modes are supported by timer1: synchronous internal timer synchronous internal gated timer synchronous external timer asynchronous external timer 13.1 additional supported features selectable clock prescaler timer operation during sleep and idle modes fast bit manipulation using clr, set and inv registers asynchronous mode can be used with the s osc to function as a real-time clock adc event trigger figure 13-1: timer1 block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 14. timers (ds60001105) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). on sync sosci sosco/t1ck pr1 t1if equal 16-bit comparator tmr1 reset soscen (1) event flag 1 0 tsync tgate tgate pbclk3 1 0 tcs gate sync tckps<1:0> prescaler 2 1, 8, 64, 256 x 1 1 0 0 0 q qd note 1: the default state of the soscen bit (osccon<1>) during a device reset is controlled by the fsoscen bit in configuration word, devcfg1. trigger to adc
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 284 ? 2015-2016 microchip technology inc. 13.2 timer1 control register table 13-1: timer1 register map virtual address (bf84_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0000 t1con 31:16 0000 15:0 on sidl twdis twip tgate tckps<1:0> tsync tcs 0000 0010 tmr1 31:16 0000 15:0 tmr1<15:0> 0000 0020 pr1 31:16 0000 15:0 pr1<15:0> ffff legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, p lus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 285 pic32mz embedded connectivity with floating point unit (ef) family register 13-1: t1con: type a timer control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 u-0 r/w-0 r/w-0 r-0 u-0 u-0 u-0 on sidl twdis twip 7:0 r/w-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 tgate tckps<1:0> tsync tcs legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 on: timer on bit 1 = timer is enabled 0 = timer is disabled bit 14 unimplemented: read as 0 bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters idle mode 0 = continue operation even in idle mode bit 12 twdis: asynchronous timer write disable bit 1 = writes to tmr1 are ignored until pending write operation completes 0 = back-to-back writes are enabled (legacy asynchronous timer functionality) bit 11 twip: asynchronous timer write in progress bit in asynchronous timer mode: 1 = asynchronous write to tmr1 register in progress 0 = asynchronous write to tmr1 register complete in synchronous timer mode: this bit is read as 0 . bit 10-8 unimplemented: read as 0 bit 7 tgate: timer gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 6 unimplemented: read as 0 bit 5-4 tckps<1:0>: timer input clock prescale select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 unimplemented: read as 0
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 286 ? 2015-2016 microchip technology inc. bit 2 tsync: timer external clock input synchronization selection bit when tcs = 1 : 1 = external clock input is synchronized 0 = external clock input is not synchronized when tcs = 0 : this bit is ignored. bit 1 tcs: timer clock source select bit 1 = external clock from t1cki pin 0 = internal peripheral clock bit 0 unimplemented: read as 0 register 13-1: t1con: type a time r control register (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 287 pic32mz embedded connectivity with floating point unit (ef) family 14.0 timer2/3, timer4/5, timer6/7, and timer8/9 the pic32mz ef family of devices features eight synchronous 16-bit timers (default) that can operate as a free-running interval timer for various timing applications and counting external events. the following modes are supported: synchronous internal 16-bit timer synchronous internal 16-bit gated timer synchronous external 16-bit timer four 32-bit synchronous timers are available by combining timer2 with timer3, timer4 with timer5, timer6 with timer7, and timer8 with timer9. the 32-bit timers can operate in one of three modes: synchronous internal 32-bit timer synchronous internal 32-bit gated timer synchronous external 32-bit timer 14.1 additional supported features selectable clock prescaler timers operational during cpu idle time base for input capture and output compare modules (timer2 through timer7 only) adc event trigger (timer3 and timer5 only) fast bit manipulation using clr, set, and inv registers figure 14-1: timer2 through timer9 block diagram (16-bit) note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive refer - ence source. to complement the informa - tion in this data sheet, refer to section 14. timers (ds60001105) of the ?pic32 family reference manual? , which is avail - able from the microchip web site ( www.microchip.com/pic32 ). sync prx txif event flag equal comparator x 16 tmrx reset q qd tgate 1 0 gate txck sync on tgate tcs tckps prescaler 3 1, 2, 4, 8, 16, 32, 64, 256 x 1 1 0 0 0 pbclk3 trigger to adc (1) note 1: the adc event trigger is available on timer3 and timer5 only.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 288 ? 2015-2016 microchip technology inc. figure 14-2: timer2/3, timer4/5, timer6/7, and timer8/9 block diagram (32-bit) tmry (2) tmrx (2) tyif event flag (2) equal 32-bit comparator pry (2) prx (2) reset ls half word ms half word note 1: adc event trigger is available only on the timer2/3 and timer4/5 pairs. 2: in this diagram, x represents timer2, 4, 6, or 8, and y represents timer 3, 5, 7, or 9. tgate 0 1 pbclk3 gate txck (2) sync sync adc event trigger (1) on tgate tcs tckps prescaler 3 1, 2, 4, 8, 16, 32, 64, 256 1 0 0 0 q q d x 1
? 2015-2016 microchip technology inc. ds60001320d-page 289 pic32mz embedded connectivity with floating point unit (ef) family 14.2 timer2-timer9 control registers table 14-1: timer2 through timer9 register map virtual address (bf84_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0200 t2con 31:16 0000 15:0 on sidl tgate tckps<2:0> t32 tcs 0000 0210 tmr2 31:16 0000 15:0 tmr2<15:0> 0000 0220 pr2 31:16 0000 15:0 pr2<15:0> ffff 0400 t3con 31:16 0000 15:0 on sidl tgate tckps<2:0> tcs 0000 0410 tmr3 31:16 0000 15:0 tmr3<15:0> 0000 0420 pr3 31:16 0000 15:0 pr3<15:0> ffff 0600 t4con 31:16 0000 15:0 on sidl tgate tckps<2:0> t32 tcs 0000 0610 tmr4 31:16 0000 15:0 tmr4<15:0> 0000 0620 pr4 31:16 0000 15:0 pr4<15:0> ffff 0800 t5con 31:16 0000 15:0 on sidl tgate tckps<2:0> tcs 0000 0810 tmr5 31:16 0000 15:0 tmr5<15:0> 0000 0820 pr5 31:16 0000 15:0 pr5<15:0> ffff 0a00 t6con 31:16 0000 15:0 on sidl tgate tckps<2:0> t32 tcs 0000 0a10 tmr6 31:16 0000 15:0 tmr6<15:0> 0000 0a20 pr6 31:16 0000 15:0 pr6<15:0> ffff 0c00 t7con 31:16 0000 15:0 on sidl tgate tckps<2:0> tcs 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, p lus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 290 ? 2015-2016 microchip technology inc. 0c10 tmr7 31:16 0000 15:0 tmr7<15:0> 0000 0c20 pr7 31:16 0000 15:0 pr7<15:0> ffff 0e00 t8con 31:16 0000 15:0 on sidl tgate tckps<2:0> t32 tcs 0000 0e10 tmr8 31:16 0000 15:0 tmr8<15:0> 0000 0e20 pr8 31:16 0000 15:0 pr8<15:0> ffff 1000 t9con 31:16 0000 15:0 on sidl tgate tckps<2:0> tcs 0000 1010 tmr9 31:16 0000 15:0 tmr9<15:0> 0000 1020 pr9 31:16 0000 15:0 pr9<15:0> ffff table 14-1: timer2 through timer9 register map (continued) virtual address (bf84_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, p lus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 291 pic32mz embedded connectivity with floating point unit (ef) family register 14-1: txcon: type b time r control register (x = 2-9) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on (1) s i d l (2) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 tgate (1) tckps<2:0> (1) t32 (3) t c s (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 on: timer on bit (1) 1 = module is enabled 0 = module is disabled bit 14 unimplemented: read as 0 bit 13 sidl: stop in idle mode bit (2) 1 = discontinue operation when device enters idle mode 0 = continue operation even in idle mode bit 12-8 unimplemented: read as 0 bit 7 tgate: timer gated time accumulation enable bit (1) when tcs = 1 : this bit is ignored and is read as 0 . when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 6-4 tckps<2:0>: timer input clock prescale select bits (1) 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value bit 3 t32: 32-bit timer mode select bit (3) 1 = odd numbered and even numbered timers form a 32-bit timer 0 = odd numbered and even numbered timers form separate 16-bit timers note 1: while operating in 32-bit mode, this bit has no effect for odd numbered timers (timer1, timer3, timer5, timer7, and timer9). all timer functions are set through the even numbered timers. 2: while operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in idle mode. 3: this bit is available only on even numbered timers (timer2, timer4, timer6, and timer8).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 292 ? 2015-2016 microchip technology inc. bit 2 unimplemented: read as 0 bit 1 tcs: timer clock source select bit (1) 1 = external clock from txck pin 0 = internal peripheral clock bit 0 unimplemented: read as 0 register 14-1: txcon: type b timer cont rol register (x = 2-9) (continued) note 1: while operating in 32-bit mode, this bit has no effect for odd numbered timers (timer1, timer3, timer5, timer7, and timer9). all timer functions are set through the even numbered timers. 2: while operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in idle mode. 3: this bit is available only on even numbered timers (timer2, timer4, timer6, and timer8).
? 2015-2016 microchip technology inc. ds60001320d-page 293 pic32mz embedded connectivity with floating point unit (ef) family 15.0 deadman timer (dmt) the primary function of the deadman timer (dmt) is to reset the processor in the event of a software mal - function. the dmt is a free-running instruction fetch timer, which is clocked whenever an instruction fetch occurs until a count match occurs. instructions are not fetched when the processor is in sleep mode. the dmt consists of a 32-bit counter with a time-out count match value as specified by the dmtcnt<3:0> bits in the devcfg1 configuration register. a deadman timer is typically used in mission critical and safety critical applications, where any single fail - ure of the software functionality and sequencing must be detected. figure 15-1 shows a block diagram of the deadman timer module. figure 15-1: deadman timer block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 9. watchdog, deadman, and power-up timers (ds60001114) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 32-bit counter on pbclk7 proper clear sequence flag on clock on dmt count reset load dmt event system reset system reset instruction fetched strobe force dmt event improper sequence flag 32 (counter) ? ? dmt window interval (2) window interval open (counter) = dmt max count (1) counter initialization value note 1: dmt max count is controlled by the dmtcnt<3:0> bits in the devcfg1 configuration regi ster. 2: dmt window interval is controlled by the dmtintv<2:0> bits in the devcfg1 confi guration register. 3: refer to section 6.0 resets for more information. to nmi (3)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 294 ? 2015-2016 microchip technology inc. 15.1 deadman timer control registers table 15-1: deadman timer register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0a00 dmtcon 31:16 0000 15:0 on x000 0a10 dmtpreclr 31:16 0000 15:0 step1<7:0> 0000 0a20 dmtclr 31:16 0000 15:0 step2<7:0> 0000 0a30 dmtstat 31:16 0000 15:0 bad1 bad2 dmtevent winopn 0000 0a40 dmtcnt 31:16 counter<31:0> 0000 15:0 0000 0a60 dmtpscnt 31:16 pscnt<31:0> 0000 15:0 00xx 0a70 dmtpsintv 31:16 psintv<31:0> 0000 15:0 000x legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal.
? 2015-2016 microchip technology inc. ds60001320d-page 295 pic32mz embedded connectivity with floating point unit (ef) family register 15-1: dmtcon: deadman timer control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-y u-0 u-0 u-0 u-0 u-0 u-0 u-0 on (1) 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 on: deadman timer module enable bit (1) 1 = deadman timer module is enabled 0 = deadman timer module is disabled the reset value of this bit is determined by the setting of the fdmten bit (devcfg1<3>). bit 13-0 unimplemented: read as 0 note 1: this bit only has control when fdmten (devcfg1<3>) = 0 . register 15-2: dmtpreclr: deadman timer preclear register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 step1<7:0> 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-8 step1<7:0>: preclear enable bits 01000000 = enables the deadman timer preclear (step 1) all other write patterns = set bad1 flag. these bits are cleared when a dmt reset event occurs. step1<7:0> is also cleared if the step2<7:0> bits are loaded with the correct value in the correct sequence. bit 7-0 unimplemented: read as 0
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 296 ? 2015-2016 microchip technology inc. register 15-3: dmtclr: deadman timer clear register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 step2<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as 0 bit 7-0 step2<7:0>: clear timer bits 00001000 = clears step1<7:0>, step2<7:0> and the deadman timer if, and only if, preceded by cor- rect loading of step1<7:0> bits in the correct sequence. the write to these bits may be verified by reading dmtcnt and observing the counter being reset. all other write patterns = set bad2 bit, the value of step1<7:0> will remain unchanged, and the new value being written step2<7:0> will be captured. these bits are also cleared when a dmt reset event occurs.
? 2015-2016 microchip technology inc. ds60001320d-page 297 pic32mz embedded connectivity with floating point unit (ef) family register 15-4: dmtstat: deadman timer status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r-0, hc, hs r-0, hc, hs r-0, hc, hs u-0 u-0 u-0 u-0 r-0, hc, hs bad1 bad2 dmtevent w i n o p n legend: hc = hardware cleared hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as 0 bit 7 bad1: bad step1<7:0> value detect bit 1 = incorrect step1<7:0> value was detected 0 = incorrect step1<7:0> value was not detected bit 6 bad2: bad step2<7:0> value detect bit 1 = incorrect step2<7:0> value was detected 0 = incorrect step2<7:0> value was not detected bit 5 dmtevent: deadman timer event bit 1 = deadman timer event was detected (counter expired or bad step1<7:0 > or step2<7:0> value was entered prior to counter increment) 0 = deadman timer even was not detected bit 4-1 unimplemented: read as 0 bit 0 winopn: deadman timer clear window bit 1 = deadman timer clear window is open 0 = deadman timer clear window is not open
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 298 ? 2015-2016 microchip technology inc. register 15-5: dmtcnt: deadman timer count register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 counter<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 counter<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 counter<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 counter<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-8 counter<31:0>: read current contents of dmt counter register 15-6: dmtpscnt: post status configure dmt count status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 pscnt<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 pscnt<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 pscnt<15:8> 7:0 r-0 r-0 r-0 r-y r-y r-y r-y r-y pscnt<7:0> legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-8 pscnt<31:0>: dmt instruction count value configuration status bits this is always the value of the dmtcnt<4:0> bits in the devcfg1 configuration register.
? 2015-2016 microchip technology inc. ds60001320d-page 299 pic32mz embedded connectivity with floating point unit (ef) family register 15-7: dmtpsintv: post status co nfigure dmt interval status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 psintv<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 psintv<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 psintv<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-y r-y r-y psintv<7:0> legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-8 psintv<31:0>: dmt window interval configuration status bits this is always the value of the dmtintv<2:0> bits in the devcfg1 configuration register.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 300 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 301 pic32mz embedded connectivity with floating point unit (ef) family 16.0 watchdog timer (wdt) when enabled, the watchdog timer (wdt) operates from the internal low-power oscillator (lprc) clock source and can be used to detect system software mal - functions by resetting the device if the wdt is not cleared periodically in software. various wdt time-out periods can be selected using the wdt postscaler. the wdt can also be used to wake the device from sleep or idle mode. the following are key features of the wdt module: configuration or software controlled user-configurable time-out period can wake the device from sleep or idle figure 16-1: watchdog timer block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to sec - tion 9. watchdog, deadman, and power-up timers (ds60001114) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). wake wdtclrkey<15:0> = 0x5743 on power save 32-bit counter wdt counter reset 32 wdt event rundiv<4:0> (wdtcon<12:8>) clock decoder 0 1 on reset event to nmi (1) note 1: refer to 6.0 resets for more information. on lprc
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 302 ? 2015-2016 microchip technology inc. 16.1 watchdog timer control registers table 16-1: watchdog timer register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0800 wdtcon (1) 31:16 wdtclrkey<15:0> 0000 15:0 on rundiv<4:0> wdtwinen xx00 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at it s virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see 12.0 i/o ports for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 303 pic32mz embedded connectivity with floating point unit (ef) family register 16-1: wdtcon: wat chdog timer control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 wdtclrkey<15:8> 23:16 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 wdtclrkey<7:0> 15:8 r/w-y u-0 u-0 r-y r-y r-y r-y r-y on (1) rundiv<4:0> 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 wdtwinen legend: y = values set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 wdtclrkey: watchdog timer clear key bits to clear the watchdog timer to prevent a time-out, software must write the value 0x5743 to this location using a single 16-bit write. bit 15 on: watchdog timer enable bit (1) 1 = the wdt is enabled 0 = the wdt is disabled bit 14-13 unimplemented: read as 0 bit 12-8 rundiv<4:0>: watchdog timer postscaler value bits on reset, these bits are set to the values of the wdtps<4:0> configuration bits in devcfg1. bit 7-1 unimplemented: read as 0 bit 0 wdtwinen: watchdog timer window enable bit 1 = enable windowed watchdog timer 0 = disable windowed watchdog timer note 1: this bit only has control when the fwdten bit (devcfg1<23>) = 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 304 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 305 pic32mz embedded connectivity with floating point unit (ef) family 17.0 input capture the input capture module is useful in applications requiring frequency (period) and pulse measurement. the input capture module captures the 16-bit or 32-bit value of the selected time base registers when an event occurs at the icx pin. capture events are caused by the following: capture timer value on every edge (rising and falling), specified edge first prescaler capture event modes: - capture timer value on every 4th rising edge of input at icx pin - capture timer value on every 16th rising edge of input at icx pin each input capture channel can select between one of six 16-bit timers for the time base, or two of six 16-bit timers together to form a 32-bit timer. the selected timer can use either an internal or external clock. other operational features include: device wake-up from capture pin during sleep and idle modes interrupt on input capture event 4-word fifo buffer for capture values; interrupt optionally generated after 1, 2, 3, or 4 buffer locations are filled input capture can also be used to provide additional sources of external interrupts figure 17-1: input capture block diagram note: this data sheet summarizes the fea - tures of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 15. input cap - ture (ds60001122) of the ?pic32 fam - ily reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). fifo control icxbuf (1) timerx (2) capture event /n fifo ici<1:0> icm<2:0> icm<2:0> 101 100 011 010 001 001111 to cpu set flag icxif (1) (in ifsx register) rising edge mode prescaler mode (4th rising edge) fallingedgemode edge detection prescaler mode (16th rising edge) sleep/idle wake-up mode c32/ictmr icx (1) mode 110 specified/every edge mode fedge pbclk3 note 1: an x in a signal, register or bit name denotes the number of the capture channel . 2: see table 17-1 for timerx and timery selections. timery (2)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 306 ? 2015-2016 microchip technology inc. the timer source for each input capture module depends on the setting of the icaclk bit in the cfgcon register. the available configurations are shown in tab l e 17-1 . table 17-1: timer source configurations input capture module timerx timery icaclk (cfgcon<17>) = 0 ic1 ic9 timer2 timer2 timer3 timer3 icaclk (cfgcon<17>) = 1 ic1 timer4 timer5 ic2 timer4 timer5 ic3 timer4 timer5 ic4 timer2 timer3 ic5 timer2 timer3 ic6 timer2 timer3 ic7 timer6 timer7 ic8 timer6 timer7 ic9 timer6 timer7
? 2015-2016 microchip technology inc. ds60001320d-page 307 pic32mz embedded connectivity with floating point unit (ef) family 17.1 input capture control registers table 17-2: input capture 1 throug h input capture 9 register map virtual address (bf84_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 ic1con (1) 31:16 0000 15:0 on sidl fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2010 ic1buf 31:16 ic1buf<31:0> xxxx 15:0 xxxx 2200 ic2con (1) 31:16 0000 15:0 on sidl fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2210 ic2buf 31:16 ic2buf<31:0> xxxx 15:0 xxxx 2400 ic3con (1) 31:16 0000 15:0 on sidl fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2410 ic3buf 31:16 ic3buf<31:0> xxxx 15:0 xxxx 2600 ic4con (1) 31:16 0000 15:0 on sidl fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2610 ic4buf 31:16 ic4buf<31:0> xxxx 15:0 xxxx 2800 ic5con (1) 31:16 0000 15:0 on sidl fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2810 ic5buf 31:16 ic5buf<31:0> xxxx 15:0 xxxx 2a00 ic6con (1) 31:16 0000 15:0 on sidl fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2a10 ic6buf 31:16 ic6buf<31:0> xxxx 15:0 xxxx 2c00 ic7con (1) 31:16 0000 15:0 on sidl fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2c10 ic7buf 31:16 ic7buf<31:0> xxxx 15:0 xxxx 2e00 ic8con (1) 31:16 0000 15:0 on sidl fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2e10 ic8buf 31:16 ic8buf<31:0> xxxx 15:0 xxxx 3000 ic9con (1) 31:16 0000 15:0 on sidl fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 3010 ic9buf 31:16 ic9buf<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at it s virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 308 ? 2015-2016 microchip technology inc. register 17-1: ic x con: input capture x control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 on s i d l f e d g ec 3 2 7:0 r/w-0 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 ictmr (1) ici<1:0> icov icbne icm<2:0> legend: r = readable bit w = writable bit u = unimplemented bit -n = bit value at por: (0, 1, x = unknown) p = programmable bit r = reserved bit bit 31-16 unimplemented: read as 0 bit 15 on: input capture module enable bit 1 = module is enabled 0 = disable and reset module, disable clocks, disable interrupt generation and allow sfr modificatio ns bit 14 unimplemented: read as 0 bit 13 sidl: stop in idle control bit 1 = halt in cpu idle mode 0 = continue to operate in cpu idle mode bit 12-10 unimplemented: read as 0 bit 9 fedge: first capture edge select bit (only used in mode 6, icm<2:0> = 110 ) 1 = capture rising edge first 0 = capture falling edge first bit 8 c32: 32-bit capture select bit 1 = 32-bit timer resource capture 0 = 16-bit timer resource capture bit 7 ictmr: timer select bit (does not affect timer selection when c32 (icxcon<8>) is 1 ) (1) 0 = timery is the counter source for capture 1 = timerx is the counter source for capture bit 6-5 ici<1:0>: interrupt control bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture overflow status flag bit (read-only) 1 = input capture overflow is occurred 0 = no input capture overflow is occurred bit 3 icbne: input capture buffer not empty status bit (read-only) 1 = input capture buffer is not empty; at least one more capture value can be read 0 = input capture buffer is empty bit 2-0 icm<2:0>: input capture mode select bits 111 = interrupt-only mode (only supported while in sleep mode or idle mode) 110 = simple capture event mode C every edge, specified edge first and every edge thereafter 101 = prescaled capture event mode C every sixteenth rising edge 100 = prescaled capture event mode C every fourth rising edge 011 = simple capture event mode C every rising edge 010 = simple capture event mode C every falling edge 001 = edge detect mode C every edge (rising and falling) 000 = input capture module is disabled note 1: refer to table 17-1 for timerx and timery selections.
? 2015-2016 microchip technology inc. ds60001320d-page 309 pic32mz embedded connectivity with floating point unit (ef) family 18.0 output compare the output compare module is used to generate a single pulse or a train of pulses in response to selected time base events. for all modes of operation, the output compare mod - ule compares the values stored in the ocxr and/or the ocxrs registers to the value in the selected timer. when a match occurs, the output compare module generates an event based on the selected mode of operation. the following are key features of the output compare module: multiple output compare modules in a device programmable interrupt generation on compare event single and dual compare modes single and continuous output pulse generation pulse-width modulation (pwm) mode hardware-based pwm fault detection and automatic output disable programmable selection of 16-bit or 32-bit time bases can operate from either of two available 16-bit time bases or a single 32-bit time base adc event trigger figure 18-1: output comp are module block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 16. output compare (ds60001111) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). ocxr (1) comparator output logic q s r ocm<2:0> output enable ocx (1) set flag bit ocxif (1) ocxrs (1) mode select 3 note 1: where x is shown, reference is made to the registers associated with the respective output compare channels, 1 through 9. 2: the ocfa pin controls the oc1, oc3, and oc7-oc9 channels. the ocfb pin controls the oc4-oc6 channels. 3: refer to table 18-1 for timerx and timery selections. 4: the adc event trigger is only available on oc1, oc3, and oc 5. 0 1 octsel 0 1 16 16 ocfa or timerx (3) timerx (3) logic output enable pbclk3 timery (3) rollover timery (3) rollover ocfb (2) trigger to adc (4)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 310 ? 2015-2016 microchip technology inc. the timer source for each output compare module depends on the setting of the ocaclk bit in the cfg - con register. the available configurations are shown in table 18-1 . table 18-1: timer source configurations output compare module timerx timery ocaclk (cfgcon<16>) = 0 oc1 oc9 timer2 timer2 timer3 timer3 ocaclk (cfgcon<16>) = 1 oc1 timer4 timer5 oc2 timer4 timer5 oc3 timer4 timer5 oc4 timer2 timer3 oc5 timer2 timer3 oc6 timer2 timer3 oc7 timer6 timer7 oc8 timer6 timer7 oc9 timer6 timer7
? 2015-2016 microchip technology inc. ds60001320d-page 311 pic32mz embedded connectivity with floating point unit (ef) family 18.1 output compare control registers table 18-2: output compare 1 throug h output compare 9 register map virtual address (bf84_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 4000 oc1con 31:16 0000 15:0 on sidl oc32 ocflt octsel ocm<2:0> 0000 4010 oc1r 31:16 oc1r<31:0> xxxx 15:0 xxxx 4020 oc1rs 31:16 oc1rs<31:0> xxxx 15:0 xxxx 4200 oc2con 31:16 0000 15:0 on sidl oc32 ocflt octsel ocm<2:0> 0000 4210 oc2r 31:16 oc2r<31:0> xxxx 15:0 xxxx 4220 oc2rs 31:16 oc2rs<31:0> xxxx 15:0 xxxx 4400 oc3con 31:16 0000 15:0 on sidl oc32 ocflt octsel ocm<2:0> 0000 4410 oc3r 31:16 oc3r<31:0> xxxx 15:0 xxxx 4420 oc3rs 31:16 15:0 oc3rs<31:0> xxxx xxxx 4600 oc4con 31:16 0000 15:0 on sidl oc32 ocflt octsel ocm<2:0> 0000 4610 oc4r 31:16 oc4r<31:0> xxxx 15:0 xxxx 4620 oc4rs 31:16 15:0 oc4rs<31:0> xxxx xxxx 4800 oc5con 31:16 0000 15:0 on sidl oc32 ocflt octsel ocm<2:0> 0000 4810 oc5r 31:16 oc5r<31:0> xxxx 15:0 xxxx 4820 oc5rs 31:16 oc5rs<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 312 ? 2015-2016 microchip technology inc. 4a00 oc6con 31:16 0000 15:0 on sidl oc32 ocflt octsel ocm<2:0> 0000 4a10 oc6r 31:16 oc6r<31:0> xxxx 15:0 xxxx 4a20 oc6rs 31:16 oc6rs<31:0> xxxx 15:0 xxxx 4c00 oc7con 31:16 0000 15:0 on sidl oc32 ocflt octsel ocm<2:0> 0000 4c10 oc7r 31:16 oc7r<31:0> xxxx 15:0 xxxx 4c20 oc7rs 31:16 oc7rs<31:0> xxxx 15:0 xxxx 4e00 oc8con 31:16 0000 15:0 on sidl oc32 ocflt octsel ocm<2:0> 0000 4e10 oc8r 31:16 oc8r<31:0> xxxx 15:0 xxxx 4e20 oc8rs 31:16 15:0 oc8rs<31:0> xxxx xxxx 5000 oc9con 31:16 0000 15:0 on sidl oc32 ocflt octsel ocm<2:0> 0000 5010 oc9r 31:16 oc9r<31:0> xxxx 15:0 xxxx 5020 oc9rs 31:16 15:0 oc9rs<31:0> xxxx table 18-2: output compare 1 through output compare 9 register map (continued) virtual address (bf84_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16 /0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 313 pic32mz embedded connectivity with floating point unit (ef) family register 18-1: ocxcon: output compare x control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on s i d l 7:0 u-0 u-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 oc32 ocflt (1) octsel (2) ocm<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 on: output compare peripheral on bit 1 = output compare peripheral is enabled 0 = output compare peripheral is disabled bit 14 unimplemented: read as 0 bit 13 sidl: stop in idle mode bit 1 = discontinue operation when cpu enters idle mode 0 = continue operation in idle mode bit 12-6 unimplemented: read as 0 bit 5 oc32: 32-bit compare mode bit 1 = ocxr<31:0> and/or ocxrs<31:0> are used for comparisons to the 32-bit timer source 0 = ocxr<15:0> and ocxrs<15:0> are used for comparisons to the 16-bit timer source bit 4 ocflt: pwm fault condition status bit (1) 1 = pwm fault condition has occurred (cleared in hw only) 0 = no pwm fault condition has occurred bit 3 octsel: output compare timer select bit (2) 1 = timery is the clock source for this output compare module 0 = timerx is the clock source for this output compare module bit 2-0 ocm<2:0>: output compare mode select bits 111 = pwm mode on ocx; fault pin is enabled 110 = pwm mode on ocx; fault pin is disabled 101 = initialize ocx pin low; generate continuous output pulses on ocx pin 100 = initialize ocx pin low; generate single output pulse on ocx pin 011 = compare event toggles ocx pin 010 = initialize ocx pin high; compare event forces ocx pin low 001 = initialize ocx pin low; compare event forces ocx pin high 000 = output compare peripheral is disabled but continues to draw current note 1: this bit is only used when ocm<2:0> = 111 . it is read as 0 in all other modes. 2: refer to table 18-1 for timerx and timery selections.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 314 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 315 pic32mz embedded connectivity with floating point unit (ef) family 19.0 serial peripheral interface (spi) and inter-ic sound (i 2 s) the spi/i 2 s module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices, as well as digital audio devices. these peripheral devices may be serial eeproms, shift registers, display drivers, analog-to-digital converters, and so on. the spi/i 2 s module is compatible with motorola ? spi and siop interfaces. the following are key features of the spi module: master and slave modes support four different clock formats enhanced framed spi protocol support user-configurable 8-bit, 16-bit and 32-bit data width separate spi fifo buffers for receive and transmit - fifo buffers act as 4/8/16-level deep fifos based on 32/16/8-bit data width programmable interrupt event on every 8-bit, ? 16-bit and 32-bit data transfer operation during sleep and idle modes audio codec support: -i 2 s protocol - left-justified - right-justified -pcm figure 19-1: spi/i 2 s module block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive refer - ence source. to complement the informa - tion in this data sheet, refer to section 23. serial peripheral interface (spi) (ds60001106) in the ?pic32 family refer - ence manual? , which is available from the microchip web site ( www.microchip.com/ pic32 ). internal data bus sdix sdox ssx /f sync sckx spixsr bit 0 shift control edge select msten baud rate slave select sync control clock control transmit receive and frame note: access spixtxb and spixrxb fifos via spixbuf register. fifos share address spixbuf spixbuf generator pbclk2 write read spixtxb fifo spixrxb fifo refclko1 mclksel
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 316 ? 2015-2016 microchip technology inc. 19.1 spi control registers table 19-1: spi1 through spi6 register map virtual address (bf82_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 spi1con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> mclksel spife enhbuf 0000 15:0 on sidl dissdo mode32 mode16 smp cke ssen ckp msten dissdi stxisel<1:0> srxisel<1:0> 0000 1010 spi1stat 31:16 rxbufelm<4:0> txbufelm<4:0> 0000 15:0 frmerr spibusy spitur srmt spirov spirbe spitbe spitbf spirbf 0008 1020 spi1buf 31:16 data<31:0> 0000 15:0 0000 1030 spi1brg 31:16 0000 15:0 brg<12:0> 0000 1040 spi1con2 31:16 0000 15:0 spi sgnext frm erren spi roven spi turen ignrov igntur auden aud mono audmod<1:0> 0000 1200 spi2con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> mclksel spife enhbuf 0000 15:0 on sidl dissdo mode32 mode16 smp cke ssen ckp msten dissdi stxisel<1:0> srxisel<1:0> 0000 1210 spi2stat 31:16 rxbufelm<4:0> txbufelm<4:0> 0000 15:0 frmerr spibusy spitur srmt spirov spirbe spitbe spitbf spirbf 0008 1220 spi2buf 31:16 data<31:0> 0000 15:0 0000 1230 spi2brg 31:16 0000 15:0 brg<8:0> 0000 1240 spi2con2 31:16 0000 15:0 spi sgnext frm erren spi roven spi turen ignrov igntur auden aud mono audmod<1:0> 0000 1400 spi3con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> mclksel spife enhbuf 0000 15:0 on sidl dissdo mode32 mode16 smp cke ssen ckp msten dissdi stxisel<1:0> srxisel<1:0> 0000 1410 spi3stat 31:16 rxbufelm<4:0> txbufelm<4:0> 0000 15:0 frmerr spibusy spitur srmt spirov spirbe spitbe spitbf spirbf 0008 1420 spi3buf 31:16 data<31:0> 0000 15:0 0000 1430 spi3brg 31:16 0000 15:0 brg<8:0> 0000 1440 spi3con2 31:16 0000 15:0 spi sgnext frm erren spi roven spi turen ignrov igntur auden aud mono audmod<1:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table except spixbuf have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 317 pic32mz embedded connectivity with floating point unit (ef) family 1600 spi4con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> mclksel spife enhbuf 0000 15:0 on sidl dissdo mode32 mode16 smp cke ssen ckp msten dissdi stxisel<1:0> srxisel<1:0> 0000 1610 spi4stat 31:16 rxbufelm<4:0> txbufelm<4:0> 0000 15:0 frmerr spibusy spitur srmt spirov spirbe spitbe spitbf spirbf 0008 1620 spi4buf 31:16 data<31:0> 0000 15:0 0000 1630 spi4brg 31:16 0000 15:0 brg<8:0> 0000 1640 spi4con2 31:16 0000 15:0 spi sgnext frm erren spi roven spi turen ignrov igntur auden aud mono audmod<1:0> 0000 1800 spi5con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> mclksel spife enhbuf 0000 15:0 on sidl dissdo mode32 mode16 smp cke ssen ckp msten dissdi stxisel<1:0> srxisel<1:0> 0000 1810 spi5stat 31:16 rxbufelm<4:0> txbufelm<4:0> 0000 15:0 frmerr spibusy spitur srmt spirov spirbe spitbe spitbf spirbf 0008 1820 spi5buf 31:16 data<31:0> 0000 15:0 0000 1830 spi5brg 31:16 0000 15:0 brg<8:0> 0000 1840 spi5con2 31:16 0000 15:0 spi sgnext frm erren spi roven spi turen ignrov igntur auden aud mono audmod<1:0> 0000 1a00 spi6con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> mclksel spife enhbuf 0000 15:0 on sidl dissdo mode32 mode16 smp cke ssen ckp msten dissdi stxisel<1:0> srxisel<1:0> 0000 1a10 spi6stat 31:16 rxbufelm<4:0> txbufelm<4:0> 0000 15:0 frmerr spibusy spitur srmt spirov spirbe spitbe spitbf spirbf 0008 1a20 spi6buf 31:16 data<31:0> 0000 15:0 0000 1a30 spi6brg 31:16 0000 15:0 brg<8:0> 0000 1a40 spi6con2 31:16 0000 15:0 spi sgnext frm erren spi roven spi turen ignrov igntur auden aud mono audmod<1:0> 0000 table 19-1: spi1 through spi6 register map (continued) virtual address (bf82_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table except spixbuf have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 318 ? 2015-2016 microchip technology inc. register 19-1: spixcon: spi control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> 23:16 r/w-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 mclksel (1) spife enhbuf (1) 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 on sidl dissdo (4) mode32 mode16 smp cke (2) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen ckp (3) msten dissdi (4) stxisel<1:0> srxisel<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 frmen: framed spi support bit 1 = framed spi support is enabled (ssx pin used as fsync input/output) 0 = framed spi support is disabled bit 30 frmsync: frame sync pulse direction control on ssx pin bit (framed spi mode only) 1 = frame sync pulse input (slave mode) 0 = frame sync pulse output (master mode) bit 29 frmpol: frame sync polarity bit (framed spi mode only) 1 = frame pulse is active-high 0 = frame pulse is active-low bit 28 mssen: master mode slave select enable bit 1 = slave select spi support is enabled. the ss pin is automatically driven during transmission in ? master mode. polarity is determined by the frmpol bit. 0 = slave select spi support is disabled. bit 27 frmsypw: frame sync pulse width bit 1 = frame sync pulse is one character wide 0 = frame sync pulse is one clock wide bit 26-24 frmcnt<2:0>: frame sync pulse counter bits. controls the number of data characters transmitted per pulse. this bit is only valid in framed mode. 111 = reserved 110 = reserved 101 = generate a frame sync pulse on every 32 data characters 100 = generate a frame sync pulse on every 16 data characters 011 = generate a frame sync pulse on every 8 data characters 010 = generate a frame sync pulse on every 4 data characters 001 = generate a frame sync pulse on every 2 data characters 000 = generate a frame sync pulse on every data character bit 23 mclksel: master clock enable bit (1) 1 = refclko1 is used by the baud rate generator 0 = pbclk2 is used by the baud rate generator bit 22-18 unimplemented: read as 0 note 1: this bit can only be written when the on bit = 0 . refer to section 37.0 electrical characteristics for maximum clock frequency requirements. 2: this bit is not used in the framed spi mode. the user should program this bit to 0 for the framed spi mode (frmen = 1 ). 3: when auden = 1 , the spi/i 2 s module functions as if the ckp bit is equal to 1 , regardless of the actual value of the ckp bit. 4: this bit present for legacy compatibility and is superseded by pps functionality on these de vices (see section 12.4 peripheral pin select (pps) for more information).
? 2015-2016 microchip technology inc. ds60001320d-page 319 pic32mz embedded connectivity with floating point unit (ef) family bit 17 spife: frame sync pulse edge select bit (framed spi mode only) 1 = frame synchronization pulse coincides with the first bit clock 0 = frame synchronization pulse precedes the first bit clock bit 16 enhbuf: enhanced buffer enable bit (1) 1 = enhanced buffer mode is enabled 0 = enhanced buffer mode is disabled bit 15 on: spi/i 2 s module on bit 1 = spi/i 2 s module is enabled 0 = spi/i 2 s module is disabled bit 14 unimplemented: read as 0 bit 13 sidl: stop in idle mode bit 1 = discontinue operation when cpu enters in idle mode 0 = continue operation in idle mode bit 12 dissdo: disable sdox pin bit (4) 1 = sdox pin is not used by the module. pin is controlled by associated port register 0 = sdox pin is controlled by the module bit 11-10 mode<32,16>: 32/16-bit communication select bits when auden = 1 : mode32 mode16 communication 11 24-bit data, 32-bit fifo, 32-bit channel/64-bit frame 10 32-bit data, 32-bit fifo, 32-bit channel/64-bit frame 01 16-bit data, 16-bit fifo, 32-bit channel/64-bit frame 00 16-bit data, 16-bit fifo, 16-bit channel/32-bit frame when auden = 0 : mode32 mode16 communication 1x 32-bit 01 16-bit 00 8-bit bit 9 smp: spi data input sample phase bit master mode (msten = 1 ): 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time slave mode (msten = 0 ): smp value is ignored when spi is used in slave mode. the module always uses smp = 0 . bit 8 cke: spi clock edge select bit (2) 1 = serial output data changes on transition from active clock state to idle clock state (see ckp bit) 0 = serial output data changes on transition from idle clock state to active clock state (see ckp bit) bit 7 ssen: slave select enable (slave mode) bit 1 = ssx pin is used for slave mode 0 = ssx pin is not used for slave mode, pin is controlled by the port function. bit 6 ckp: clock polarity select bit (3) 1 = idle state for clock is a high level; active state is a low level 0 = idle state for clock is a low level; active state is a high level register 19-1: spixcon: spi co ntrol register (continued) note 1: this bit can only be written when the on bit = 0 . refer to section 37.0 electrical characteristics for maximum clock frequency requirements. 2: this bit is not used in the framed spi mode. the user should program this bit to 0 for the framed spi mode (frmen = 1 ). 3: when auden = 1 , the spi/i 2 s module functions as if the ckp bit is equal to 1 , regardless of the actual value of the ckp bit. 4: this bit present for legacy compatibility and is superseded by pps functionality on these de vices (see section 12.4 peripheral pin select (pps) for more information).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 320 ? 2015-2016 microchip technology inc. bit 5 msten: master mode enable bit 1 = master mode 0 =slave mode bit 4 dissdi: disable sdi bit (4) 1 = sdi pin is not used by the spi module (pin is controlled by port function) 0 = sdi pin is controlled by the spi module bit 3-2 stxisel<1:0>: spi transmit buffer empty interrupt mode bits 11 = interrupt is generated when the buffer is not full (has one or more empty elements) 10 = interrupt is generated when the buffer is empty by one-half or more 01 = interrupt is generated when the buffer is completely empty 00 = interrupt is generated when the last transfer is shifted out of spisr and transmit operations are ? complete bit 1-0 srxisel<1:0>: spi receive buffer full interrupt mode bits 11 = interrupt is generated when the buffer is full 10 = interrupt is generated when the buffer is full by one-half or more 01 = interrupt is generated when the buffer is not empty 00 = interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty) register 19-1: spixcon: spi co ntrol register (continued) note 1: this bit can only be written when the on bit = 0 . refer to section 37.0 electrical characteristics for maximum clock frequency requirements. 2: this bit is not used in the framed spi mode. the user should program this bit to 0 for the framed spi mode (frmen = 1 ). 3: when auden = 1 , the spi/i 2 s module functions as if the ckp bit is equal to 1 , regardless of the actual value of the ckp bit. 4: this bit present for legacy compatibility and is superseded by pps functionality on these de vices (see section 12.4 peripheral pin select (pps) for more information).
? 2015-2016 microchip technology inc. ds60001320d-page 321 pic32mz embedded connectivity with floating point unit (ef) family register 19-2: spixcon2: spi control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 spisgnext frmerren spiroven spituren ignrov igntur 7:0 r/w-0 u-0 u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 auden (1) audmono (1,2) audmod<1:0> (1,2) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 spisgnext: sign extend read data from the rx fifo bit 1 = data from rx fifo is sign extended 0 = data from rx fifo is not sign extended bit 14-13 unimplemented: read as 0 bit 12 frmerren: enable interrupt events via frmerr bit 1 = frame error overflow generates error events 0 = frame error does not generate error events bit 11 spiroven: enable interrupt events via spirov bit 1 = receive overflow generates error events 0 = receive overflow does not generate error events bit 10 spituren: enable interrupt events via spitur bit 1 = transmit underrun generates error events 0 = transmit underrun does not generates error events bit 9 ignrov: ignore receive overflow bit (for audio data transmissions) 1 = a rov is not a critical error; during rov data in the fifo is not overwritten by receive data 0 = a rov is a critical error which stop spi operation bit 8 igntur: ignore transmit underrun bit (for audio data transmissions) 1 = a tur is not a critical error and zeros are transmitted until the spixtxb is not empty 0 = a tur is a critical error which stop spi operation bit 7 auden: enable audio codec support bit (1) 1 = audio protocol is enabled 0 = audio protocol is disabled bit 6-5 unimplemented: read as 0 bit 3 audmono: transmit audio data format bit (1,2) 1 = audio data is mono (each data word is transmitted on both left and right channels) 0 = audio data is stereo bit 2 unimplemented: read as 0 bit 1-0 audmod<1:0>: audio protocol mode bit (1,2) 11 = pcm/dsp mode 10 = right justified mode 01 = left justified mode 00 = i 2 s mode note 1: this bit can only be written when the on bit = 0 . 2: this bit is only valid for auden = 1 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 322 ? 2015-2016 microchip technology inc. register 19-3: spixstat: spi status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 rxbufelm<4:0> 23:16 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 txbufelm<4:0> 15:8 u-0 u-0 u-0 r/c-0, hs r-0 u-0 u-0 r-0 frmerr spibusy spitur 7:0 r-0 r/w-0 r-0 u-0 r-1 u-0 r-0 r-0 srmt spirov spirbe spitbe spitbf spirbf legend: c = clearable bit hs = set in hardware r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28-24 rxbufelm<4:0>: receive buffer element count bits (valid only when enhbuf = 1 ) bit 23-21 unimplemented: read as 0 bit 20-16 txbufelm<4:0>: transmit buffer element count bits (valid only when enhbuf = 1 ) bit 15-13 unimplemented: read as 0 bit 12 frmerr: spi frame error status bit 1 = frame error is detected 0 = no frame error is detected this bit is only valid when frmen = 1 . bit 11 spibusy: spi activity status bit 1 = spi peripheral is currently busy with some transactions 0 = spi peripheral is currently idle bit 10-9 unimplemented: read as 0 bit 8 spitur: transmit under run bit 1 = transmit buffer has encountered an underrun condition 0 = transmit buffer has no underrun condition this bit is only valid in framed sync mode; the underrun condition must be cleared by disabling/re-enabling the module. bit 7 srmt: shift register empty bit (valid only when enhbuf = 1 ) 1 = when spi module shift register is empty 0 = when spi module shift register is not empty bit 6 spirov: receive overflow flag bit 1 = a new data is completely received and discarded. the user software has not read the previous d ata in the spixbuf register. 0 = no overflow has occurred this bit is set in hardware; can only be cleared (= 0 ) in software. bit 5 spirbe: rx fifo empty bit (valid only when enhbuf = 1 ) 1 = rx fifo is empty (crptr = swptr) 0 = rx fifo is not empty (crptr ? ? swptr) bit 4 unimplemented: read as 0
? 2015-2016 microchip technology inc. ds60001320d-page 323 pic32mz embedded connectivity with floating point unit (ef) family bit 3 spitbe: spi transmit buffer empty status bit 1 = transmit buffer, spixtxb is empty 0 = transmit buffer, spixtxb is not empty automatically set in hardware when spi transfers data from spixtxb to spixsr. automatically cleared in hardware when spixbuf is written to, loading spixtxb. bit 2 unimplemented: read as 0 bit 1 spitbf: spi transmit buffer full status bit 1 = transmit is not yet started, spitxb is full 0 = transmit buffer is not full standard buffer mode: automatically set in hardware when the core writes to the spibuf location, loading spitxb. automatically cleared in hardware when the spi module transfers data from spitxb to spisr. enhanced buffer mode: set when cwptr + 1 = srptr; cleared otherwise bit 0 spirbf: spi receive buffer full status bit 1 = receive buffer, spixrxb is full 0 = receive buffer, spixrxb is not full standard buffer mode: automatically set in hardware when the spi module transfers data from spixsr to spixrxb. automatically cleared in hardware when spixbuf is read from, reading spixrxb. enhanced buffer mode: set when swptr + 1 = crptr; cleared otherwise register 19-3: spixstat: spi status register
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 324 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 325 pic32mz embedded connectivity with floating point unit (ef) family 20.0 serial quad interface (sqi) the sqi module is a synchronous serial interface that provides access to serial flash memories and other serial devices. the sqi module supports single lane (identical to spi), dual lane, and quad lane modes. the following are key feature of the sqi module: supports single, dual, and quad lane modes supports single data rate (sdr) mode programmable command sequence execute-in-place (xip) data transfer: - programmed i/o mode (pio) - buffer descriptor dma supports spi mode 0 and mode 3 programmable clock polarity (cpol) and clock phase (cpha) bits supports up to two chip selects supports up to four bytes of flash address programmable interrupt thresholds 32-byte transmit data buffer 32-byte receive data buffer 4-word controller buffer figure 20-1: sq i module block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 46. serial quad interface (sqi) (ds60001244) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). note: once the sqi module is configured, external devices are memory mapped into kseg2 and kseg3 (see figure 4-1 through figure 4-4 in section 4.0 memory organization for more information). the mmu must be enabled and the tlb must be set up to access this memory (refer to section 50. cpu for devices with mips32 ? microaptiv? and m-class cores (ds60001192) of the ?pic32 family reference manual? for more information). transmit buffer sqi master interface control and status registers (pio) system bus receive buffer dma bus slave bus master control buffer note 1: when configuring the refclko2 clock source, a value of 0 for the rotrim<8:0> bits must be selected. 2: this clock source is only used for sqi special function register (sfr) access. pbclk5 (2) refclko2 (1) (t bc ) sqid0 sqid1 sqid2 sqid3 sqiclk sqics0 sqics1
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 326 ? 2015-2016 microchip technology inc. 20.1 sqi control registers table 20-1: serial quadrature interface (sqi) register map virtual address (bf8e_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 sqi1 xcon1 31:16 dummybytes<2:0> addrbytes<2:0> readopcode<7:6> 0000 15:0 readopcode<5:0> typedata<1:0> typedummy<1:0> typemode<1:0> typeaddr<1:0> typecmd<1:0> 0000 2004 sqi1 xcon2 31:16 0000 15:0 devsel<1:0> modebytes<1:0> modecode<7:0> 0000 2008 sqi1cfg 31:16 csen<1:0> sqien dataen<1:0> con fiforst rxfifo rst txfifo rst reset 0000 15:0 bursten hold wp lsbf cpol cpha mode<2:0> 0000 200c sqi1con 31:16 scheck dassert devsel<1:0> lanemode<1:0> cmdinit<1:0> 0000 15:0 txrxcount<15:0> 0000 2010 sqi1 clkcon 31:16 clkdiv<10:8> 0000 15:0 clkdiv<7:0> stable en 0000 2014 sqi1 cmdthr 31:16 0000 15:0 txcmdthr<4:0> rxcmdthr<4:0> 0000 2018 sqi1 intthr 31:16 0000 15:0 txintthr<4:0> rxintthr<4:0> 0000 201c sqi1 inten 31:16 0000 15:0 dmaeie pkt compie bd doneie con thrie con emptyie con fullie rx thrie rx fullie rx emptyie tx thrie tx fullie tx emptyie 0000 2020 sqi1 intstat 31:16 0000 15:0 dmaeif pkt compif bd doneif con thrif con emptyif con fullif rx thrif rx fullif rx emptyif tx thrif tx fullif tx emptyif 0000 2024 sqi1 txdata 31:16 txdata<31:16> 0000 15:0 txdata<15:0> 0000 2028 sqi1 rxdata 31:16 rxdata<31:16> 0000 15:0 rxdata<15:0> 0000 202c sqi1 stat1 31:16 txfifofree<7:0> 0000 15:0 rxfifocnt<7:0> 0000 2030 sqi1 stat2 31:16 cmdstat<1:0> 0000 15:0 conavail<4:0> sdid3 sdid2 sdid1 sdid0 rxun txov 00x0 2034 sqi1 bdcon 31:16 0000 15:0 start pollen dmaen 0000 2038 sqi1bd curadd 31:16 bdcurraddr<31:16> 0000 15:0 bdcurraddr<15:0> 0000 2040 sqi1bd baseadd 31:16 bdaddr<31:16> 0000 15:0 bdaddr<15:0> 0000
? 2015-2016 microchip technology inc. ds60001320d-page 327 pic32mz embedded connectivity with floating point unit (ef) family 2044 sqi1bd stat 31:16 bdstate<3:0> dma start dmaactv 0000 15:0 bdcon<15:0> 0000 2048 sqi1bd pollcon 31:16 0000 15:0 pollcon<15:0> 0000 204c sqi1bd txdstat 31:16 txstate<3:0> txbufcnt<4:0> 0000 15:0 txcurbuflen<7:0> 0000 2050 sqi1bd rxdstat 31:16 rxstate<3:0> rxbufcnt<4:0> 0000 15:0 rxcurbuflen<7:0> 0000 2054 sqi1thr 31:16 0000 15:0 thres<4:0> 0000 2058 sqi1int sigen 31:16 0000 15:0 dmaeise pkt doneise bd doneise con thrise con emptyise con fullise rx thrise rx fullise rx emptyise tx thrise tx fullise tx emptyise 0000 205c sqi1 tapcon 31:16 0000 15:0 clkindly<5:0> dataoutdly<3:0> clkoutdly<3:0> 0000 2060 sqi1 memstat 31:16 statpos typestat<1:0> statbytes<1:0> 0000 15:0 statdata<15:0> 0000 2064 sqi1 xcon3 31:16 init1 scheck init1count<1:0> init1type<1:0> init1cmd3<7:0> 0000 15:0 init1cmd2<7:0> init1cmd1<7:0> 0000 2068 sqi1 xcon4 31:16 init2 scheck init2count<1:0> init2type<1:0> init2cmd3<7:0> 0000 15:0 init2cmd2<7:0> init2cmd1<7:0> 0000 table 20-1: serial quadrature interface (sqi) register map (continued) virtual address (bf8e_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 328 ? 2015-2016 microchip technology inc. register 20-1: sqi1xcon1: sqi xip control register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dummybytes<2:0> addrbytes<2:0> readopcode<7:6> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 readopcode<5:0> typedata<1:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 typedummy<1:0> typemode<1:0> typeaddr<1:0> typecmd<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as 0 bit 23-21 dummybytes<2:0>: transmit dummy bytes bits 111 = transmit seven dummy bytes after the address bytes 011 = transmit three dummy bytes after the address bytes 010 = transmit two dummy bytes after the address bytes 001 = transmit one dummy bytes after the address bytes 000 = transmit zero dummy bytes after the address bytes bit 20-18 addrbytes<2:0>: address cycle bits 111 = reserved 101 = reserved 100 = four address bytes 011 = three address bytes 010 = two address bytes 001 = one address bytes 000 = zero address bytes bit 17-10 readopcode<7:0>: op code value for read operation bits these bits contain the 8-bit op code value for read operation. bit 9-8 typedata<1:0>: sqi type data enable bits the boot controller will receive the data in single lane, dual lane, or quad lane. 11 = reserved 10 = quad lane mode data is enabled 01 = dual lane mode data is enabled 00 = single lane mode data is enabled bit 7-6 typedummy<1:0>: sqi type dummy enable bits the boot controller will send the dummy in single lane, dual lane, or quad lane. 11 = reserved 10 = quad lane mode dummy is enabled 01 = dual lane mode dummy is enabled 00 = single lane mode dummy is enabled
? 2015-2016 microchip technology inc. ds60001320d-page 329 pic32mz embedded connectivity with floating point unit (ef) family bit 5-4 typemode<1:0>: sqi type mode enable bits the boot controller will send the mode in single lane, dual lane, or quad lane. 11 = reserved 10 = quad lane mode is enabled 01 = dual lane mode is enabled 00 = single lane mode is enabled bit 3-2 typeaddr<1:0>: sqi type address enable bits the boot controller will send the address in single lane, dual lane, or quad lane. 11 = reserved 10 = quad lane mode address is enabled 01 = dual lane mode address is enabled 00 = single lane mode address is enabled bit 1-0 typecmd<1:0>: sqi type command enable bits the boot controller will send the command in single lane, dual lane, or quad lane. 11 = reserved 10 = quad lane mode command is enabled 01 = dual lane mode command is enabled 00 = single lane mode command is enabled register 20-1: sqi1xcon1: sqi xip control register 1 (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 330 ? 2015-2016 microchip technology inc. register 20-2: sqi1xcon2: sqi xip control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 devsel<1:0> modebytes<1:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 modecode<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-12 unimplemented: read as 0 bit 11-10 devsel<1:0>: device select bits 11 = reserved 10 = reserved 01 = device 1 is selected 00 = device 0 is selected bit 9-8 modebytes<1:0>: mode byte cycle enable bits 11 = three cycles 10 = two cycles 01 = one cycle 00 = zero cycles bit 7-0 modecode<7:0>: mode code value bits these bits contain the 8-bit code value for the mode bits.
? 2015-2016 microchip technology inc. ds60001320d-page 331 pic32mz embedded connectivity with floating point unit (ef) family register 20-3: sqi1cfg: sq i configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 csen<1:0> 23:16 r/w-0 u-0 r/w-0 r/w-0 r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc sqien dataen<1:0> con fiforst rx fiforst tx fiforst reset 15:8 u-0 r-0 r-0 r/w-0 r-0 r/w-0 r/w-0 u-0 bursten (1) h o l dw p 7:0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lsbf cpol cpha mode<2:0> legend: hc = hardware cleared r = reserved r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-26 unimplemented: read as 0 bit 25-24 csen<1:0>: chip select output enable bits 11 = chip select 0 and chip select 1 are used 10 = chip select 1 is used (chip select 0 is not used) 01 = chip select 0 is used (chip select 1 is not used) 00 = chip select 0 and chip select 1 are not used bit 23 sqien: sqi enable bit 1 = sqi module is enabled 0 = sqi module is disabled bit 22 unimplemented: read as 0 bit 21-20 dataen<1:0>: data output enable bits 11 = reserved 10 = sqid3-sqid0 outputs are enabled 01 = sqid1 and sqid0 data outputs are enabled 00 = sqid0 data output is enabled bit 19 confiforst: control fifo reset bit 1 = a reset pulse is generated clearing the control fifo 0 = a reset pulse is not generated bit 18 rxfiforst: receive fifo reset bit 1 = a reset pulse is generated clearing the receive fifo 0 = a reset pulse is not generated bit 17 txfiforst: transmit fifo reset bit 1 = a reset pulse is generated clearing the transmit fifo 0 = a reset pulse is not generated bit 16 reset: software reset select bit this bit is automatically cleared by the sqi module. all of the internal state machines and fifo pointers are reset by this reset pulse. 1 = a reset pulse is generated 0 = a reset pulse is not generated bit 15 unimplemented: read as 0 bit 14-13 reserved: must be programmed as 0 note 1: this bit must be programmed as 1 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 332 ? 2015-2016 microchip technology inc. bit 12 bursten: burst configuration bit (1) 1 = burst is enabled 0 = burst is not enabled bit 11 reserved: must be programmed as 0 bit 10 hold: hold bit in single lane or dual lane mode, this bit is used to drive the sqid3 pin, which can be used for devices with a hold input pin. the meaning of the values for this bit will depend on the device to which sqid3 is connected. bit 9 wp: write protect bit in single lane or dual lane mode, this bit is used to drive the sqid2 pin, which can be used with devices with a write-protect pin. the meaning of the values for this bit will dep end on the device to which sqid2 is connected. bit 8-6 unimplemented: read as 0 bit 5 lsbf: data format select bit 1 = lsb is sent or received first 0 = msb is sent or received first bit 4 cpol: clock polarity select bit 1 = active-low sqiclk (sqiclk high is the idle state) 0 = active-high sqiclk (sqiclk low is the idle state) bit 3 cpha: clock phase select bit 1 = sqiclk starts toggling at the start of the first data bit 0 = sqiclk starts toggling at the middle of the first data bit bit 2-0 mode<2:0>: mode select bits 111 = reserved 100 = reserved 011 = xip mode is selected (when this mode is entered, the module behaves as if executing in place (xip), but uses the register data to control timing) 010 = dma mode is selected 001 = cpu mode is selected (the module is controlled by the cpu in pio mode. this mode is entered when leaving boot or xip mode) 000 = reserved register 20-3: sqi1cfg: sqi conf iguration register (continued) note 1: this bit must be programmed as 1 .
? 2015-2016 microchip technology inc. ds60001320d-page 333 pic32mz embedded connectivity with floating point unit (ef) family register 20-4: sqi1con: sqi control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 r-0 r/w-0 scheck 23:16 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dassert devsel<1:0> lanemode<1:0> cmdinit<1:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txrxcount<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txrxcount<7:0> legend: r = reserved r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-26 unimplemented: read as 0 bit 25 reserved: must be programmed as 0 bit 24 scheck: flash status check bit 1 = check the status of the flash 0 = do not check the status of the flash bit 23 unimplemented: read as 0 bit 22 dassert: chip select assert bit 1 = chip select is deasserted after transmission or reception of the specified number of bytes 0 = chip select is not deasserted after transmission or reception of the specified number of bytes bit 21-20 devsel<1:0>: sqi device select bits 11 = reserved 10 = reserved 01 = select device 1 00 = select device 0 bit 19-18 lanemode<1:0>: sqi lane mode select bits 11 = reserved 10 = quad lane mode 01 = dual lane mode 00 = single lane mode bit 17-16 cmdinit<1:0>: command initiation mode select bits if it is transmit, commands are initiated based on a write to the transmit register or the contents of tx fifo. if cmdinit is receive, commands are initiated based on reads to the read register or rx fifo availability. 11 = reserved 10 = receive 01 = transmit 00 = idle bit 15-0 txrxcount<15:0>: transmit/receive count bits these bits specify the total number of bytes to transmit or receive (based on cmdinit).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 334 ? 2015-2016 microchip technology inc. register 20-5: sqi1 clkcon: sqi clock control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 c l k d i v < 1 0 : 8 > (1) 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 clkdiv<7:0> (1) 7:0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 r/w-0 stable en legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-19 unimplemented: read as 0 bit 18-8 clkdiv<10:0>: sqi clock t sqi frequency select bit (1) 10000000000 = base clock t bc is divided by 2048 01000000000 = base clock t bc is divided by 1024 00100000000 = base clock t bc is divided by 512 00010000000 = base clock t bc is divided by 256 00001000000 = base clock t bc is divided by 128 00000100000 = base clock t bc is divided by 64 00000010000 = base clock t bc is divided by 32 00000001000 = base clock t bc is divided by 16 00000000100 = base clock t bc is divided by 8 00000000010 = base clock t bc is divided by 4 00000000001 = base clock t bc is divided by 2 00000000000 = base clock t bc setting these bits to 00000000000 specifies the highest frequency of the sqi clock. bit 7-2 unimplemented: read as 0 bit 1 stable: t sqi clock stable select bit this bit is set to 1 when the sqi clock, t sqi , is stable after writing a 1 to the en bit. 1 = t sqi clock is stable 0 = t sqi clock is not stable bit 0 en: t sqi clock enable select bit when clock oscillation is stable, the sqi module will set the stable bit to 1 . 1 = enable the sqi clock (t sqi ) (when clock oscillation is stable, the sqi module sets the stable bit to 1 ) 0 = disable the sqi clock (t sqi ) (the sqi module should stop its clock to enter a low power state); sfrs can still be accessed, as they use pbclk5 note 1: refer to table 37-34 in 37.0 electrical characteristics for the maximum clock frequency specifications.
? 2015-2016 microchip technology inc. ds60001320d-page 335 pic32mz embedded connectivity with floating point unit (ef) family register 20-6: sqi1cmdthr: sq i command threshold register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txcmdthr<4:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxcmdthr<4:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as 0 bit 12-8 txcmdthr<4:0>: transmit command threshold bits in transmit initiation mode, the sqi module performs a transmit operation when transmit command threshold bytes are present in the tx fifo. these bits should usually be set to 1 for normal flash commands, and set to a higher value for page programming. for 16-bit mode, the value should be a multiple of 2. bit 7-5 unimplemented: read as 0 bit 4-0 rxcmdthr<4:0>: receive command threshold bits (1) in receive initiation mode, the sqi module attempts to perform receive operations to fetch the receive com- mand threshold number of bytes in the receive buffer. if space for these bytes is not present in the fifo, the sqi will not initiate a transfer. for 16-bit mode, the value should be a multiple of 2. if software performs any reads, thereby reducing the fifo count, hardware would initiate a receive transfer to make the fifo count equal to the value in these bits. if software would not like any more words latched into the fifo, command initiation mode needs to be changed to idle before any fifo reads by software. in the case of boot/xip mode, the sqi module will use the system bus burst size, instead of the receive command threshold value. note 1: these bits should only be programmed when a receive is not active (i.e., during idle mode or a transmit).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 336 ? 2015-2016 microchip technology inc. register 20-7: sqi1intthr: sqi interrupt threshold register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t x i n t t h r < 4 : 0 > 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxintthr<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as 0 bit 12-8 txintthr<4:0>: transmit interrupt threshold bits a transmit interrupt is set when the transmit fifo has more space than the set number of bytes. for 16-bit mode, the value should be a multiple of 2. bit 7-5 unimplemented: read as 0 bit 4-0 rxintthr<4:0>: receive interrupt threshold bits a receive interrupt is set when the receive fifo count is larger than or equal to the set number of bytes. for 16-bit mode, the value should be multiple of 2.
? 2015-2016 microchip technology inc. ds60001320d-page 337 pic32mz embedded connectivity with floating point unit (ef) family register 20-8: sqi1inten: sqi interrupt enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 dmaeie pktcompie bddoneie conthrie 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 conemptyie confullie rxthrie rxfullie rxemptyie txthrie txfullie txemptyie legend: hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-12 unimplemented: read as 0 bit 11 dmaeie: dma bus error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 10 pktcompie: dma buffer descriptor packet complete interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 9 bddoneie: dma buffer descriptor done interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 8 conthrie: control buffer threshold interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 7 conemptyie: control buffer empty interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 6 confullie: control buffer full interrupt enable bit this bit enables an interrupt when the receive fifo buffer is full. 1 = interrupt is enabled 0 = interrupt is disabled bit 5 rxthrie: receive buffer threshold interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 4 rxfullie: receive buffer full interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 3 rxemptyie: receive buffer empty interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 2 txthrie: transmit threshold interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 1 txfullie: transmit buffer full interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 0 txemptyie: transmit buffer empty interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 338 ? 2015-2016 microchip technology inc. register 20-9: sqi1intstat: sq i interrupt status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 r/w-0, hs r/w- 0, hs r/w-0, hs r/w-0, hs dma eif pkt compif bd doneif con thrif 7:0 r/w-1, hs r/w-0, hs r/w-1, hs r/w-0, hs r/w-1, hs r/w-1, hs r/w-0, hs r/w-1, hs con emptyif con fullif rxthrif (1) rxfullif rx emptyif txthrif txfullif tx emptyif legend: hs = hardware set r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-12 unimplemented: read as 0 bit 11 dmaeif: dma bus error interrupt flag bit 1 = dma bus error has occurred 0 = dma bus error has not occurred bit 10 pktcompif: dma buffer descriptor processor packet completion interrupt flag bit 1 = dma bd packet is complete 0 = dma bd packet is in progress bit 9 bddoneif: dma buffer descriptor done interrupt flag bit 1 = dma bd process is done 0 = dma bd process is in progress bit 8 conthrif: control buffer threshold interrupt flag bit 1 = the control buffer has more than thres words of space available 0 = the control buffer has less than thres words of space available bit 7 conemptyif: control buffer empty interrupt flag bit 1 = control buffer is empty 0 = control buffer is not empty bit 6 confullif: control buffer full interrupt flag bit 1 = control buffer is full 0 = control buffer is not full bit 5 rxthrif: receive buffer threshold interrupt flag bit (1) 1 = receive buffer has more than rxintthr words of space available 0 = receive buffer has less than rxintthr words of space available bit 4 rxfullif: receive buffer full interrupt flag bit 1 = receive buffer is full 0 = receive buffer is not full bit 3 rxemptyif: receive buffer empty interrupt flag bit 1 = receive buffer is empty 0 = receive buffer is not empty note 1: in boot/xip mode, the por value of the receive buffer threshold is zero. therefore, this bit will be set to a 1 , immediately after a por until a read request on the system bus is received. note: the bits in the register are cleared by writing a ' 1 ' to the corresponding bit position.
? 2015-2016 microchip technology inc. ds60001320d-page 339 pic32mz embedded connectivity with floating point unit (ef) family bit 2 txthrif: transmit buffer threshold interrupt flag bit 1 = transmit buffer has more than txintthr words of space available 0 = transmit buffer has less than txintthr words of space available bit 1 txfullif: transmit buffer full interrupt flag bit 1 = the transmit buffer is full 0 = the transmit buffer is not full bit 0 txemptyif: transmit buffer empty interrupt flag bit 1 = the transmit buffer is empty 0 = the transmit buffer has content register 20-9: sqi1intstat: sqi inte rrupt status register (continued) note 1: in boot/xip mode, the por value of the receive buffer threshold is zero. therefore, this bit will be set to a 1 , immediately after a por until a read request on the system bus is received. note: the bits in the register are cleared by writing a ' 1 ' to the corresponding bit position.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 340 ? 2015-2016 microchip technology inc. register 20-10: sqi1txdata: sqi transmit data buffer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txdata<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txdata<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txdata<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txdata<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 txdata<31:0>: transmit command data bits data is loaded into this register before being transmitted. prior to the data transfer, the data in txdata is loaded into the shift register (sfdr). multiple writes to txdata can occur while a transfer is in progress. there can be a maximum of eight commands that can be queued. register 20-11: sqi1rxdata: sqi receive data buffer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxdata<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxdata<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxdata<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxdata<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 rxdata<31:0>: receive data buffer bits at the end of a data transfer, the data in the shift register is loaded into the rxdata register. this register works like a fifo. the depth of the receive buffer is eight words.
? 2015-2016 microchip technology inc. ds60001320d-page 341 pic32mz embedded connectivity with floating point unit (ef) family register 20-12: sqi1stat1: sqi status register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 txfifofree<7:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxfifocnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as 0 bit 23-16 txfifofree<7:0>: transmit fifo available word space bits bit 15-8 unimplemented: read as 0 bit 7-0 rxfifocnt<7:0>: number of words of read data in the fifo
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 342 ? 2015-2016 microchip technology inc. register 20-13: sqi1stat2: sqi status register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 r-0 r-0 c m d s t a t < 1 : 0 > 15:8 u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 conavail<4:1> 7:0 r-0 r-0 r-0 r-0 r-0 u-0 r-0 r-0 conavail<0> sqid3 sqid2 sqid1 sqid0 rxun txov legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-18 unimplemented: read as 0 bit 17-16 cmdstat<1:0>: current command status bits these bits indicate the current command status. 11 = reserved 10 = receive 01 = transmit 00 = idle bit 15-12 unimplemented: read as 0 bit 11-7 conavail<4:0>: control fifo space available bits these bits indicate the available control word space. 11111 = 32 bytes are available 11110 = 31 bytes are available 00001 = 1 byte is available 00000 = no bytes are available bit 6 sqid3: sqid3 status bit 1 = data is present on sqid3 0 = data is not present on sqid3 bit 5 sqid2: sqid2 status bit 1 = data is present on sqid2 0 = data is not present on sqid2 bit 4 sqid1: sqid1 status bit 1 = data is present on sqid1 0 = data is not present on sqid1 bit 3 sqid0: sqid0 status bit 1 = data is present on sqid0 0 = data is not present on sqid0 bit 2 unimplemented: read as 0 bit 1 rxun: receive fifo underflow status bit 1 = receive fifo underflow has occurred 0 = receive fifo underflow has not occurred bit 0 txov: transmit fifo overflow status bit 1 = transmit fifo overflow has occurred 0 = transmit fifo overflow has not occurred
? 2015-2016 microchip technology inc. ds60001320d-page 343 pic32mz embedded connectivity with floating point unit (ef) family register 20-14: sqi1bdcon: sqi buffe r descriptor control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 start pollen dmaen legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-3 unimplemented: read as 0 bit 2 start: buffer descriptor processor start bit 1 = start the buffer descriptor processor 0 = disable the buffer descriptor processor bit 1 pollen: buffer descriptor poll enable bit 1 = bdp poll is enabled 0 = bdp poll is not enabled bit 0 dmaen: dma enable bit 1 = dma is enabled 0 = dma is disabled register 20-15: sqi1bdcuradd: sqi buffer descriptor current address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bdcurraddr<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bdcurraddr<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bdcurraddr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bdcurraddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 bdcurraddr<31:0>: current buffer descriptor address bits these bits contain the address of the current descriptor being processed by the buffer descriptor processor.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 344 ? 2015-2016 microchip technology inc. register 20-16: sqi1bdbaseadd: sqi buffer descriptor base address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 bdaddr<31:0>: dma base address bits these bits contain the physical address of the root buffer descriptor. this register should be updated only when the dma is idle. register 20-17: sqi1bdstat: sqi bu ffer descriptor status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 r-x r-x r-x r-x r-x r-x bdstate<3:0> dmastart dmaactv 15:8 r-x r-x r-x r-x r-x r-x r-x r-x bdcon<15:8> 7:0 r-x r-x r-x r-x r-x r-x r-x r-x bdcon<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-22 unimplemented: read as 0 bit 21-18 bdstate<3:0>: dma buffer descriptor processor state status bits these bits return the current state of the buffer descriptor processor: 5 = fetched buffer descriptor is disabled 4 = descriptor is done 3 = data phase 2 = buffer descriptor is loading 1 = descriptor fetch request is pending 0 = idle bit 17 dmastart: dma buffer descriptor processor start status bit 1 = dma has started 0 = dma has not started bit 16 dmaactv: dma buffer descriptor processor active status bit 1 = buffer descriptor processor is active 0 = buffer descriptor processor is idle bit 15-0 bdcon<15:0>: dma buffer descriptor control word bits these bits contain the current buffer descriptor control word.
? 2015-2016 microchip technology inc. ds60001320d-page 345 pic32mz embedded connectivity with floating point unit (ef) family register 20-18: sqi1bdpollcon: sqi buffe r descriptor poll control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pollcon<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pollcon<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 pollcon<15:0>: buffer descriptor processor poll status bits these bits indicate the number of cycles the bdp would wait before refetching the descriptor control word if the previous descriptor fetched was disabled. register 20-19: sqi1bdtxdstat: sqi buffer descriptor dma transmit status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r-x r-x r-x r-x u-0 txstate<3:0> 23:16 u-0 u-0 u-0 r-x r-x r-x r-x r-x txbufcnt<4:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r-x r-x r-x r-x r-x r-x r-x r-x txcurbuflen<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28-25 txstate<3:0>: current dma transmit state status bits these bits provide information on the current dma receive states. bit 24-21 unimplemented: read as 0 bit 20-16 txbufcnt<4:0>: dma buffer byte count status bits these bits provide information on the internal fifo space. bit 15-8 unimplemented: read as 0 bit 7-0 txcurbuflen<7:0>: current dma transmit buffer length status bits these bits provide the length of the current dma transmit buffer.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 346 ? 2015-2016 microchip technology inc. register 20-20: sqi1bdrxdstat: sqi buffer descriptor dma receive status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r-x r-x r-x r-x u-0 rxstate<3:0> 23:16 u-0 u-0 u-0 r-x r-x r-x r-x r-x rxbufcnt<4:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r-x r-x r-x r-x r-x r-x r-x r-x rxcurbuflen<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28-25 rxstate<3:0>: current dma receive state status bits these bits provide information on the current dma receive states. bit 24-21 unimplemented: read as 0 bit 20-16 rxbufcnt<4:0>: dma buffer byte count status bits these bits provide information on the internal fifo space. bit 15-8 unimplemented: read as 0 bit 7-0 rxcurbuflen<7:0>: current dma receive buffer length status bits these bits provide the length of the current dma receive buffer. register 20-21: sqi1thr: sqi threshold control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 thres<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-5 unimplemented: read as 0 bit 4-0 thres<4:0>: sqi control threshold value bits the sqi control threshold interrupt is asserted when the amount of space indicated by thres<4:0> is available in the sqi control buffer.
? 2015-2016 microchip technology inc. ds60001320d-page 347 pic32mz embedded connectivity with floating point unit (ef) family register 20-22: sqi1intsigen: sqi interrupt signal enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 d m a e i s e pkt doneise bd doneise con thrise 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 con emptyise con fullise rx thrise rx fullise rx emptyise tx thrise tx fullise tx emptyise legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-12 unimplemented: read as 0 bit 11 dmaeise: dma bus error interrupt signal enable bit 1 = interrupt signal is enabled 0 = interrupt signal is disabled bit 10 pktdoneise: receive error interrupt signal enable bit 1 = interrupt signal is enabled 0 = interrupt signal is disabled bit 9 bddoneise: transmit error interrupt signal enable bit 1 = interrupt signal is enabled 0 = interrupt signal is disabled bit 8 conthrise: control buffer threshold interrupt signal enable bit 1 = interrupt signal is enabled 0 = interrupt signal is disabled bit 7 conemptyise: control buffer empty interrupt signal enable bit 1 = interrupt signal is enabled 0 = interrupt signal is disabled bit 6 confullise: control buffer full interrupt signal enable bit 1 = interrupt signal is enabled 0 = interrupt signal is disabled bit 5 rxthrise: receive buffer threshold interrupt signal enable bit 1 = interrupt signal is enabled 0 = interrupt signal is disabled bit 4 rxfullise: receive buffer full interrupt signal enable bit 1 = interrupt signal is enabled 0 = interrupt signal is disabled bit 3 rxemptyise: receive buffer empty interrupt signal enable bit 1 = interrupt signal is enabled 0 = interrupt signal is disabled bit 2 txthrise: transmit buffer threshold interrupt signal enable bit 1 = interrupt signal is enabled 0 = interrupt signal is disabled bit 1 txfullise: transmit buffer full interrupt signal enable bit 1 = interrupt signal is enabled 0 = interrupt signal is disabled bit 0 txemptyise: transmit buffer empty interrupt signal enable bit 1 = interrupt signal is enabled 0 = interrupt signal is disabled
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 348 ? 2015-2016 microchip technology inc. register 20-23: sqi1tapcon: sqi tap control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 clkindly<5:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dataoutdly<3:0> clkoutdly<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-14 unimplemented: read as 0 bit 13-8 clkindly<5:0>: sqi clock input delay bits these bits are used to add fractional delays to sqi clock input while sampling the incoming data. 111111 = 64 taps added on clock input 111110 = 63 taps added on clock input 000001 = 2 taps added on clock input 000000 = 1 tap added on clock input bit 7-4 dataoutdly<3:0>: sqi data output delay bits these bits are used to add fractional delays to sqi data output while writing the data to the flash. 1111 = 16 taps added on clock output 1110 = 15 taps added on clock output 0001 = 2 taps added on clock output 0000 = 1 tap added on clock output bit 3-0 clkoutdly<3:0>: sqi clock output delay bits these bits are used to add fractional delays to sqi clock output while writing the data to the flash. 1111 = 16 taps added on clock output 1110 = 15 taps added on clock output 0001 = 2 taps added on clock output 0000 = 1 tap added on clock output
? 2015-2016 microchip technology inc. ds60001320d-page 349 pic32mz embedded connectivity with floating point unit (ef) family register 20-24: sqi1memstat: sqi memory status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 statpos stattype<1:0> statbytes<1:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 statdata<7:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 statcmd<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-21 unimplemented: read as 0 bit 20 statpos: status bit position in flash bit indicates the busy bit position in the flash status register. this bit is added to support all flash types (with busy bit at 0 and at 7). 1 = busy bit position is bit 7 in status register 0 = busy bit position is bit 0 in status register bit 19-18 stattype<1:0>: status command/read lane mode bits 11 = reserved 10 = status command and read are executed in quad lane mode 01 = status command and read are executed in dual lane mode 00 = status command and read are executed in single lane mode bit 17-16 statbytes<1:0>: number of status bytes bits 11 = reserved 10 = status command/read is 2 bytes long 01 = status command/read is 1 byte long 00 = reserved bit 15-8 statdata<7:0>: status data bits these bits contain the status value of the flash device bit 7-0 statcmd<7:0>: status command bits the status check command is written into these bits
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 350 ? 2015-2016 microchip technology inc. register 20-25: sqi1xcon3: sqi xip control register 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 init1scheck init1count<1:0> init1type<1:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 init1cmd3<7:0> (1) 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 init1cmd2<7:0> (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 init1cmd1<7:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28 init1scheck: flash initialization 1 command status check bit 1 = check the status after executing the init1 command 0 = do not check the status bit 27-26 init1count<1:0>: flash initialization 1 command count bits 11 = init1cmd1, init1cmd2, and init1cmd3 are sent 10 = init1cmd1 and init1cmd2 are sent, but init1cmd3 is still pending 01 = init1cmd1 is sent, but init1cmd2 and init1cmd3 are still pending 00 = no commands are sent bit 25-24 init1type<1:0>: flash initialization 1 command type bits 11 = reserved 10 = init1 commands are sent in quad lane mode 01 = init1 commands are sent in dual lane mode 00 = init1 commands are sent in single lane mode bit 24-16 init1cmd3<7:0>: flash initialization command 3 bits (1) third command of the flash initialization. bit 15-8 init1cmd2<7:0>: flash initialization command 2 bits (1) second command of the flash initialization. bit 7-0 init1cmd1<7:0>: flash initialization command 1 bits (1) first command of the flash initialization. note 1: init1cmd1 can be wen and init1cmd2 can be sector unprotect. note: some flash devices require write enable and sector unprotect commands before read/write operations and this register is useful in working with those flash types (xip mode only)
? 2015-2016 microchip technology inc. ds60001320d-page 351 pic32mz embedded connectivity with floating point unit (ef) family register 20-26: sqi1xcon4: sqi xip control register 4 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 init2scheck init2count<1:0> init2type<1:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 init2cmd3<7:0> (1) 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 init2cmd2<7:0> (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 init2cmd1<7:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28 init2scheck: flash initialization 2 command status check bit 1 = check the status after executing the init2 command 0 = do not check the status bit 27-26 init2count<1:0>: flash initialization 2 command count bits 11 = init2cmd1, init2cmd2, and init2cmd3 are sent 10 = init2cmd1 and init2cmd2 are sent, but init2cmd3 is still pending 01 = init2cmd1 is sent, but init2cmd2 and init2cmd3 are still pending 00 = no commands are sent bit 25-24 init2type<1:0>: flash initialization 2 command type bits 11 = reserved 10 = init2 commands are sent in quad lane mode 01 = init2 commands are sent in dual lane mode 00 = init2 commands are sent in single lane mode bit 24-16 init2cmd3<7:0>: flash initialization command 3 bits (1) third command of the flash initialization. bit 15-8 init2cmd2<7:0>: flash initialization command 2 bits (1) second command of the flash initialization. bit 7-0 init2cmd1<7:0>: flash initialization command 1 bits (1) first command of the flash initialization. note 1: init2cmd1 can be wen and init2cmd2 can be sector unprotect. note: some flash devices require write enable and sector unprotect commands before read/write operations and this register is useful in working with those flash types (xip mode only)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 352 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 353 pic32mz embedded connectivity with floating point unit (ef) family 21.0 inter-integrated circuit (i 2 c) the i 2 c module provides complete hardware support for both slave and multi-master modes of the i 2 c serial communication standard. each i 2 c module has a 2-pin interface: sclx pin is clock sdax pin is data each i 2 c module offers the following key features: i 2 c interface supporting both master and slave operation i 2 c slave mode supports 7-bit and 10-bit addressing i 2 c master mode supports 7-bit and 10-bit addressing i 2 c port allows bidirectional transfers between master and slaves serial clock synchronization for the i 2 c port can be used as a handshake mechanism to suspend and resume serial transfer (sclrel control) i 2 c supports multi-master operation; detects bus collision and arbitrates accordingly provides support for address bit masking smbus support figure 21-1 illustrates the i 2 c module block diagram. note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 24. inter- integrated circuit (i 2 c) (ds60001116) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/ pic32 ).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 354 ? 2015-2016 microchip technology inc. figure 21-1: i 2 c block diagram internal data bus sclx sdax shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control pbclk2 start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk i2cxrcv
? 2015-2016 microchip technology inc. ds60001320d-page 355 pic32mz embedded connectivity with floating point unit (ef) family 21.1 i 2 c control registers table 21-1: i2c1 through i2c5 register map virtual address (bf82_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0000 i2c1con 31:16 pcie scie boen sdaht sbcde ahen dhen 0000 15:0 on sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 0010 i2c1stat 31:16 0000 15:0 ackstat trstat acktim bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 0020 i2c1add 31:16 0000 15:0 address register 0000 0030 i2c1msk 31:16 0000 15:0 address mask register 0000 0040 i2c1brg 31:16 0000 15:0 baud rate generator register 0000 0050 i2c1trn 31:16 0000 15:0 transmit register 0000 0060 i2c1rcv 31:16 0000 15:0 receive register 0000 0200 i2c2con (2) 31:16 pcie scie boen sdaht sbcde ahen dhen 0000 15:0 on sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 0210 i2c2stat (2) 31:16 0000 15:0 ackstat trstat acktim bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 0220 i2c2add (2) 31:16 0000 15:0 address register 0000 0230 i2c2msk (2) 31:16 0000 15:0 address mask register 0000 0240 i2c2brg (2) 31:16 0000 15:0 baud rate generator register 0000 0250 i2c2trn (2) 31:16 0000 15:0 transmit register 0000 0260 i2c2rcv (2) 31:16 0000 15:0 receive register 0000 0400 i2c3con 31:16 pcie scie boen sdaht sbcde ahen dhen 0000 15:0 on sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 0410 i2c3stat 31:16 0000 15:0 ackstat trstat acktim bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 0420 i2c3add 31:16 0000 15:0 address register 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table except i2cxrcv have corresponding clr, set and inv registers at their vi rtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this register is not available on 64-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 356 ? 2015-2016 microchip technology inc. 0430 i2c3msk 31:16 0000 15:0 address mask register 0000 0440 i2c3brg 31:16 0000 15:0 baud rate generator register 0000 0450 i2c3trn 31:16 0000 15:0 transmit register 0000 0460 i2c3rcv 31:16 0000 15:0 receive register 0000 0600 i2c4con 31:16 pcie scie boen sdaht sbcde ahen dhen 0000 15:0 on sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 0610 i2c4stat 31:16 0000 15:0 ackstat trstat acktim bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 0620 i2c4add 31:16 0000 15:0 address register 0000 0630 i2c4msk 31:16 0000 15:0 address mask register 0000 0640 i2c4brg 31:16 0000 15:0 baud rate generator register 0000 0650 i2c4trn 31:16 0000 15:0 transmit register 0000 0660 i2c4rcv 31:16 0000 15:0 receive register 0000 0800 i2c5con 31:16 pcie scie boen sdaht sbcde ahen dhen 0000 15:0 on sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 0810 i2c5stat 31:16 0000 15:0 ackstat trstat acktim bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 0820 i2c5add 31:16 0000 15:0 address register 0000 0830 i2c5msk 31:16 0000 15:0 address mask register 0000 0840 i2c5brg 31:16 0000 15:0 baud rate generator register 0000 0850 i2c5trn 31:16 0000 15:0 transmit register 0000 0860 i2c5rcv 31:16 0000 15:0 receive register 0000 table 21-1: i2c1 through i2c5 register map (continued) virtual address (bf82_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table except i2cxrcv have corresponding clr, set and inv registers at their vi rtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: this register is not available on 64-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 357 pic32mz embedded connectivity with floating point unit (ef) family register 21-1: i2c x con: i 2 c control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pcie scie boen sdaht sbcde ahen dhen 15:8 r/w-0 u-0 r/w-0 r/w-1, hc r/w-0 r/w-0 r/w-0 r/w-0 on sidl sckrel strict a10m disslw smen 7:0 r/w-0 r/w-0 r/w-0 r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc gcen stren ackdt acken rcen pen rsen sen legend: hc = cleared in hardware r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-23 unimplemented: read as 0 bit 22 pcie: stop condition interrupt enable bit (i 2 c slave mode only) 1 = enable interrupt on detection of stop condition 0 = stop detection interrupts are disabled bit 21 scie: start condition interrupt enable bit (i 2 c slave mode only) 1 = enable interrupt on detection of start or restart conditions 0 = start detection interrupts are disabled bit 20 boen: buffer overwrite enable bit (i 2 c slave mode only) 1 = i2cxrcv is updated and ack is generated for a received address/data byte, ignoring the state of the i2cov bit (i2cxstat<6>)only if the rbf bit (i2cxstat<2>) = 0 0 = i2cxrcv is only updated when the i2cov bit (i2cxstat<6>) is clear bit 19 sdaht: sda hold time selection bit 1 = minimum of 300 ns hold time on sda after the falling edge of scl 0 = minimum of 100 ns hold time on sda after the falling edge of scl bit 18 sbcde: slave mode bus collision detect enable bit (i 2 c slave mode only) 1 = enable slave bus collision interrupts 0 = slave bus collision interrupts are disabled bit 18 ahen: address hold enable bit (slave mode only) 1 = following the 8th falling edge of scl for a matching received address byte; sckrel bit will be cleared and the scl will be held low. 0 = address holding is disabled bit 16 dhen: data hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of scl for a received data byte; slave hardware clears the sckrel bit and scl is held low 0 = data holding is disabled bit 15 on: i 2 c enable bit 1 = enables the i 2 c module and configures the sda and scl pins as serial port pins 0 = disables the i 2 c module; all i 2 c pins are controlled by port functions bit 14 unimplemented: read as 0 bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 358 ? 2015-2016 microchip technology inc. bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = release sclx clock 0 = hold sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software can write 0 to initiate stretch and write 1 to release clock). hardware clear at beginning of slave transmission. hardware clear at end of slave reception. if stren = 0 : bit is r/s (i.e., software can only write 1 to release clock). hardware clear at beginning of slave ? transmission. bit 11 strict: strict i 2 c reserved address rule enable bit 1 = strict reserved addressing is enforced. device does not respond to reserved address space or generate addresses in reserved address space. 0 = strict i 2 c reserved address rule is not enabled bit 10 a10m: 10-bit slave address bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control is disabled 0 = slew rate control is enabled bit 8 smen: smbus input levels bit 1 = enable i/o pin thresholds compliant with smbus specification 0 = disable smbus input thresholds bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enable interrupt when a general call address is received in the i2cxrsr ? (module is enabled for reception) 0 = general call address is disabled bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with sclrel bit. 1 = enable software or receive clock stretching 0 = disable software or receive clock stretching bit 5 ackdt: acknowledge data bit (when operating as i 2 c master, applicable during master receive) value that is transmitted when the software initiates an acknowledge sequence. 1 = send nack during acknowledge 0 = send ack during acknowledge bit 4 acken: acknowledge sequence enable bit ? (when operating as i 2 c master, applicable during master receive) 1 = initiate acknowledge sequence on sdax and sclx pins and transmit ackdt data bit. ? hardware clear at end of master acknowledge sequence. 0 = acknowledge sequence not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c. hardware clear at end of eighth bit of master receive data byte. 0 = receive sequence not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiate stop condition on sdax and sclx pins. hardware clear at end of master stop sequence. 0 = stop condition not in progress bit 1 rsen: repeated start condition enable bit (when operating as i 2 c master) 1 = initiate repeated start condition on sdax and sclx pins. hardware clear at end of ? master repeated start sequence. 0 = repeated start condition not in progress bit 0 sen: start condition enable bit (when operating as i 2 c master) 1 = initiate start condition on sdax and sclx pins. hardware clear at end of master start sequence. 0 = start condition not in progress register 21-1: i2c x con: i 2 c control register (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 359 pic32mz embedded connectivity with floating point unit (ef) family register 21-2: i2c x stat: i 2 c status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r-0, hs, hc r-0, hs, hc r/c-0, hs, hc u- 0 u-0 r/c-0, hs r-0, hs, hc r-0, hs, hc ackstat trstat acktim bcl gcstat add10 7:0 r/c-0, hs, sc r/c-0, hs, sc r-0, hs, hc r/c-0, hs, hc r/c-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc iwcol i2cov d_a p s r_w rbf tbf legend: hs = hardware set hc = hardware cleared sc = software cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared c = clearable bit bit 31-16 unimplemented: read as 0 bit 15 ackstat: acknowledge status bit ? (when operating as i 2 c master, applicable to master transmit operation) 1 = nack received from slave 0 = ack received from slave hardware set or clear at end of slave acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware set at beginning of master transmission. hardware clear at end of slave acknowledge. bit 13 acktim: acknowledge time status bit (valid in i 2 c slave mode only) 1 = i 2 c bus is in an acknowledge sequence, set on the eight falling edge of scl clock 0 = not an acknowledge sequence, cleared on 9th rising edge of scl clock bit 12-11 unimplemented: read as 0 bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detected during a master operation 0 = no collision hardware set at detection of bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware set when address matches general call address. hardware clear at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware set at match of 2nd byte of matched 10-bit address. hardware clear at stop detection. bit 7 iwcol: write collision detect bit 1 = an attempt to write the i2cxtrn register failed because the i 2 c module is busy 0 = no collision hardware set at occurrence of write to i2cxtrn while busy (cleared by software). bit 6 i2cov: receive overflow flag bit 1 = a byte was received while the i2cxrcv register is still holding the previous byte 0 = no overflow hardware set at attempt to transfer i2 cxrsr to i2cxrcv (cleared by software).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 360 ? 2015-2016 microchip technology inc. bit 5 d_a: data/address bit (when operating as i 2 c slave) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was device address hardware clear at device address match. hardware set by reception of slave byte. bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware set or clear when start, repeated start or stop detected. bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware set or clear when start, repeated start or stop detected. bit 2 r_w: read/write information bit (when operating as i 2 c slave) 1 = read C indicates data transfer is output from slave 0 = write C indicates data transfer is input to slave hardware set or clear after reception of i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive complete, i2cxrcv is full 0 = receive not complete, i2cxrcv is empty hardware set when i2cxrcv is written with received byte. hardware clear when software ? reads i2cxrcv. bit 0 tbf: transmit buffer full status bit 1 = transmit in progress, i2cxtrn is full 0 = transmit complete, i2cxtrn is empty hardware set when software writes i2cxtrn. hardware clear at completion of data transmission. register 21-2: i2c x stat: i 2 c status register (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 361 pic32mz embedded connectivity with floating point unit (ef) family 22.0 universal asynchronous receiver transmitter (uart) the uart module is one of the serial i/o modules available in the pic32mz ef family of devices. the uart is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols, such as rs-232, rs-485, lin, and irda ? . the module also supports the hardware flow control option, with uxcts and uxrts pins, and also includes an irda encoder and decoder. the primary features of the uart module are: full-duplex, 8-bit or 9-bit data transmission even, odd or no parity options (for 8-bit data) one or two stop bits hardware auto-baud feature hardware flow control option fully integrated baud rate generator (brg) with 16-bit prescaler baud rates ranging from 76 bps to 25 mbps at 100 mhz (pbclk2) 8-level deep first-in-first-out (fifo) transmit data buffer 8-level deep fifo receive data buffer parity, framing and buffer overrun error detection support for interrupt-only on address detect ? (9th bit = 1 ) separate transmit and receive interrupts loopback mode for diagnostic support lin protocol support irda encoder and decoder with 16x baud clock output for external irda encoder/decoder support figure 22-1 illustrates a simplified block diagram of the uart module. figure 22-1: uart simplified block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 21. universal asynchronous receiver transmitter (uart) (ds60001107) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). baud rate generator uxrx hardware flow control uartx receiver uartx transmitter uxtx uxcts uxrts /bclkx irda ? pbclk2
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 362 ? 2015-2016 microchip technology inc. 22.1 uart control registers table 22-1: uart1 through uart6 register map virtual address (bf82_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 u1mode (1) 31:16 0000 15:0 on sidl iren rtsmd uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 2010 u1sta (1) 31:16 adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 2020 u1txreg 31:16 0000 15:0 tx8 transmit register 0000 2030 u1rxreg 31:16 0000 15:0 rx8 receive register 0000 2040 u1brg (1) 31:16 0000 15:0 baud rate generator prescaler 0000 2200 u2mode (1) 31:16 15:0 0000 on sidl iren rtsmd uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 2210 u2sta (1) 31:16 adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 2220 u2txreg 31:16 0000 15:0 tx8 transmit register 0000 2230 u2rxreg 31:16 0000 15:0 rx8 receive register 0000 2240 u2brg (1) 31:16 0000 15:0 baud rate generator prescaler 0000 2400 u3mode (1) 31:16 15:0 0000 on sidl iren rtsmd uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 2410 u3sta (1) 31:16 adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 2420 u3txreg 31:16 0000 15:0 tx8 transmit register 0000 2430 u3rxreg 31:16 0000 15:0 rx8 receive register 0000 2440 u3brg (1) 31:16 0000 15:0 baud rate generator prescaler 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offs et of 0x4, 0x8 and 0xc, respecti vely. see section 12.3 clr, set, and inv registers for more informa - tion.
? 2015-2016 microchip technology inc. ds60001320d-page 363 pic32mz embedded connectivity with floating point unit (ef) family 2600 u4mode (1) 31:16 15:0 0000 on sidl iren rtsmd uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 2610 u4sta (1) 31:16 adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 2620 u4txreg 31:16 0000 15:0 tx8 transmit register 0000 2630 u4rxreg 31:16 0000 15:0 rx8 receive register 0000 2640 u4brg (1) 31:16 0000 15:0 baud rate generator prescaler 0000 2800 u5mode (1) 31:16 15:0 0000 on sidl iren rtsmd uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 2810 u5sta (1) 31:16 adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 2820 u5txreg 31:16 0000 15:0 tx8 transmit register 0000 2830 u5rxreg 31:16 0000 15:0 rx8 receive register 0000 2840 u5brg (1) 31:16 0000 15:0 baud rate generator prescaler 0000 2a00 u6mode (1) 31:16 15:0 0000 on sidl iren rtsmd uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 2a10 u6sta (1) 31:16 adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 2a20 u6txreg 31:16 0000 15:0 tx8 transmit register 0000 2a30 u6rxreg 31:16 0000 15:0 rx8 receive register 0000 2a40 u6brg (1) 31:16 0000 15:0 baud rate generator prescaler 0000 table 22-1: uart1 through uart6 register map (continued) virtual address (bf82_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offs et of 0x4, 0x8 and 0xc, respecti vely. see section 12.3 clr, set, and inv registers for more informa- tion.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 364 ? 2015-2016 microchip technology inc. register 22-1: uxmode: uartx mode register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 on s i d li r e nr t s m d u e n < 1 : 0 > (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud rxinv brgh pdsel<1:0> stsel legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 on: uartx enable bit 1 = uartx is enabled. uartx pins are controlled by uartx as defined by uen<1:0> and utxen ? control bits 0 = uartx is disabled. all uartx pins are controlled by corresponding bits in the portx, trisx and latx registers; uartx power consumption is minimal bit 14 unimplemented: read as 0 bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters idle mode 0 = continue operation in idle mode bit 12 iren: irda encoder and decoder enable bit 1 = irda is enabled 0 = irda is disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 =uxrts pin is in simplex mode 0 =uxrts pin is in flow control mode bit 10 unimplemented: read as 0 bit 9-8 uen<1:0>: uartx enable bits (1) 11 = uxtx, uxrx and uxbclk pins are enabled and used; uxcts pin is controlled by corresponding bits in the portx register 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin is controlled by corresponding bits in the portx register 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /uxbclk pins are controlled by corresponding bits in the portx register bit 7 wake: enable wake-up on start bit detect during sleep mode bit 1 = wake-up is enabled 0 = wake-up is disabled bit 6 lpback: uartx loopback mode select bit 1 = loopback mode is enabled 0 = loopback mode is disabled note 1: these bits are present for legacy compatibility, and are superseded by pps functionality on these devices . for additional information, see section 12.4 peripheral pin select (pps) .
? 2015-2016 microchip technology inc. ds60001320d-page 365 pic32mz embedded connectivity with floating point unit (ef) family bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next character C requires reception of sync character (0x55); cleared by hardware upon completion 0 = baud rate measurement is disabled or completed bit 4 rxinv: receive polarity inversion bit 1 = uxrx idle state is 0 0 = uxrx idle state is 1 bit 3 brgh: high baud rate enable bit 1 = high-speed mode C 4x baud clock enabled 0 = standard speed mode C 16x baud clock enabled bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop selection bit 1 = 2 stop bits 0 = 1 stop bit register 22-1: uxmode: uartx mode register (continued) note 1: these bits are present for legacy compatibility, and are superseded by pps functionality on these devices . for additional information, see section 12.4 peripheral pin select (pps) .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 366 ? 2015-2016 microchip technology inc. register 22-2: uxsta: uartx status and control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 a d m _ e n 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr<7:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-1 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt 7:0 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 r/w-0 r-0 urxisel<1:0> adden ridle perr ferr oerr urxda legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-25 unimplemented: read as 0 bit 24 adm_en: automatic address detect mode enable bit 1 = automatic address detect mode is enabled 0 = automatic address detect mode is disabled bit 23-16 addr<7:0>: automatic address mask bits when the adm_en bit is 1 , this value defines the address character to use for automatic address detection. bit 15-14 utxisel<1:0>: tx interrupt mode selection bits 11 = reserved, do not use 10 = interrupt is generated and asserted while the transmit buffer is empty 01 = interrupt is generated and asserted when all characters have been transmitted 00 = interrupt is generated and asserted while the transmit buffer contains at least one empty space bit 13 utxinv: transmit polarity inversion bit if irda mode is disabled (i.e., iren (uxmode<12>) is 0 ): 1 = uxtx idle state is 0 0 = uxtx idle state is 1 if irda mode is enabled (i.e., iren (uxmode<12>) is 1 ): 1 = irda encoded uxtx idle state is 1 0 = irda encoded uxtx idle state is 0 bit 12 urxen: receiver enable bit 1 = uartx receiver is enabled. uxrx pin is controlled by uartx (if on = 1 ) 0 = uartx receiver is disabled. uxrx pin is ignored by the uartx module bit 11 utxbrk: transmit break bit 1 = send break on next transmission. start bit followed by twelve 0 bits, followed by stop bit; cleared by hardware upon completion 0 = break transmission is disabled or completed bit 10 utxen: transmit enable bit 1 = uartx transmitter is enabled. uxtx pin is controlled by uartx (if on = 1 ) 0 = uartx transmitter is disabled. any pending transmission is aborted and buffer is reset bit 9 utxbf: transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at least one more character can be written bit 8 trmt: transmit shift register is empty bit (read-only) 1 = transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
? 2015-2016 microchip technology inc. ds60001320d-page 367 pic32mz embedded connectivity with floating point unit (ef) family bit 7-6 urxisel<1:0>: receive interrupt mode selection bit 11 = reserved 10 = interrupt flag bit is asserted while receive buffer is 3/4 or more full 01 = interrupt flag bit is asserted while receive buffer is 1/2 or more full 00 = interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character) bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode is enabled. if 9-bit mode is not selected, this control bit has no effe ct 0 = address detect mode is disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = data is being received bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current character 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit. this bit is set in hardware and can only be cleared (= 0 ) in software. clearing a previously set oerr bit resets the receiver buffer and rsr to empty state. 1 = receive buffer has overflowed 0 = receive buffer has not overflowed bit 0 urxda: receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 22-2: uxsta: uartx status and control register (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 368 ? 2015-2016 microchip technology inc. figure 22-2 and figure 22-3 illustrate the typical receive and transmit timing for the uart module. figure 22-2: uart reception figure 22-3: transmission (8-bit or 9-bit data) start 1 stop start 2 stop 4 start 5 stop 10 start 11 stop 13 read to uxrxreg uxrx ridle oerr uxrxif urxisel = 00 uxrxif urxisel = 01 uxrxif urxisel = 10 char 1 char 2-4 char 5-10 char 11-13 cleared by software cleared by software cleared by software start start bit 0 bit 1 stop write to tsr bclk/16 (shift clock) uxtx uxtxif uxtxif utxisel = 00 bit 1 uxtxreg utxisel = 01 uxtxif utxisel = 10 8 into txbuf pull from buffer
? 2015-2016 microchip technology inc. ds60001320d-page 369 pic32mz embedded connectivity with floating point unit (ef) family 23.0 parallel master port (pmp) the pmp is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, lcds, external memory devices and microcontrollers. because the interface to parallel peripherals varies significantly, the pmp module is highly configurable. the following are key features of the pmp module: 8-bit,16-bit interface up to 16 programmable address lines up to two chip select lines programmable strobe options: - individual read and write strobes, or - read/ write strobe with enable strobe address auto-increment/auto-decrement programmable address/data multiplexing programmable polarity on control signals parallel slave port support: - legacy addressable - address support - 4-byte deep auto-incrementing buffer programmable wait states operate during sleep and idle modes separate configurable read/write registers or dual buffers for master mode fast bit manipulation using clr, set, and inv registers figure 23-1: pmp module pinout and connections to external devices note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive refer - ence source. to complement the informa - tion in this data sheet, refer to section 13. parallel master port (pmp) (ds60001128) in the ?pic32 family ref - erence manual? , which is available from the microchip web site ( www.micro - chip.com/pic32 ). note: on 64-pin devices, data pins pmd<15:8> are not available in 16-bit master modes. pma0 pma14 pmrd pmwr pmenb pmrd/pmwr pmcs1 pma1 pma<13:2> pmall pmalh flash address bus data bus control lines lcd fifo microcontroller 8-bit/16-bit data (with or without multiplexed addressing) up to 16-bit address parallel buffer pmd<7:0> master port eeprom sram note: on 64-pin devices, data pins pmd<15:8> are not available in 16-bit master modes. pmd<15:8> (1) pma15 pmcs2 pbclk2
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 370 ? 2015-2016 microchip technology inc. 23.1 pmp control registers table 23-1: parallel master port register map virtual address (bf82_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 e000 pmcon 31:16 rdstart dualbuf 0000 15:0 on sidl adrmux<1:0> pmpttl ptwren ptrden csf<1:0> alp cs2p cs1p wrsp rdsp 0000 e010 pmmode 31:16 0000 15:0 busy irqm<1:0> incm<1:0> mode16 mode<1:0> waitb<1:0> waitm<3:0> waite<1:0> 0000 e020 pmaddr 31:16 0000 15:0 cs2 cs1 addr<13:0> 0000 addr15 addr14 0000 e030 pmdout 31:16 0000 15:0 dataout<15:0> 0000 e040 pmdin 31:16 0000 15:0 datain<15:0> 0000 e050 pmaen 31:16 0000 15:0 pten<15:0> 0000 e060 pmstat 31:16 0000 15:0 ibf ibov ib3f ib2f ib1f ib0f obe obuf ob3e ob2e ob1e ob0e 008f e070 pmwaddr 31:16 0000 15:0 wcs2 wcs1 0000 waddr15 waddr14 waddr<13:0> 0000 e080 pmraddr 31:16 0000 15:0 rcs2 rcs1 0000 raddr15 raddr14 raddr<13:0> 0000 e090 pmrdin 31:16 31:16 0000 15:0 15:0 rdatain<15:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus of fsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 371 pic32mz embedded connectivity with floating point unit (ef) family register 23-1: pmcon: parallel port control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 r/w-0, hc u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 rdstart dualbuf 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 on s i d l adrmux<1:0> pmpttl ptwren ptrden 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 csf<1:0> (1) alp (1) cs2p (1) cs1p (1) wrsp rdsp legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as 0 bit 23 rdstart: start read on pmp bus bit this bit is cleared by hardware at the end of the read cycle. 1 = start a read cycle on the pmp bus 0 = no effect bit 22-18 unimplemented: read as 0 bit 17 dualbuf: dual read/write buffers enable bit this bit is valid in master mode only. 1 = pmp uses separate registers for reads and wr ites (pmraddr, pmdatain, pmwaddr, pmdataout) 0 = pmp uses legacy registers (pmaddr, pmdata) bit 16 unimplemented: read as 0 bit 15 on: parallel master port enable bit 1 = pmp is enabled 0 = pmp is disabled, no off-chip access performed bit 14 unimplemented: read as 0 bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 adrmux<1:0>: address/data multiplexing selection bits 11 = lower 8 bits of address are multiplexed on pmd<15:0> pins; upper 8 bits are not used 10 = all 16 bits of address are multiplexed on pmd<15:0> pins 01 = lower 8 bits of address are multiplexed on pmd<7:0> pins, upper bits are on pma<15:8> 00 = address and data appear on separate pins bit 10 pmpttl: pmp module ttl input buffer select bit 1 = pmp module uses ttl input buffers 0 = pmp module uses schmitt trigger input buffer bit 9 ptwren: write enable strobe port enable bit 1 = pmwr/pmenb port is enabled 0 = pmwr/pmenb port is disabled bit 8 ptrden: read/write strobe port enable bit 1 = pmrd/pmwr port is enabled 0 = pmrd/pmwr port is disabled note 1: these bits have no effect when their corresponding pins are used as address lines.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 372 ? 2015-2016 microchip technology inc. bit 7-6 csf<1:0>: chip select function bits (1) 11 = reserved 10 = pmcs1 and pmcs2 function as chip select 01 = pmcs2 functions as chip select and pmcs1 functions as address bit 14 00 = pmcs1 and pmcs2 function as address bit 14 and address bit 15 bit 5 alp: address latch polarity bit (1) 1 = active-high (pmall and pmalh) 0 = active-low (pmall and pmalh ) bit 4 cs2p: chip select 2 polarity bit (1) 1 = active-high (pmcs2) 0 =active-low (pmcs2 ) bit 3 cs1p: chip select 1 polarity bit (1) 1 = active-high (pmcs1) 0 =active-low (pmcs1 ) bit 2 unimplemented: read as 0 bit 1 wrsp: write strobe polarity bit for slave modes and master mode 2 ( m ode< 1:0> = 00 , 01 , 10 ) : 1 = write strobe active-high (pmwr) 0 = write strobe active-low (pmwr ) for master mode 1 ( m ode< 1:0> = 11 ) : 1 = enable strobe active-high (pmenb) 0 = enable strobe active-low (pmenb ) bit 0 rdsp: read strobe polarity bit for slave modes and master mode 2 ( m ode< 1:0> = 00 , 01 , 10 ) : 1 = read strobe active-high (pmrd) 0 = read strobe active-low (pmrd ) for master mode 1 ( m ode< 1:0> = 11 ) : 1 = read/write strobe active-high (pmrd/pmwr ) 0 = read/write strobe active-low (pmrd /pmwr) register 23-1: pmcon: parallel po rt control register (continued) note 1: these bits have no effect when their corresponding pins are used as address lines.
? 2015-2016 microchip technology inc. ds60001320d-page 373 pic32mz embedded connectivity with floating point unit (ef) family register 23-2: pmmode: parallel port mode register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 busy irqm<1:0> incm<1:0> mode16 mode<1:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 waitb<1:0> (1) waitm<3:0> (1) waite<1:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 busy: busy bit (master mode only) 1 = port is busy 0 = port is not busy bit 14-13 irqm<1:0>: interrupt request mode bits 11 = reserved, do not use 10 = interrupt is generated when read buffer 3 is read or write buffer 3 is written (buffered psp mode) ? or on a read or write operation when pma<1:0> = 11 (addressable slave mode only) 01 = interrupt is generated at the end of the read/write cycle 00 = no interrupt is generated bit 12-11 incm<1:0>: increment mode bits 11 = slave mode read and write buffers auto-increment (mode<1:0> = 00 only) 10 = decrement addr<15:0> and addr<14> by 1 every read/write cycle (2) 01 = increment addr<15:0> and addr<14> by 1 every read/write cycle (2) 00 = no increment or decrement of address bit 10 mode16: 8/16-bit mode bit 1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer 0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer bit 9-8 mode<1:0>: parallel port mode select bits 11 = master mode 1 (pmcsx, pmrd/pmwr, pmenb, pma, and pmd<15:0>) (3) 10 = master mode 2 (pmcsx, pmrd, pmwr, pma, and pmd<15:0>) (3) 01 = enhanced slave mode, control signals (pmrd, pmwr, pmcsx, pmd<7:0>, and pma<1:0>) 00 = legacy parallel slave port, control signals (pmrd, pmwr, pmcsx, and pmd<7:0>) bit 7-6 waitb<1:0>: data setup to read/write strobe wait states bits (1) 11 = data wait of 4 t pbclk 2 ; multiplexed address phase of 4 t pbclk 2 10 = data wait of 3 t pbclk 2 ; multiplexed address phase of 3 t pbclk 2 01 = data wait of 2 t pbclk 2 ; multiplexed address phase of 2 t pbclk 2 00 = data wait of 1 t pbclk 2 ; multiplexed address phase of 1 t pbclk 2 (default) note 1: whenever waitm<3:0> = 0000, waitb and waite bits are ignored and forced to 1 t pbclk 2 cycle for a write operation; waitb = 1 t pbclk 2 cycle, waite = 0 t pbclk 2 cycles for a read operation. 2: address bits 14 and 15 are is not subject to auto-increment/decrement if configured as chip select. 3: the pmd<15:8> bits are not active is the mode16 bit = 1 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 374 ? 2015-2016 microchip technology inc. bit 5-2 waitm<3:0>: data read/write strobe wait states bits (1) 1111 = wait of 16 t pbclk 2 0001 = wait of 2 t pbclk 2 0000 = wait of 1 t pbclk 2 (default) bit 1-0 waite<1:0>: data hold after read/write strobe wait states bits (1) 11 = wait of 4 t pbclk 2 10 = wait of 3 t pbclk 2 01 = wait of 2 t pbclk 2 00 = wait of 1 t pbclk 2 (default) for read operations: 11 = wait of 3 t pbclk 2 10 = wait of 2 t pbclk 2 01 = wait of 1 t pbclk 2 00 = wait of 0 t pbclk 2 (default) register 23-2: pmmode: parallel po rt mode register (continued) note 1: whenever waitm<3:0> = 0000, waitb and waite bits are ignored and forced to 1 t pbclk 2 cycle for a write operation; waitb = 1 t pbclk 2 cycle, waite = 0 t pbclk 2 cycles for a read operation. 2: address bits 14 and 15 are is not subject to auto-increment/decrement if configured as chip select. 3: the pmd<15:8> bits are not active is the mode16 bit = 1 .
? 2015-2016 microchip technology inc. ds60001320d-page 375 pic32mz embedded connectivity with floating point unit (ef) family register 23-3: pmaddr: paralle l port address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cs2 (1) cs1 (3) addr<13:8> addr15 (2) addr14 (4) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 cs2: chip select 2 bit (1) 1 = chip select 2 is active 0 = chip select 2 is inactive bit 15 addr<15>: target address bit 15 (2) bit 14 cs1: chip select 1 bit (3) 1 = chip select 1 is active 0 = chip select 1 is inactive bit 14 addr<14>: target address bit 14 (4) bit 13-0 addr<13:0>: address bits note 1: when the csf<1:0> bits (pmcon<7:6>) = 10 or 01 . 2: when the csf<1:0> bits (pmcon<7:6>) = 00 . 3: when the csf<1:0> bits (pmcon<7:6>) = 10 . 4: when the csf<1:0> bits (pmcon<7:6>) = 00 or 01 . note: if the dualbuf bit (pmcon<17>) = 0 , the bits in this register control both read and write target addressing. if the dualbuf bit = 1 , the bits in this register are not used. in this instance, use the pmraddr register for read operations and the pmwaddr register for write operations.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 376 ? 2015-2016 microchip technology inc. register 23-4: pmdout: parallel port output data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dataout<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dataout<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 dataout<15:0>: port data output bits this register is used for read operations in the enhanced parallel slave mode and write operations for dual buffer master mode. in dual buffer master mode, the dualbuf bit (pmpcon<17>) = 1 , a write to the msb triggers the trans- action on the pmp port. when mode16 = 1 , msb = dataout<15:8>. when mode16 = 0 , msb = dataout<7:0>. note: in master mode, a read will return the last value written to the register. in slave mode, a read will return indeterminate results. register 23-5: pmdin: parallel port input data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 datain<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 datain<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 datain<15:0>: port data input bits this register is used for both parallel master port mode and enhanced parallel slave mode. in parallel master mode, a write to the msb triggers the write transaction on the pmp port. similarly, a read to the msb triggers the read transaction on the pmp port. when mode16 = 1 , msb = datain<15:8>. when mode16 = 0 , msb = datain<7:0>. note: this register is not used in dual buffer master mode (i.e., dualbuf bit (pmpcon<17>) = 1 ).
? 2015-2016 microchip technology inc. ds60001320d-page 377 pic32mz embedded connectivity with floating point unit (ef) family register 23-6: pmaen: parallel port pin enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pten<15:14> pten<13:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pten<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as 0 bit 15-14 pten<15:14>: pmcs1 strobe enable bits 1 = pma15 and pma14 function as either pma<15:14> or pmcs1 and pmcs2 (1) 0 = pma15 and pma14 function as port i/o bit 13-2 pten<13:2>: pmp address port enable bits 1 = pma<13:2> function as pmp address lines 0 = pma<13:2> function as port i/o bit 1-0 pten<1:0>: pmalh/pmall strobe enable bits 1 = pma1 and pma0 function as either pma<1:0> or pmalh and pmall (2) 0 = pma1 and pma0 pads function as port i/o note 1: the use of these pins as pma15 and pma14 or cs1 and cs2 is selected by the csf<1:0> bits in the pmcon register. 2: the use of these pins as pma1/pma0 or pmalh/pmall depends on the address/da ta multiplex mode selected by bits adrmux<1:0> in the pmcon register.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 378 ? 2015-2016 microchip technology inc. register 23-7: pmstat: parallel port st atus register (slave modes only) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r-0 r/w-0, hs, sc u-0 u-0 r-0 r-0 r-0 r-0 ibf ibov ib3f ib2f ib1f ib0f 7:0 r-1 r/w-0, hs, sc u-0 u-0 r-1 r-1 r-1 r-1 obe obuf ob3e ob2e ob1e ob0e legend: hs = hardware set sc = software cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 ibf: input buffer full status bit 1 = all writable input buffer registers are full 0 = some or all of the writable input buffer registers are empty bit 14 ibov: input buffer overflow status bit 1 = a write attempt to a full input byte buffer is occurred (must be cleared in software) 0 = no overflow is occurred bit 13-12 unimplemented: read as 0 bit 11-8 ibxf: input buffer x status full bits 1 = input buffer contains data that has not been read (reading buffer will clear this bit) 0 = input buffer does not contain any unread data bit 7 obe: output buffer empty status bit 1 = all readable output buffer registers are empty 0 = some or all of the readable output buffer registers are full bit 6 obuf: output buffer underflow status bit 1 = a read occurred from an empty output byte buffer (must be cleared in software) 0 = no underflow is occurred bit 5-4 unimplemented: read as 0 bit 3-0 obxe: output buffer x status empty bits 1 = output buffer is empty (writing data to the buffer will clear this bit) 0 = output buffer contains data that has not been transmitted
? 2015-2016 microchip technology inc. ds60001320d-page 379 pic32mz embedded connectivity with floating point unit (ef) family register 23-8: pmwaddr: parallel port write address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcs2 (1) wcs1 (3) waddr<13:8> waddr15 (2) waddr14 (4) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 waddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 wcs2: chip select 2 bit (1) 1 = chip select 2 is active 0 = chip select 2 is inactive bit 15 waddr<15>: target address bit 15 (2) bit 14 wcs1: chip select 1 bit (3) 1 = chip select 1 is active 0 = chip select 1 is inactive bit 14 waddr<14>: target address bit 14 (4) bit 13-0 waddr<13:0>: address bits note 1: when the csf<1:0> bits (pmcon<7:6>) = 10 or 01 . 2: when the csf<1:0> bits (pmcon<7:6>) = 00 . 3: when the csf<1:0> bits (pmcon<7:6>) = 10 . 4: when the csf<1:0> bits (pmcon<7:6>) = 00 or 01 . note: this register is only used when the dualbuf bit (pmcon<17>) is set to 1 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 380 ? 2015-2016 microchip technology inc. register 23-9: pmraddr: parallel port read address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rcs2 (1) rcs1 (3) raddr<13:8> raddr15 (2) raddr14 (4) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 raddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 rcs2: chip select 2 bit (1) 1 = chip select 2 is active 0 = chip select 2 is inactive (raddr15 function is selected) bit 15 raddr<15>: target address bit 15 (2) bit 14 rcs1: chip select 1 bit (3) 1 = chip select 1 is active 0 = chip select 1 is inactive (raddr14 function is selected) bit 14 raddr<14>: target address bit 14 (4) bit 13-0 raddr<13:0>: address bits note 1: when the csf<1:0> bits (pmcon<7:6>) = 10 or 01 . 2: when the csf<1:0> bits (pmcon<7:6>) = 00 . 3: when the csf<1:0> bits (pmcon<7:6>) = 10 . 4: when the csf<1:0> bits (pmcon<7:6>) = 00 or 01 . note: this register is only used when the dualbuf bit (pmcon<17>) is set to 1 .
? 2015-2016 microchip technology inc. ds60001320d-page 381 pic32mz embedded connectivity with floating point unit (ef) family register 23-10: pmrdin: parallel port read input data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rdatain<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rdatain<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 rdatain<15:0>: port read input data bits note: this register is only used when the dualbuf bit (pmcon<17>) is set to 1 and exclusively for reads. if the dualbuf bit is 0 , the pmdin register ( register 23-5 ) is used for reads instead of pmrdin.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 382 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 383 pic32mz embedded connectivity with floating point unit (ef) family 24.0 external bus interface (ebi) the external bus interface (ebi) module provides a high-speed, convenient way to interface external parallel memory devices to the pic32mz ef family device. with the ebi module, it is possible to connect asynchronous sram and nor flash devices, as well as non-memory devices such as camera sensors and lcds. the features of the ebi module depend on the pin count of the pic32mz ef device, as shown in table 24-1 . table 24-1: ebi module features figure 24-1: ebi system block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 47. external bus interface (ebi) (ds60001245) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). note: the ebi module is not available on 64-pin devices. feature number of device pins 100 124 144 async sram y y y async nor flash y y y available address lines 20 20 24 8-bit data bus support y y y 16-bit data bus support y y y available chip selects 1 1 4 timing mode sets 3 3 3 8-bit r/w from 16-bit bus n n y non-memory device y y y lcd y y y note: once the ebi module is configured, exter - nal devices will be memory mapped and can be access from kseg2 memory space (see figure 4-1 through figure 4-4 in section 4.0 memory organization for more information). the mmu must be enabled and the tlb must be set up to access this memory (refer to section 50. cpu for devices with mips32 ? microaptiv? and m-class cores (ds60001192) of the ?pic32 family reference manual? for more information). control registers address decoder static memory controller control registers data fifo address fifo system bus bus interface memory interface external bus interface sysclk ebia<23:0> ebid<15:0> ebibs <1:0> ebics <3:0> ebioe ebirp ebiwe ebirdy<3:1>
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 384 ? 2015-2016 microchip technology inc. 24.1 ebi control registers table 24-2: ebi register map virtual address (bf8e_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1014 ebics0 31:16 csaddr<15:0> 0000 15:0 0000 1018 ebics1 (1) 31:16 csaddr<15:0> 0000 15:0 0000 101c ebics2 (1) 31:16 csaddr<15:0> 0000 15:0 0000 1020 ebics3 (1) 31:16 csaddr<15:0> 0000 15:0 0000 1054 ebimsk0 31:16 0000 15:0 regsel<2:0> memtype<2:0> memsize<4:0> 0020 1058 ebimsk1 (1) 31:16 0000 15:0 regsel<2:0> memtype<2:0> memsize<4:0> 0020 105c ebimsk2 (1) 31:16 0000 15:0 regsel<2:0> memtype<2:0> memsize<4:0> 0120 1060 ebimsk3 (1) 31:16 0000 15:0 regsel<2:0> memtype<2:0> memsize<4:0> 0120 1094 ebismt0 31:16 rdymode pagesize<1:0> pagemode tprc<3:0> tbta<2:0> 041c 15:0 twp<5:0> twr<1:0> tas<1:0> trc<5:0> 2d4b 1098 ebismt1 31:16 rdymode pagesize<1:0> pagemode tprc<3:0> tbta<2:0> 041c 15:0 twp<5:0> twr<1:0> tas<1:0> trc<5:0> 2d4b 109c ebismt2 31:16 rdymode pagesize<1:0> pagemode tprc<3:0> tbta<2:0> 014c 15:0 twp<5:0> twr<1:0> tas<1:0> trc<5:0> 2d4b 10a0 ebiftrpd 31:16 0000 15:0 trpd<11:0> 00c8 10a4 ebismcon 31:16 0000 15:0 smdwidth2<2:0> smdwidth1<2:0> smdwidth0<2:0> smrp 0201 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register is available on 144-pin devices only.
? 2015-2016 microchip technology inc. ds60001320d-page 385 pic32mz embedded connectivity with floating point unit (ef) family register 24-1: ebicsx: external bus interfac e chip select register (x = 0-3) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 csaddr<15:8> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 csaddr<7:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 csaddr<15:0>: base address for device bits address in physical memory, which will select the external device. bit 15-0 unimplemented: read as 0
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 386 ? 2015-2016 microchip technology inc. register 24-2: ebimskx: external bus interf ace address mask register (x = 0-3) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u - 0u - 0u - 0u - 0u - 0u - 0u - 0u - 0 23:16 u - 0u - 0u - 0u - 0u - 0u - 0u - 0u - 0 15:8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 regsel<2:0> 7:0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 memtype<2:0> memsize<4:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-11 unimplemented: read as 0 bit 10-8 regsel<2:0>: timing register set for chip select x bits 111 = reserved 011 = reserved 010 = use ebismt2 001 = use ebismt1 000 = use ebismt0 bit 7-5 memtype<2:0>: select memory type for chip select x bits 111 = reserved 011 = reserved 010 = nor-flash 001 = sram 000 = reserved bit 4-0 memsize<4:0>: select memory size for chip select x bits (1) 11111 = reserved 01010 = reserved 01001 = 16 mb 01000 = 8 mb 00111 = 4 mb 00110 = 2 mb 00101 = 1 mb 00100 = 512 kb 00011 = 256 kb 00010 = 128 kb 00001 = 64 kb (smaller memories alias within this range) 00000 = chip select is not used note 1: the specified value for these bits depends on the number of available address lines. refer to the specific device pin table ( table 2 through table 5 ) for the available address lines.
? 2015-2016 microchip technology inc. ds60001320d-page 387 pic32mz embedded connectivity with floating point unit (ef) family register 24-3: ebismtx: external bus inte rface static memory timing register ? (x = 0-2) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 rdymode pagesize<1:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 pagemode tprc<3:0> (1) tbta<2:0> (1) 15:8 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 r/w-1 r/w-0 r/w-1 twp<5:0> (1) twr<1:0> (1) 7:0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 r/w-1 tas<1:0> (1) trc<5:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-27 unimplemented: read as 0 bit 26 rdymode: data ready device select bit the device associated with register set x is a data-ready device, and will use the ebirdyx pin. 1 = ebirdyx input is used 0 = ebirdyx input is not used bit 25-24 pagesize<1:0>: page size for page mode device bits 11 = 32-word page 10 = 16-word page 01 = 8-word page 00 = 4-word page bit 23 pagemode: memory device page mode support bit 1 = device supports page mode 0 = device does not support page mode bit 22-19 tprc<3:0>: page mode read cycle time bits (1) read cycle time is tprc + 1 clock cycle. bit 18-16 tbta<2:0>: data bus turnaround time bits (1) clock cycles (0-7) for static memory between read-to-write, write-to-read, and read-to-read when chip select changes. bit 15-10 twp<5:0>: write pulse width bits (1) write pulse width is twp + 1 clock cycle. bit 9-8 twr<1:0>: write address/data hold time bits (1) number of clock cycles to hold address or data on the bus. bit 7-6 tas<1:0>: write address setup time bits (1) clock cycles for address setup time. a value of 0 is only valid in the case of ssram. bit 5-0 trc<5:0>: read cycle time bits (1) read cycle time is trc + 1 clock cycle. note 1: refer to the section 47. external bus interface (ebi) in the ?pic32 family reference manual? for the ebi timing diagrams and additional information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 388 ? 2015-2016 microchip technology inc. register 24-4: ebiftrpd: external bus interface flash timing register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 trpd<11:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trpd<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-12 unimplemented: read as 0 bit 11-0 trpd<11:0>: flash timing bits these bits define the number of clock cycles to wait after resetting the external flash memory before any read/write access.
? 2015-2016 microchip technology inc. ds60001320d-page 389 pic32mz embedded connectivity with floating point unit (ef) family register 24-5: ebismcon: external bus interface static memory control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 smdwidth2<2:0> smdwidth1<2:0> smdwidth0<2:1> 7:0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-1 smdwidth0<0> s m r p legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-13 smdwidth2<2:0>: static memory width for register ebismt2 bits 111 = reserved 110 = reserved 101 = reserved 100 = 8 bits 011 = reserved 010 = reserved 001 = reserved 000 = 16 bits bit 12-10 smdwidth1<2:0>: static memory width for register ebismt1 bits 111 = reserved 110 = reserved 101 = reserved 100 = 8 bits 011 = reserved 010 = reserved 001 = reserved 000 = 16 bits bit 9-7 smdwidth0<2:0>: static memory width for register ebismt0 bits 111 = reserved 110 = reserved 101 = reserved 100 = 8 bits 011 = reserved 010 = reserved 001 = reserved 000 = 16 bits bit 6-1 unimplemented: read as 0 bit 0 smrp: flash reset/power-down mode select bit after a reset, the controller internally performs a power-down for flash, and then sets this bit to 1 . 1 = flash is taken out of power-down mode 0 = flash is forced into power-down mode
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 390 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 391 pic32mz embedded connectivity with floating point unit (ef) family 25.0 real-time clock and calendar (rtcc) the rtcc module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no cpu intervention. low- power optimization provides extended battery lifetime while keeping track of time. the following are key features of the rtcc module: time: hours, minutes, and seconds 24-hour format (military time) visibility of one-half second period provides calendar: weekday, date, month and year alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month, and one year alarm repeat with decrementing counter alarm with indefinite repeat: chime year range: 2000 to 2099 leap year correction bcd format for smaller firmware overhead optimized for long-term battery operation fractional second synchronization user calibration of the clock crystal frequency with auto-adjust calibration range: ? 0.66 seconds error per month calibrates up to 260 ppm of crystal error uses external 32.768 khz crystal or 32 khz internal oscillator alarm pulse, seconds clock, or internal clock output on rtcc pin figure 25-1: rt cc block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 29. real-time clock and calendar (rtcc) (ds60001125) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). rtcc prescalers rtcc timer comparator compare registers repeat counter year, mth, day wkday hr, min, sec mth, day wkday hr, min, sec with masks rtcc interrupt logic alarm event 32.768 khz input from secondary oscillator (s osc ) 0.5 seconds rtcc interrupt rtcval alrmval rtcc pin rtcoe 32 khz input from internal oscillator (lprc) rtcclksel<1:0> t rtc seconds pulse t rtc alarm pulse rtcoutsel<1:0>
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 392 ? 2015-2016 microchip technology inc. 25.1 rtcc control registers table 25-1: rtcc register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0c00 rtccon 31:16 cal<9:0> 0000 15:0 on sidl rtcclksel<1:0> rtcoutsel<1:0> rtcclkon rtcwren rtcsync halfsec rtcoe 0000 0c10 rtcalrm 31:16 0000 15:0 alrmen chime piv alrmsync amask<3:0> arpt<7:0> 0000 0c20 rtctime 31:16 hr10<3:0> hr01<3:0> min10<3:0> min01<3:0> xxxx 15:0 sec10<3:0> sec01<3:0> xx00 0c30 rtcdate 31:16 year10<3:0> year01<3:0> month10<3:0> month01<3:0> xxxx 15:0 day10<3:0> day01<3:0> wday01<3:0> xx00 0c40 alrmtime 31:16 hr10<3:0> hr01<3:0> min10<3:0> min01<3:0> xxxx 15:0 sec10<3:0> sec01<3:0> xx00 0c50 alrmdate 31:16 month10<3:0> month01<3:0> 00xx 15:0 day10<3:0> day01<3:0> wday01<3:0> xx0x legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual addr ess, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 393 pic32mz embedded connectivity with floating point unit (ef) family register 25-1: rtccon: real-time cl ock and calendar control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 c a l < 9 : 8 > 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cal<7:0> 15:8 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 on (1) s i d l rtcclksel<1:0> rtc outsel<1> (2) 7:0 r/w-0 r-0 u-0 u-0 r/w-0 r-0 r-0 r/w-0 rtc outsel<0> (2) rtc clkon (5) rtc wren (3) rtc sync halfsec (4) rtcoe legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-26 unimplemented: read as 0 bit 25-16 cal<9:0>: real-time clock drift calibration bits, which contain a signed 10-bit integer value 0111111111 = maximum positive adjustment, adds 511 real-time clock pulses every one minute 0000000001 = minimum positive adjustment, adds 1 real-time clock pulse every one minute 0000000000 = no adjustment 1111111111 = minimum negative adjustment, subtracts 1 real-time clock pulse every one minute 1000000000 = maximum negative adjustment, subtracts 512 real-time clock pulses every one minute bit 15 on: rtcc on bit (1) 1 = rtcc module is enabled 0 = rtcc module is disabled bit 14 unimplemented: read as 0 bit 13 sidl: stop in idle mode bit 1 = disables rtcc operation when cpu enters idle mode 0 = continue normal operation when cpu enters idle mode bit 12-11 unimplemented: read as 0 note 1: the on bit is only writable when rtcwren = 1 . 2: requires rtcoe = 1 (rtccon<0>) for the output to be active. 3: the rtcwren bit can be set only when the write sequence is enabled. 4: this bit is read-only. it is cleared to 0 on a write to the seconds bit fields (rtctime<14:8>). 5: this bit is undefined when rtcclksel<1:0> = 00 (lprc is the clock source). note: this register is reset only on a power-on reset (por).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 394 ? 2015-2016 microchip technology inc. bit 10-9 rtcclksel<1:0>: rtcc clock select bits when a new value is written to these bits, the seconds value register should also be written to properly reset the clock prescalers in the rtcc. 11 = reserved 10 = reserved 01 = rtcc uses the external 32.768 khz secondary oscillator (sosc) 00 = rtcc uses the internal 32 khz oscillator (lprc) bit 8-7 rtcoutsel<1:0>: rtcc output data select bits (2) 11 = reserved 10 = rtcc clock is presented on the rtcc pin 01 = seconds clock is presented on the rtcc pin 00 = alarm pulse is presented on the rtcc pin when the alarm interrupt is triggered bit 6 rtcclkon: rtcc clock enable status bit (5) 1 = rtcc clock is actively running 0 = rtcc clock is not running bit 5-4 unimplemented: read as 0 bit 3 rtcwren: real-time clock value registers write enable bit (3) 1 = real-time clock value registers can be written to by the user 0 = real-time clock value registers are locked out from being written to by the user bit 2 rtcsync: real-time clock value registers read synchronization bit 1 = real-time clock value registers can change while reading (due to a rollover ripple that results in an invalid data read). if the register is read twice and results in the same data, the data can be assumed to be valid. 0 = real-time clock value registers can be read without concern about a rollover ripple bit 1 halfsec: half-second status bit (4) 1 = second half period of a second 0 = first half period of a second bit 0 rtcoe: rtcc output enable bit 1 = rtcc output is enabled 0 = rtcc output is not enabled register 25-1: rtccon: real-time cl ock and calendar control register (continued) note 1: the on bit is only writable when rtcwren = 1 . 2: requires rtcoe = 1 (rtccon<0>) for the output to be active. 3: the rtcwren bit can be set only when the write sequence is enabled. 4: this bit is read-only. it is cleared to 0 on a write to the seconds bit fields (rtctime<14:8>). 5: this bit is undefined when rtcclksel<1:0> = 00 (lprc is the clock source). note: this register is reset only on a power-on reset (por).
? 2015-2016 microchip technology inc. ds60001320d-page 395 pic32mz embedded connectivity with floating point unit (ef) family register 25-2: rtcalrm: real-time clock alarm control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 alrmen (1,2) chime (2) piv (2) alrmsync amask<3:0> (2) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 arpt<7:0> (2) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 alrmen: alarm enable bit (1,2) 1 = alarm is enabled 0 = alarm is disabled bit 14 chime: chime enable bit (2) 1 = chime is enabled C arpt<7:0> is allowed to rollover from 0x00 to 0xff 0 = chime is disabled C arpt<7:0> stops once it reaches 0x00 bit 13 piv: alarm pulse initial value bit (2) when alrmen = 0 , piv is writable and determines the initial value of the alarm pulse. when alrmen = 1 , piv is read-only and returns the state of the alarm pulse. bit 12 alrmsync: alarm sync bit 1 = arpt<7:0> and alrmen may change as a result of a half second rollover during a read. ? the arpt must be read repeatedly until the same value is read twice. this must be done since multiple bits may be changing. 0 = arpt<7:0> and alrmen can be read without concerns of rollover because the prescaler is more than 32 real-time clocks away from a half-second rollover bit 11-8 amask<3:0>: alarm mask configuration bits (2) 0000 = every half-second 0001 = every second 0010 = every 10 seconds 0011 = every minute 0100 = every 10 minutes 0101 = every hour 0110 = once a day 0111 = once a week 1000 = once a month 1001 = once a year (except when configured for february 29, once every four years) 1010 = reserved 1011 = reserved 11xx = reserved note 1: hardware clears the alrmen bit anytime the alarm event occurs, when arpt<7: 0> = 00 and chime = 0 . 2: this field should not be written when the rtcc on bit = 1 (rtccon<15>) and alrmsync = 1 . note: this register is reset only on a power-on reset (por).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 396 ? 2015-2016 microchip technology inc. bit 7-0 arpt<7:0>: alarm repeat counter value bits (2) 11111111 = alarm will trigger 256 times 00000000 = alarm will trigger one time the counter decrements on any alarm event. the counter only rolls over from 0x00 to 0xff if chime = 1 . register 25-2: rtcalrm: real-time clock alarm control register (continued) note 1: hardware clears the alrmen bit anytime the alarm event occurs, when arpt<7: 0> = 00 and chime = 0 . 2: this field should not be written when the rtcc on bit = 1 (rtccon<15>) and alrmsync = 1 . note: this register is reset only on a power-on reset (por).
? 2015-2016 microchip technology inc. ds60001320d-page 397 pic32mz embedded connectivity with floating point unit (ef) family register 25-3: rtctime: real-time clock time value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hr10<3:0> hr01<3:0> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x min10<3:0> min01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sec10<3:0> sec01<3:0> 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-28 hr10<3:0>: binary-coded decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 hr01<3:0>: binary-coded decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 min10<3:0>: binary-coded decimal value of minutes bits, 10 digits; contains a value from 0 t o 5 bit 19-16 min01<3:0>: binary-coded decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 sec10<3:0>: binary-coded decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 sec01<3:0>: binary-coded decimal value of seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 unimplemented: read as 0 note: this register is only writable when rtcwren = 1 (rtccon<3>).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 398 ? 2015-2016 microchip technology inc. register 25-4: rtcdate: real-time clock date value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x year10<3:0> year01<3:0> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x month10<3:0> month01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x day10<3:0> day01<3:0> 7:0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x wday01<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-28 year10<3:0>: binary-coded decimal value of years bits, 10 digits bit 27-24 year01<3:0>: binary-coded decimal value of years bits, 1 digit bit 23-20 month10<3:0>: binary-coded decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 month01<3:0>: binary-coded decimal value of months bits, 1 digit; contains a value from 0 to 9 bit 15-12 day10<3:0>: binary-coded decimal value of days bits, 10 digits; contains a value from 0 to 3 bit 11-8 day01<3:0>: binary-coded decimal value of days bits, 1 digit; contains a value from 0 to 9 bit 7-4 unimplemented: read as 0 bit 3-0 wday01<3:0>: binary-coded decimal value of weekdays bits,1 digit; contains a value from 0 to 6 note: this register is only writable when rtcwren = 1 (rtccon<3>).
? 2015-2016 microchip technology inc. ds60001320d-page 399 pic32mz embedded connectivity with floating point unit (ef) family register 25-5: alrmtime: alarm time value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hr10<3:0> hr01<3:0> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x min10<3:0> min01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sec10<3:0> sec01<3:0> 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-28 hr10<3:0>: binary coded decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 hr01<3:0>: binary coded decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 min10<3:0>: binary coded decimal value of minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 min01<3:0>: binary coded decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 sec10<3:0>: binary coded decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 sec01<3:0>: binary coded decimal value of seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 unimplemented: read as 0
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 400 ? 2015-2016 microchip technology inc. register 25-6: alrmdate: alarm date value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x month10<3:0> month01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x day10<1:0> day01<3:0> 7:0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x wday01<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as 0 bit 23-20 month10<3:0>: binary coded decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 month01<3:0>: binary coded decimal value of months bits, 1 digit; contains a value from 0 to 9 bit 15-12 day10<3:0>: binary coded decimal value of days bits, 10 digits; contains a value from 0 t o 3 bit 11-8 day01<3:0>: binary coded decimal value of days bits, 1 digit; contains a value from 0 to 9 bit 7-4 unimplemented: read as 0 bit 3-0 wday01<3:0>: binary coded decimal value of weekdays bits, 1 digit; contains a value from 0 to 6
? 2015-2016 microchip technology inc. ds60001320d-page 401 pic32mz embedded connectivity with floating point unit (ef) family 26.0 crypto engine the crypto engine is intended to accelerate applica - tions that need cryptographic functions. by execut - ing these functions in the hardware module, software overhead is reduced and actions, such as encryp - tion, decryption, and authentication can execute much more quickly. the crypto engine uses an internal descriptor-based dma for efficient programming of the security associ - ation data and packet pointers (allowing scatter/ gather data fetching). an intelligent state machine schedules the crypto engines based on the protocol selection and packet boundaries. the hardware engines can perform the encryption and authentica - tion in sequence or in parallel. the following are key features of the crypto engine: bulk ciphers and hash engines integrated dma to off-load processing: - buffer descriptor-based - secure association per buffer descriptor some functions can execute in parallel bulk ciphers that are handled by the crypto engine include: aes: - 128-bit, 192-bit, and 256-bit key sizes - cbc, ecb, ctr, cfb, and ofb modes des/tdes: - cbc, ecb, cfb, and ofb modes authentication engines that are available through the crypto engine include: sha-1 sha-256 md-5 aes-gcm hmac operation (for all authentication engines) the rate of data that can be processed by the crypto engine depends on these factors: which engine is in use whether the engines are used in parallel or in series the demands on source and destination memories by other parts of the system (i.e., cpu, dma, etc.) the speed of pbclk5, which drives the crypto engine table 26-1 shows typical performance for various engines. table 26-1: crypto engine performance figure 26-1: crypto engine block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 49. crypto engine (ce) and random number generator (rng) (ds60001246) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). engine/ algorithm performance factor (mbps/mhz) maximum mbps (pbclk5 = 100 mhz) des 14.4 1440 tdes 6.6 660 aes-128 9.0 900 aes-192 7.9 790 aes-256 7.2 720 md5 15.6 1560 sha-1 13.2 1320 sha-256 9.3 930 dma controller system inb fifo outb fifo crypto fsm packet rd packet wr aes tdes sha-1 md5 local bus sfr system bus bus pbclk5 sha-256
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 402 ? 2015-2016 microchip technology inc. 26.1 crypto engine control registers table 26-2: crypto engine register map virtual address (bf8e_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5000 cever 31:16 revision<7:0> version<7:0> 0000 15:0 id<15:0> 0000 5004 cecon 31:16 0000 15:0 swapoen swrst swapen bdpchst bdpplen dmaen 0000 5008 cebdaddr 31:16 bdpaddr<31:0> 0000 15:0 0000 500c cebdpaddr 31:16 baseaddr<31:0> 0000 15:0 0000 5010 cestat 31:16 errmode<2:0> errop<2:0> errphase<1:0> bdstate<3:0> start active 0000 15:0 bdctrl<15:0> 0000 5014 ceintsrc 31:16 0000 15:0 areif pktif cbdif pendif 0000 5018 ceinten 31:16 0000 15:0 areie pktie cbdie pendie 0000 501c cepollcon 31:16 0000 15:0 bdpplcon<15:0> 0000 5020 cehdlen 31:16 0000 15:0 hdrlen<7:0> 0000 5024 cetrllen 31:16 0000 15:0 trlrlen<7:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal.
? 2015-2016 microchip technology inc. ds60001320d-page 403 pic32mz embedded connectivity with floating point unit (ef) family register 26-1: cever: crypto engine revision, version, and id register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 revision<7:0> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 version<7:0> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 id<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 id<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 revision<7:0>: crypto engine revision bits bit 23-16 version<7:0>: crypto engine version bits bit 15-0 id<15:0>: crypto engine identification bits
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 404 ? 2015-2016 microchip technology inc. register 26-2: cecon: crypto engine control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-0 r/w-0, hc r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 swapoen swrst swapen bdpchst bdpplen dmaen legend: hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as 0 bit 7 swapoen: swap output data enable bit 1 = output data is byte swapped when written by dedicated dma 0 = output data is not byte swapped when written by dedicated dma bit 6 swrst: software reset bit 1 = initiate a software reset of the crypto engine 0 = normal operation bit 5 swapen: input data swap enable bit 1 = input data is byte swapped when read by dedicated dma 0 = input data is not byte swapped when read by dedicated dma bit 4-3 unimplemented: read as 0 bit 2 bdpchst: buffer descriptor processor (bdp) fetch enable bit this bit should be enabled only after all dma descriptor programming is completed. 1 = bdp descriptor fetch is enabled 0 = bdp descriptor fetch is disabled bit 1 bdpplen: buffer descriptor processor poll enable bit this bit should be enabled only after all dma descriptor programming is completed. 1 = poll for descriptor until valid bit is set 0 = do not poll bit 0 dmaen: dma enable bit 1 = crypto engine dma is enabled 0 = crypto engine dma is disabled
? 2015-2016 microchip technology inc. ds60001320d-page 405 pic32mz embedded connectivity with floating point unit (ef) family register 26-3: cebdaddr: crypto engine buffer descriptor register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bdpaddr<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bdpaddr<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bdpaddr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bdpaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 bdpaddr<31:0>: current buffer descriptor process address status bits these bits contain the current descriptor address that is being processed by the buffer descriptor processor (bdp). register 26-4: cebdpaddr: crypto engine buffer descriptor processor register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 baseaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 baseaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 baseaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 baseaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 baseaddr<31:0>: buffer descriptor base address bits these bits contain the physical address of the first buffer descriptor in the buffer descriptor chain. whe n enabled, the crypto dma begins fetching buffer descriptors from this address.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 406 ? 2015-2016 microchip technology inc. register 26-5: cestat: crypto engine status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 errmode<2:0> errop<2:0> errphase<1:0> 23:16 u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 bdstate<3:0> start active 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bdctrl<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bdctrl<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 errmode<2:0>: internal error mode status bits 111 = reserved 110 = reserved 101 = reserved 100 = reserved 011 = cek operation 010 = kek operation 001 = preboot authentication 000 = normal operation bit 28-26 errop<2:0>: internal error operation status bits 111 = reserved 110 = reserved 101 = reserved 100 = authentication 011 = reserved 010 = decryption 001 = encryption 000 = reserved bit 25-24 errphase<1:0>: internal error phase of dma status bits 11 = destination data 10 = source data 01 = security association (sa) access 00 = buffer descriptor (bd) access bit 23-22 unimplemented: read as 0 bit 21-18 bdstate<3:0>: buffer descriptor processor state status bits the current state of the bdp: 1111 = reserved 0111 = reserved 0110 = sa fetch 0101 = fetch bdp is disabled 0100 = descriptor is done 0011 = data phase 0010 = bdp is loading 0001 = descriptor fetch request is pending 0000 = bdp is idle bit 17 start: dma start status bit 1 = dma start has occurred 0 = dma start has not occurred
? 2015-2016 microchip technology inc. ds60001320d-page 407 pic32mz embedded connectivity with floating point unit (ef) family bit 16 active: buffer descriptor processor status bit 1 = bdp is active 0 = bdp is idle bit 15-0 bdctrl<15:0>: descriptor control word status bits these bits contain the control word for the current buffer descriptor. register 26-5: cestat: crypto engine status register (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 408 ? 2015-2016 microchip technology inc. register 26-6: ceintsrc: crypto engine interrupt source register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 areif pktif cbdif pendif legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as 0 bit 3 areif: access response error interrupt bit 1 = error occurred trying to access memory outside the crypto engine 0 = no error has occurred bit 2 pktif: dma packet completion interrupt status bit 1 = dma packet was completed 0 = dma packet was not completed bit 1 cbdif: bd transmit status bit 1 = last bd transmit was processed 0 = last bd transmit has not been processed bit 0 pendif: crypto engine interrupt pending status bit 1 = crypto engine interrupt is pending (this value is the result of an or of all interrupts in the crypto engin e) 0 = crypto engine interrupt is not pending
? 2015-2016 microchip technology inc. ds60001320d-page 409 pic32mz embedded connectivity with floating point unit (ef) family register 26-7: ceinten: crypto en gine interrupt enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 areie pktie bdpie pendie (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as 0 bit 3 areie: access response error interrupt enable bit 1 = access response error interrupts are enabled 0 = access response error interrupts are not enabled bit 2 pktie: dma packet completion interrupt enable bit 1 = dma packet completion interrupts are enabled 0 = dma packet completion interrupts are not enabled bit 1 bdpie: dma buffer descriptor processor interrupt enable bit 1 = bdp interrupts are enabled 0 = bdp interrupts are not enabled bit 0 pendie: master interrupt enable bit (1) 1 = crypto engine interrupts are enabled 0 = crypto engine interrupts are not enabled note 1: the pendie bit is a global enable bit and must be enabled together with the other interrupts desired.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 410 ? 2015-2016 microchip technology inc. register 26-8: cepollcon: crypto engine poll control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdpplcon<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdpplcon<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 bdpplcon<15:0>: buffer descriptor processor poll control bits these bits determine the number of sysclk cycles that the crypto dma would wait before refetching the descriptor control word if the buffer descriptor fetched was disabled.
? 2015-2016 microchip technology inc. ds60001320d-page 411 pic32mz embedded connectivity with floating point unit (ef) family register 26-9: cehdlen: crypto engine header length register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 hdrlen<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as 0 bit 7-0 hdrlen<7:0>: dma header length bits for every packet, skip this length of locations and start filling the data. register 26-10: cetrllen: crypto engine trailer length register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trlrlen<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as 0 bit 7-0 trlrlen<7:0>: dma trailer length bits for every packet, skip this length of locations at the end of the current packet and start putting the next packet.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 412 ? 2015-2016 microchip technology inc. 26.2 crypto engine buffer descriptors host software creates a linked list of buffer descriptors and the hardware updates them. tab le 26-3 provides a list of the crypto engine buffer descriptors, followed by format descriptions of each buffer descriptor (see figure 26-2 through figure 26-9 ). table 26-3: crypto engine buffer descriptors name (see note 1) bit 31/2315/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bd_ctrl 31:24 desc_en cry_mode<2:0> 23:16 sa_fetch_en last_bd lifm pkt_int_en cbd_int_en 15:8 bd_buflen<15:8> 7:0 bd_buflen<7:0> bd_sa_addr 31:24 bd_saaddr<31:24> 23:16 bd_saaddr<23:16> 15:8 bd_saaddr<15:8> 7:0 bd_saadr<7:0> bd_scraddr 31:24 bd_srcaddr<31:24> 23:16 bd_srcaddr<23:16> 15:8 bd_srcaddr<15:8> 7:0 bd_srcaddr<7:0> bd_dstaddr 31:24 bd_dstaddr<31:24> 23:16 bd_dstaddr<23:16> 15:8 bd_dstaddr<15:8> 7:0 bd_dstaddr<7:0> bd_nxtptr 31:24 bd_nxtaddr<31:24> 23:16 bd_nxtaddr<23:16> 15:8 bd_nxtaddr<15:8> 7:0 bd_nxtaddr<7:0> bd_updptr 31:24 bd_updaddr<31:24> 23:16 bd_updaddr<23:16> 15:8 bd_updaddr<15:8> 7:0 bd_updaddr<7:0> bd_msg_len 31:24 msg_length<31:24> 23:16 msg_length<23:16> 15:8 msg_length<15:8> 7:0 msg_length<7:0> bd_enc_off 31:24 encr_offset<31:24> 23:16 encr_offset<23:16> 15:8 encr_offset<15:8> 7:0 encr_offset<7:0> note 1: the buffer descriptor must be allocated in memory on a 64-bit boundary.
? 2015-2016 microchip technology inc. ds60001320d-page 413 pic32mz embedded connectivity with floating point unit (ef) family figure 26-2: format of bd_ctrl figure 26-3: format of bd_saddr bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31-24 desc_en cry_mode<2:0> 23-16 sa_ fetch_en last_bd lifm pkt_ int_en cbd_ int_en 15-8 bd_buflen<15:8> 7-0 bd_buflen<7:0> bit 31 desc_en : descriptor enable 1 = the descriptor is owned by hardware. after processing the bd, hardware reset s this bit to 0 . 0 = the descriptor is owned by software bit 30 unimplemented: must be written as 0 bit 29-27 cry_mode<2:0>: crypto mode 111 = reserved 110 = reserved 101 = reserved 100 = reserved 011 = cek operation 010 = kek operation 001 = preboot authentication 000 = normal operation bit 22 sa_fetch_en: fetch security association from external memory 1 = fetch sa from the sa pointer. this bit needs to be set to 1 for every new packet. 0 = use current fetched sa or the internal sa bit 21-20 unimplemented: must be written as 0 bit 19 last_bd: last buffer descriptors 1 = last buffer descriptor in the chain 0 = more buffer descriptors in the chain after the last bd, the cebdaddr goes to the base address in cebdpaddr. bit 18 lifm: last in frame in case of receive packets (from h/w-> host), this field is filled by the hardware to i ndicate whether the packet goes across multiple buffer descriptors. in case of transmit packets (from host -> h/w ), this field indicates whether this bd is the last in the frame. bit 17 pkt_int_en: packet interrupt enable generate an interrupt after processing the current buffer descriptor, if it is the end of the packet. bit 16 cbd_int_en: cbd interrupt enable generate an interrupt after processing the current buffer descriptor. bit 15-0 bd_buflen<15:0>: buffer descriptor length this field contains the length of the buffer and is updated with the actual length filled by the receiver. bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31-24 bd_saaddr<31:24> 23-16 bd_saaddr<23:16> 15-8 bd_saaddr<15:8> 7-0 bd_saaddr<7:0> bit 31-0 bd_saaddr<31:0>: security association ip session address the sessions sa pointer has the keys and iv values.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 414 ? 2015-2016 microchip technology inc. figure 26-4: format of bd_srcaddr figure 26-5: format of bd_dstaddr figure 26-6: format of bd_nxtaddr bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31-24 bd_scraddr<31:24> 23-16 bd_scraddr<23:16> 15-8 bd_scraddr<15:8> 7-0 bd_scraddr<7:0> bit 31-0 bd_scraddr: buffer source address the source address of the buffer that needs to be passed through the pe-crdma for e ncryption or authentication. this address must be on a 32-bit boundary. bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31-24 bd_dstaddr<31:24> 23-16 bd_dstaddr<23:16> 15-8 bd_dstaddr<15:8> 7-0 bd_dstaddr<7:0> bit 31-0 bd_dstaddr: buffer destination address the destination address of the buffer that needs to be passed thro ugh the pe-crdma for encryption or authentication. this address must be on a 32-bit boundary. bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31-24 bd_nxtaddr<31:24> 23-16 bd_nxtaddr<23:16> 15-8 bd_nxtaddr<15:8> 7-0 bd_nxtaddr<7:0> bit 31-0 bd_nxtaddr: next bd pointer address has next buffer descriptor the next buffer can be a next segment of the previous buffer or a new packet.
? 2015-2016 microchip technology inc. ds60001320d-page 415 pic32mz embedded connectivity with floating point unit (ef) family figure 26-7: format of bd_updptr figure 26-8: format of bd_msg_len figure 26-9: format of bd_enc_off bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31-24 bd_updaddr<31:24> 23-16 bd_updaddr<23:16> 15-8 bd_updaddr<15:8> 7-0 bd_updaddr<7:0> bit 31-0 bd_updaddr: upd address location the update address has the location where the crdma results are posted . the updated results are the icv values, key output values as needed. bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31-24 msg_length<31:24> 23-16 msg_length<23:16> 15-8 msg_length<15:8> 7-0 msg_length<7:0> bit 31-0 msg_length: total message length total message length for the hash and hmac algorithms in bytes. total number of crypto bytes in case of gcm algorithm (len-c). bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31-24 encr_offset<31:24> 23-16 encr_offset<23:16> 15-8 encr_offset<15:8> 7-0 encr_offset<7:0> bit 31-0 encr_offset: encryption offset encryption offset for the multi-task test cases (both encryption and authentication). the number of aad bytes in the case of gcm algorithm (len-a).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 416 ? 2015-2016 microchip technology inc. 26.3 security association structure table 26-4 shows the security association structure. the crypto engine uses the security association to determine the settings for processing a buffer descrip - tor processor. the security association contains: which algorithm to use whether to use engines in parallel (for both authentication and encryption/decryption) the size of the key authentication key encryption/decryption key authentication initialization vector (iv) encryption iv table 26-4: crypto engine security association structure name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 sa_ctrl 31:24 v e r i f y n o _ r xo r _ e ni c v o n l yi r f l a g 23:16 lnc loadiv fb flags algo<6> 15:8 algo<5:0> enctype keysize<1> 7:0 keysize<0> multitask<2:0> cryptoalgo<3:0> sa_authkey1 31:24 authkey<31:24> 23:16 authkey<23:16> 15:8 authkey<15:8> 7:0 authkey<7:0> sa_authkey2 31:24 authkey<31:24> 23:16 authkey<23:16> 15:8 authkey<15:8> 7:0 authkey<7:0> sa_authkey3 31:24 authkey<31:24> 23:16 authkey<23:16> 15:8 authkey<15:8> 7:0 authkey<7:0> sa_authkey4 31:24 authkey<31:24> 23:16 authkey<23:16> 15:8 authkey<15:8> 7:0 authkey<7:0> sa_authkey5 31:24 authkey<31:24> 23:16 authkey<23:16> 15:8 authkey<15:8> 7:0 authkey<7:0> sa_authkey6 31:24 authkey<31:24> 23:16 authkey<23:16> 15:8 authkey<15:8> 7:0 authkey<7:0> sa_authkey7 31:24 authkey<31:24> 23:16 authkey<23:16> 15:8 authkey<15:8> 7:0 authkey<7:0> sa_authkey8 31:24 authkey<31:24> 23:16 authkey<23:16> 15:8 authkey<15:8> 7:0 authkey<7:0> sa_enckey1 31:24 enckey<31:24> 23:16 enckey<23:16> 15:8 enckey<15:8> 7:0 enckey<7:0> sa_enckey2 31:24 enckey<31:24> 23:16 enckey<23:16>
? 2015-2016 microchip technology inc. ds60001320d-page 417 pic32mz embedded connectivity with floating point unit (ef) family 15:8 enckey<15:8> 7:0 enckey<7:0> sa_enckey3 31:24 enckey<31:24> 23:16 enckey<23:16> 15:8 enckey<15:8> 7:0 enckey<7:0> sa_enckey4 31:24 enckey<31:24> 23:16 enckey<23:16> 15:8 enckey<15:8> 7:0 enckey<7:0> sa_enckey5 31:24 enckey<31:24> 23:16 enckey<23:16> 15:8 enckey<15:8> 7:0 enckey<7:0> sa_enckey6 31:24 enckey<31:24> 23:16 enckey<23:16> 15:8 enckey<15:8> 7:0 enckey<7:0> sa_enckey7 31:24 enckey<31:24> 23:16 enckey<23:16> 15:8 enckey<15:8> 7:0 enckey<7:0> sa_enckey8 31:24 enckey<31:24> 23:16 enckey<23:16> 15:8 enckey<15:8> 7:0 enckey<7:0> sa_authiv1 31:24 authiv<31:24> 23:16 authiv<23:16> 15:8 authiv<15:8> 7:0 authiv<7:0> sa_authiv2 31:24 authiv<31:24> 23:16 authiv<23:16> 15:8 authiv<15:8> 7:0 authiv<7:0> sa_authiv3 31:24 authiv<31:24> 23:16 authiv<23:16> 15:8 authiv<15:8> 7:0 authiv<7:0> sa_authiv4 31:24 authiv<31:24> 23:16 authiv<23:16> 15:8 authiv<15:8> 7:0 authiv<7:0> sa_authiv5 31:24 authiv<31:24> 23:16 authiv<23:16> 15:8 authiv<15:8> 7:0 authiv<7:0> sa_authiv6 31:24 authiv<31:24> 23:16 authiv<23:16> 15:8 authiv<15:8> 7:0 authiv<7:0> sa_authiv7 31:24 authiv<31:24> 23:16 authiv<23:16> 15:8 authiv<15:8> 7:0 authiv<7:0> sa_authiv8 31:24 authiv<31:24> 23:16 authiv<23:16> 15:8 authiv<15:8> 7:0 authiv<7:0> table 26-4: crypto engine security association structure (continued) name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 418 ? 2015-2016 microchip technology inc. sa_enciv1 31:24 enciv<31:24> 23:16 enciv<23:16> 15:8 enciv<15:8> 7:0 enciv<7:0> sa_enciv2 31:24 enciv<31:24> 23:16 enciv<23:16> 15:8 enciv<15:8> 7:0 enciv<7:0> sa_enciv3 31:24 enciv<31:24> 23:16 enciv<23:16> 15:8 enciv<15:8> 7:0 enciv<7:0> sa_enciv4 31:24 enciv<31:24> 23:16 enciv<23:16> 15:8 enciv<15:8> 7:0 enciv<7:0> table 26-4: crypto engine security association structure (continued) name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0
? 2015-2016 microchip technology inc. ds60001320d-page 419 pic32mz embedded connectivity with floating point unit (ef) family figure 26-10 shows the security association control word structure. the crypto engine fetches different structures for dif - ferent flows and ensures that hardware fetches mini - mum words from sa required for processing. the structure is ready for hardware optimal data fetches. figure 26-10: format of sa_ctrl bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31-24 v e r i f y no_rx or_en icvonly irflag 23-16 lnc loadiv fb flags algo<6> 15-8 algo<5:0> enc key size<1> 7-0 key size<0> multitask<2:0> cryptoalgo<3:0> bit 31-30 reserved: do not use bit 29 verify: nist procedure verification setting 1 = nist procedures are to be used 0 = do not use nist procedures bit 28 reserved: do not use bit 27 no_rx: receive dma control setting 1 = only calculate icv for authentication calculations 0 = normal processing bit 26 or_en: or register bits enable setting 1 = or the register bits with the internal value of the csr register 0 = normal processing bit 25 icvonly: incomplete check value only flag this affects the sha-1 algorithm only. it has no effect on the aes algorithm. 1 = only three words of the hmac result are available 0 = all results from the hmac result are available bit 24 irflag: immediate result of hash setting this bit is set when the immediate result for hashing is requested. 1 = save the immediate result for hashing 0 = do not save the immediate result bit 23 lnc: load new keys setting 1 = load a new set of keys for encryption and authentication 0 = do not load new keys bit 22 loadiv: load iv setting 1 = load the iv from this security association 0 = use the next iv bit 21 fb: first block setting this bit indicates that this is the first block of data to feed the iv value. 1 = indicates this is the first block of data 0 = indicates this is not the first block of data bit 20 flags: incoming/outgoing flow setting 1 = security association is associated with an outgoing flow 0 = security association is associated with an incoming flow bit 19-17 reserved: do not use
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 420 ? 2015-2016 microchip technology inc. figure 26-10: format of sa_ctrl (continued) bit 16-10 algo<6:0>: type of algorithm to use 1xxxxxx = hmac 1 x1xxxxx = sha-256 xx1xxxx = sha1 xxx1xxx = md5 xxxx1xx = aes xxxxx1x = tdes xxxxxx1 = des bit 9 enc: type of encryption setting 1 = encryption 0 = decryption bit 8-7 keysize<1:0>: size of keys in sa_authkeyx or sa_enckeyx 11 = reserved; do not use 10 = 256 bits 01 = 192 bits 00 = 128 bits (1) bit 6-4 multitask<2:0>: how to combine parallel operations in the crypto engine 111 = parallel pass (decrypt and authenticate incoming data in parallel) 101 = pipe pass (encrypt the incoming data, and then perform authentication on the encrypted data) 011 = reserved 010 = reserved 001 = reserved 000 = encryption or authentication or decryption (no pass) bit 3-0 cryptoalgo<3:0>: mode of operation for the crypto algorithm 1111 = reserved 1110 = aes_gcm (for aes processing) 1101 = rctr (for aes processing) 1100 = rcbc_mac (for aes processing) 1011 = rofb (for aes processing) 1010 = rcfb (for aes processing) 1001 = rcbc (for aes processing) 1000 = recb (for aes processing) 0111 = tofb (for triple-des processing) 0110 = tcfb (for triple-des processing) 0101 = tcbc (for triple-des processing) 0100 = tecb (for triple-des processing) 0011 = ofb (for des processing) 0010 = cfb (for des processing) 0001 = cbc (for des processing) 0000 = ecb (for des processing) note 1: this setting does not alter the size of sa_authkeyx or sa_enckeyx in the security association, only the number of bits of sa_authkeyx and sa_enckeyx that are used.
? 2015-2016 microchip technology inc. ds60001320d-page 421 pic32mz embedded connectivity with floating point unit (ef) family 27.0 random number generator (rng) the random number generator (rng) core imple - ments a thermal noise-based, true random number generator (trng) and a cryptographically secure pseudo-random number generator (prng). the trng uses multiple ring oscillators and the inher - ent thermal noise of integrated circuits to generate true random numbers that can initialize the prng. the prng is a flexible lsfr, which is capable of manifesting a maximal length lfsr of up to 64-bits. the following are some of the key features of the random number generator: trng: - up to 25 mbps of random bits - multi-ring oscillator based design - built-in bias corrector prng: -lsfr-based - up to 64-bit polynomial length - programmable polynomial - trng can be seed value table 27-1: random number generator block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive refer - ence source. to complement the informa - tion in this data sheet, refer to section 49. crypto engine (ce) and random number generator (rng) (ds60001246) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). system bus prng sfr edge comparator ring ring bias corrector trng oscillator oscillator pbclk5
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 422 ? 2015-2016 microchip technology inc. 27.1 rng control registers table 27-2: random number generator (rng) register map virtual address (bf8e_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 rngver 31:16 id<15:0> xxxx 15:0 version<7:0> revision<7:0> xxxx 6004 rngcon 31:16 0000 15:0 load trngmode cont prngen trngen plen<7:0> 0064 6008 rngpoly1 31:16 poly<31:0> ffff 15:0 0000 600c rngpoly2 31:16 poly<31:0> ffff 15:0 0000 6010 rngnumgen1 31:16 rng<31:0> ffff 15:0 ffff 6014 rngnumgen2 31:16 rng<31:0> ffff 15:0 ffff 6018 rngseed1 31:16 seed<31:0> 0000 15:0 0000 601c rngseed2 31:16 seed<31:0> 0000 15:0 0000 6020 rngcnt 31:16 0000 15:0 rcnt<6:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal.
? 2015-2016 microchip technology inc. ds60001320d-page 423 pic32mz embedded connectivity with floating point unit (ef) family register 27-1: rngver: random num ber generator version register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 id<15:8> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 id<7:0> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 version<7:0> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 revision<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 id<15:0>: block identification bits bit 15-8 version<7:0>: block version bits bit 7-0 revision<7:0>: block revision bits
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 424 ? 2015-2016 microchip technology inc. register 27-2: rngcon: random number generator control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 load trngmode cont prngen trngen 7:0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 plen<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as 0 bit 12 load: device select bit this bit is self-clearing and is used to load the seed from the trng (i.e., the random value) as a seed to the prng. bit 11 trngmode: trng mode selection bit 1 = use ring oscillators with bias corrector 0 = use ring oscillators with xor tree note: enabling this bit will generate numbers with a more even distribution of randomness. bit 10 cont: prng number shift enable bit 1 = the prng random number is shifted every cycle 0 = the prng random number is shifted when the previous value is removed bit 9 prngen: prng operation enable bit 1 = prng operation is enabled 0 = prng operation is not enabled bit 8 trngen: trng operation enable bit 1 = trng operation is enabled 0 = trng operation is not enabled bit 7-0 plen<7:0>: prng polynomial length bits these bits contain the length of the polynomial used for the prng.
? 2015-2016 microchip technology inc. ds60001320d-page 425 pic32mz embedded connectivity with floating point unit (ef) family register 27-3: rngpolyx: random number generator polynomial register x ? (x = 1 or 2) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 poly<31:24> 23:16 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 poly<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 poly<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 poly<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 poly<31:0>: prng lfsr polynomial msb/lsb bits (rngpoly1 = lsb, rngpoly2 = msb) register 27-4: rngnumgenx: random number ge nerator register x (x = 1 or 2) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rng<31:24> 23:16 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rng<23:16> 15:8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rng<15:8> 7:0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rng<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 rng<31:0>: current prng msb/lsb value bits (rngnumgen1 = lsb, rngnumgen2 = msb)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 426 ? 2015-2016 microchip technology inc. register 27-5: rngseedx: true random number generator seed register x ? (x = 1 or 2) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 seed<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 seed<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 seed<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 seed<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 seed<31:0>: trng msb/lsb value bits (rngseed1 = lsb, rngseed2 = msb) register 27-6: rngcnt: true random number generator count register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rcnt<6:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-7 unimplemented: read as 0 bit 6-0 rcnt<6:0>: number of valid trng msb 32 bits
? 2015-2016 microchip technology inc. ds60001320d-page 427 pic32mz embedded connectivity with floating point unit (ef) family 28.0 12-bit high-speed successive approximation register (sar) analog-to- digital converter (adc) the 12-bit high-speed successive approximation register (sar) analog-to-digital converter (adc) includes the following key features: 12-bit resolution six adc modules with dedicated sample and hold (s&h) circuits two dedicated adc modules can be combined in turbo mode to provide double conversion rate (clock sources for combined adc modules must be synchronous) single-ended and/or differential inputs can operate during sleep mode supports touch sense applications six digital comparators six digital filters supporting two modes: - oversampling mode - averaging mode early interrupt generation resulting in faster processing of converted data designed for motor control, power conversion, and general purpose applications a simplified block diagram of the adc module is illustrated in figure 28-1 . the 12-bit hs sar adc has up to five dedicated adc modules (adc0-adc4) and one shared adc module (adc7). the dedicated adc modules use a single input (or its alternate) and are intended for high-speed and precise sampling of time-sensitive or transient inputs. the the shared adc module incorporates a multiplexer on the input to facilitate a larger group of inputs, with slower sampling, and provides flexible automated scanning option through the input scan logic. for each adc module, the analog inputs are connected to the s&h capacitor. the clock, sampling time, and output data resolution for each adc module can be set independently. the adc module performs the conversion of the input analog signal based on the configurations set in the registers. when conversion is complete, the final result is stored in the result buffer for the specific analog input and is passed to the digital filter and digital comparator if configured to use data from this particular sample. input to adcx mapping is illustrated in figure 28-2 . the throughput rate (see table 37-39 in 37.0 electrical characteristics ) is calculated, as shown in equation 28-1 . equation 28-1: adc throughput rate note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 22. 12-bit high-speed successive approximation register (sar) analog-to-digital converter (adc) (ds60001344) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). note 1: prior to enabling the adc module, the user application must copy the adc cali- bration data (devadc0-devadc4, devadc7; see register 34-13 ) from the configuration memory into the adc con- figuration registers (adc0cfg- adc4cfg, adc7cfg). 2: configure the aicpmpen (adc- con1<12>) and ioancpen (cfg- con<7>) bits to 0 if vdd >= 2.5v. set the aicpmpen and ioancpen bits to 1 if vdd < 2.5v. t ad = the frequency of the individual adc module ftp t ad t samp t conv + ?? -------------------------------------------- = where,
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 428 ? 2015-2016 microchip technology inc. figure 28-1: adc block diagram adc0 adc7 av dd av ss v ref +v ref - vrefsel<2:0> v refh v refl adcsel<1:0> conclkdiv<5:0> t q adcdiv<6:0> (adcxtime<22:16>) adcdiv<6:0> (adccon2<6:0>) t ad0 -t ad4 t ad7 adcdata0 ... adcdata44 digital filter digital comparator interrupt/event capacitive voltage divider (cvd) interrupt/event triggers, turbo channel, scan control logic trigger status and control registers adc4 sh0alt<1:0> (adctrgmode<17:16>) an5 v refl 01 diff0<1> (adcimcon1<1>) an0 an10 v refl 01 diffx<1> x = 5 to 44 (adcimcony) y = 1 to 3, z = 1 to 31 (odd numbers) sh4alt<1:0> (adctrgmode<25:24>) an9 v refl 01 diff4<1> (adcimcon1<1>) an42 iv temp (an44) iv ref (an43) an41 an5 cvd capacitor t clk an45 n/c n/c 0001 10 11 an49 n/c n/c 0001 10 11 system bus an4 interrupt data 01 10 11 00 fifo
? 2015-2016 microchip technology inc. ds60001320d-page 429 pic32mz embedded connectivity with floating point unit (ef) family figure 28-2: s&h block diagram an3 an48 an8 n/c 11 01 00 n/c 10 sh3alt<1:0> (adctrgmode<23:22) v refl 1 0 an0 an45 an5 n/c 11 01 00 n/c 10 sh0alt<1:0> (adctrgmode<17:16) v refl 1 0 an4 an49 an9 n/c 11 01 00 n/c 10 sh4alt<1:0> (adctrgmode<25:24) v refl 1 0 an1 an46 an6 n/c 11 01 00 n/c 10 sh1alt<1:0> (adctrgmode<19:18) sar v refl 1 0 an2 an47 an7 n/c 11 01 00 n/c 10 sh2alt<1:0> (adctrgmode<21:20) v refl 1 0 an10 v refl 1 0 diffx<1> an5 an6 an41 an42 iv ref (an43) iv temp (an44) diff3<1> (adcimcon1<7>) diff0<1> (adcimcon1<1>) diff4<1> (adcimcon1<9>) diff1<1> (adcimcon1<3>) diff2<1> (adcimcon1<5>) adc1 adc2 sar adc0 sar adc3 adc4 sar sar adc7 sar cvd capacitor cvden (adccon1<11>) cvdcpl<2:0> (adccon2<28:26>)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 430 ? 2015-2016 microchip technology inc. figure 28-3: fifo block diagram fen (adcfstat<31>) fifo (16 words) adcfifo data<31:0> adcid<2:0> (adcfstat<2:0>) adcx id adcx id converted data adc4 adc4en (adcfstat<28>) adc0 adc0en (adcfstat<24>) if data available in fifo frdy (adcfstat<22>) fien (adcfstat<23>) interrupt fcnt<7:0> (adcfstat<15:8>) number of data in fifo
? 2015-2016 microchip technology inc. ds60001320d-page 431 pic32mz embedded connectivity with floating point unit (ef) family 28.1 adc control registers table 28-1: adc register map virtual address (bf84_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 b000 adccon1 31:16 trben trberr trbmst<2:0> trbslv<2:0> fract selres<1:0> strgsrc<4:0> 0060 15:0 on sidl aicpmpen cvden fssclken fspbclken irqvs<2:0> strglvl 1000 b004 adccon2 31:16 bgvrrdy refflt eosrdy cvdcpl<2:0> samc<9:0> 0000 15:0 bgvrien reffltien eosien adceiovr adceis<2:0> adcdiv<6:0> 0000 b008 adccon3 31:16 adcsel<1:0> conclkdiv<5:0> digen7 digen4 digen3 digen2 digen1 digen0 0000 15:0 vrefsel<2:0> trgsusp updien updrdy samp rqcnvrt glswtrg gswtrg adinsel<5:0> 0000 b00c adctrgmode 31:16 sh4alt<1:0> sh3alt<1:0> sh2alt<1:0> sh1alt<1:0> sh0alt<1:0> 0000 15:0 strgen4 strgen3 strgen2 strgen1 strgen0 ssampen4 ssampen3 ssampen2 ssampen1 ssampen0 0000 b010 adcimcon1 31:16 diff15 sign15 diff14 sign14 diff13 sign13 diff12 sign12 diff11 sign11 diff10 sign10 diff9 sign9 diff8 sign8 0000 15:0 diff7 sign7 diff6 sign6 diff5 sign5 diff4 sign4 diff3 sign3 diff2 sign2 diff1 sign1 diff0 sign0 0000 b014 adcimcon2 31:16 diff31 (1) sign31 (1) diff30 (1) sign30 (1) diff29 (1) sign29 (1) diff28 (1) sign28 (1) diff27 (1) sign27 (1) diff26 (1) sign26 (1) diff25 (1) sign25 (1) diff24 (1) sign24 (1) 0000 15:0 diff23 (1) sign23 (1) diff22 (1) sign22 (1) diff21 (1) sign21 (1) diff20 (1) sign20 (1) diff19 (1) sign19 (1) diff18 sign18 diff17 sign17 diff16 sign16 0000 b018 adcimcon3 31:16 diff44 sign44 diff43 sign43 diff42 (2) sign42 (2) diff41 (2) sign41 (2) diff40 (2) sign40 (2) 0000 15:0 diff39 (2) sign39 (2) diff38 (2) sign38 (2) diff37 (2) sign37 (2) diff36 (2) sign36 (2) diff35 (2) sign35 (2) diff34 (1) sign34 (1) diff33 (1) sign33 (1) diff32 (1) sign32 (1) 0000 b020 adcgirqen1 31:16 agien31 (1) agien30 (1) agien29 (1) agien28 (1) agien27 (1) agien26 (1) agien25 (1) agien24 (1) agien23 (1) agien22 (1) agien21 (1) agien20 (1) agien19 (1) agien18 agien17 agien16 0000 15:0 agien15 agien14 agien13 agien12 agien11 agien10 agien9 agien8 agien7 agien6 agien5 agien4 agien3 agien2 agien1 agien0 0000 b024 adcgirqen2 31:16 0000 15:0 agien44 agien43 agien42 (2) agien41 (2) agien40 (2) agien39 (2) agien38 (2) agien37 (2) agien36 (2) agien35 (2) agien34 (1) agien33 (1) agien32 (1) 0000 b028 adccss1 31:16 css31 (1) css30 (1) css29 (1) css28 (1) css27 (1) css26 (1) css25 (1) css24 (1) css23 (1) css22 (1) css21 (1) css20 (1) css19 (1) css18 css17 css16 0000 15:0 css15 css14 css13 css12 css11 css10 css9 css8 css7 css6 css5 css4 css3 css2 css1 css0 0000 b02c adccss2 31:16 0000 15:0 css44 css43 css42 (2) css41 (2) css40 (2) css39 (2) css38 (2) css37 (2) css36 (2) css35 (2) css34 (1) css33 (1) css32 (1) 0000 b030 adcdstat1 31:16 ardy31 (1) ardy30 (1) ardy29 (1) ardy28 (1) ardy27 (1) ardy26 (1) ardy25 (1) ardy24 (1) ardy23 (1) ardy22 (1) ardy21 (1) ardy20 (1) ardy19 (1) ardy18 ardy17 ardy16 0000 15:0 ardy15 ardy14 ardy13 ardy12 ardy11 ardy10 ardy9 ardy8 ardy7 ardy6 ardy5 ardy4 ardy3 ardy2 ardy1 ardy0 0000 b034 adcdstat2 31:16 0000 15:0 ardy44 ardy43 ardy42 (2) ardy41 (2) ardy40 (2) ardy39 (2) ardy38 (2) ardy37 (2) ardy36 (2) ardy35 (2) ardy34 (1) ardy33 (1) ardy32 (1) 0000 b038 adccmpen1 31:16 cmpe31 (1) cmpe30 (1) cmpe29 (1) cmpe28 (1) cmpe27 (1) cmpe26 (1) cmpe25 (1) cmpe24 (1) cmpe23 (1) cmpe22 (1) cmpe21 (1) cmpe20 (1) cmpe19 (1) cmpe18 cmpe17 cmpe16 0000 15:0 cmpe15 cmpe14 cmpe13 cmpe12 cmpe11 cmpe10 cmpe9 cmpe8 cmpe7 cmpe6 cmpe5 cmpe4 cmpe3 cmpe2 cmpe1 cmpe0 0000 b03c adccmp1 31:16 dcmphi<15:0> 0000 15:0 dcmplo<15:0> 0000 b040 adccmpen2 31:16 cmpe31 (1) cmpe30 (1) cmpe29 (1) cmpe28 (1) cmpe27 (1) cmpe26 (1) cmpe25 (1) cmpe24 (1) cmpe23 (1) cmpe22 (1) cmpe21 (1) cmpe20 (1) cmpe19 (1) cmpe18 cmpe17 cmpe16 0000 15:0 cmpe15 cmpe14 cmpe13 cmpe12 cmpe11 cmpe10 cmpe9 cmpe8 cmpe7 cmpe6 cmpe5 cmpe4 cmpe3 cmpe2 cmpe1 cmpe0 0000 b044 adccmp2 31:16 dcmphi<15:0> 0000 15:0 dcmplo<15:0> 0000 b048 adccmpen3 31:16 cmpe31 (1) cmpe30 (1) cmpe29 (1) cmpe28 (1) cmpe27 (1) cmpe26 (1) cmpe25 (1) cmpe24 (1) cmpe23 (1) cmpe22 (1) cmpe21 (1) cmpe20 (1) cmpe19 (1) cmpe18 cmpe17 cmpe16 0000 15:0 cmpe15 cmpe14 cmpe13 cmpe12 cmpe11 cmpe10 cmpe9 cmpe8 cmpe7 cmpe6 cmpe5 cmpe4 cmpe3 cmpe2 cmpe1 cmpe0 0000 note 1: this bit or register is not available on 64-pin devices. 2: this bit or register is not available on 64-pin and 100-pin devices. 3: before enabling the adc, the user application must initialize the adc calibration values by copying them from the factory-progr ammed devadcx flash registers into the corresponding adcxcfg registers.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 432 ? 2015-2016 microchip technology inc. b04c adccmp3 31:16 dcmphi<15:0> 0000 15:0 dcmplo<15:0> 0000 b050 adccmpen4 31:16 cmpe31 (1) cmpe30 (1) cmpe29 (1) cmpe28 (1) cmpe27 (1) cmpe26 (1) cmpe25 (1) cmpe24 (1) cmpe23 (1) cmpe22 (1) cmpe21 (1) cmpe20 (1) cmpe19 (1) cmpe18 cmpe17 cmpe16 0000 15:0 cmpe15 cmpe14 cmpe13 cmpe12 cmpe11 cmpe10 cmpe9 cmpe8 cmpe7 cmpe6 cmpe5 cmpe4 cmpe3 cmpe2 cmpe1 cmpe0 0000 b054 adccmp4 31:16 dcmphi<15:0> 0000 15:0 dcmplo<15:0> 0000 b058 adccmpen5 31:16 cmpe31 (1) cmpe30 (1) cmpe29 (1) cmpe28 (1) cmpe27 (1) cmpe26 (1) cmpe25 (1) cmpe24 (1) cmpe23 (1) cmpe22 (1) cmpe21 (1) cmpe20 (1) cmpe19 (1) cmpe18 cmpe17 cmpe16 0000 15:0 cmpe15 cmpe14 cmpe13 cmpe12 cmpe11 cmpe10 cmpe9 cmpe8 cmpe7 cmpe6 cmpe5 cmpe4 cmpe3 cmpe2 cmpe1 cmpe0 0000 b05c adccmp5 31:16 dcmphi<15:0> 0000 15:0 dcmplo<15:0> 0000 b060 adccmpen6 31:16 cmpe31 (1) cmpe30 (1) cmpe29 (1) cmpe28 (1) cmpe27 (1) cmpe26 (1) cmpe25 (1) cmpe24 (1) cmpe23 (1) cmpe22 (1) cmpe21 (1) cmpe20 (1) cmpe19 (1) cmpe18 cmpe17 cmpe16 0000 15:0 cmpe15 cmpe14 cmpe13 cmpe12 cmpe11 cmpe10 cmpe9 cmpe8 cmpe7 cmpe6 cmpe5 cmpe4 cmpe3 cmpe2 cmpe1 cmpe0 0000 b064 adccmp6 31:16 dcmphi<15:0> 0000 15:0 dcmplo<15:0> 0000 b068 adcfltr1 31:16 afen data16en dfmode ovrsam<2:0> afgien afrdy chnlid<4:0> 0000 15:0 fltrdata<15:0> 0000 b06c adcfltr2 31:16 afen data16en dfmode ovrsam<2:0> afgien afrdy chnlid<4:0> 0000 15:0 fltrdata<15:0> 0000 b070 adcfltr3 31:16 afen data16en dfmode ovrsam<2:0> afgien afrdy chnlid<4:0> 0000 15:0 fltrdata<15:0> 0000 b074 adcfltr4 31:16 afen data16en dfmode ovrsam<2:0> afgien afrdy chnlid<4:0> 0000 15:0 fltrdata<15:0> 0000 b078 adcfltr5 31:16 afen data16en dfmode ovrsam<2:0> afgien afrdy chnlid<4:0> 0000 15:0 fltrdata<15:0> 0000 b07c adcfltr6 31:16 afen data16en dfmode ovrsam<2:0> afgien afrdy chnlid<4:0> 0000 15:0 fltrdata<15:0> 0000 b080 adctrg1 31:16 trgsrc3<4:0> trgsrc2<4:0> 0000 15:0 trgsrc1<4:0> trgsrc0<4:0> 0000 b084 adctrg2 31:16 trgsrc7<4:0> trgsrc6<4:0> 0000 15:0 trgsrc5<4:0> trgsrc4<4:0> 0000 b088 adctrg3 31:16 trgsrc11<4:0> trgsrc10<4:0> 0000 15:0 trgsrc9<4:0> trgsrc8<4:0> 0000 b0a0 adccmpcon1 31:16 cvddata<15:0> 0000 15:0 ainid<5:0> endcmp dcmpgien dcmped iebtwn iehihi iehilo ielohi ielolo 0000 b0a4 adccmpcon2 31:16 0000 15:0 ainid<4:0> endcmp dcmpgien dcmped iebtwn iehihi iehilo ielohi ielolo 0000 b0a8 adccmpcon3 31:16 0000 15:0 ainid<4:0> endcmp dcmpgien dcmped iebtwn iehihi iehilo ielohi ielolo 0000 table 28-1: adc register map (continued) virtual address (bf84_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 note 1: this bit or register is not available on 64-pin devices. 2: this bit or register is not available on 64-pin and 100-pin devices. 3: before enabling the adc, the user application must initialize the adc calibration values by copying them from the factory-progr ammed devadcx flash registers into the corresponding adcxcfg registers.
? 2015-2016 microchip technology inc. ds60001320d-page 433 pic32mz embedded connectivity with floating point unit (ef) family b0ac adccmpcon4 31:16 0000 15:0 ainid<4:0> endcmp dcmpgien dcmped iebtwn iehihi iehilo ielohi ielolo 0000 b0b0 adccmpcon5 31:16 0000 15:0 ainid<4:0> endcmp dcmpgien dcmped iebtwn iehihi iehilo ielohi ielolo 0000 b0b4 adccmpcon6 31:16 0000 15:0 ainid<4:0> endcmp dcmpgien dcmped iebtwn iehihi iehilo ielohi ielolo 0000 b0b8 adcfstat 31:16 fen adc4en adc3en adc2en adc1en adc0en fien frdy fwroverr 0000 15:0 fcnt<7:0> fsign adcid<2:0> 0000 b0bc adcfifo 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b0c0 adcbase 31:16 0000 15:0 adcbase<15:0> 0000 b0d0 adctrgsns 31:16 0000 15:0 lvl11 lvl10 lvl9 lvl8 lvl7 lvl6 lvl5 lvl4 lvl3 lvl2 lvl1 lvl0 0000 b0d4 adc0time 31:16 adceis<2:0> selres<1:0> adcdiv<6:0> 0300 15:0 samc<9:0> 0000 b0d8 adc1time 31:16 adceis<2:0> selres<1:0> adcdiv<6:0> 0300 15:0 samc<9:0> 0000 b0dc adc2time 31:16 adceis<2:0> selres<1:0> adcdiv<6:0> 0300 15:0 samc<9:0> 0000 b0e0 adc3time 31:16 adceis<2:0> selres<1:0> adcdiv<6:0> 0300 15:0 samc<9:0> 0000 b0e4 adc4time 31:16 adceis<2:0> selres<1:0> adcdiv<6:0> 0300 15:0 samc<9:0> 0000 b0f0 adceien1 31:16 eien31 (1) eien30 (1) eien29 (1) eien28 (1) eien27 (1) eien26 (1) eien25 (1) eien24 (1) eien23 (1) eien22 (1) eien21 (1) eien20 (1) eien19 (1) eien18 eien17 eien16 0000 15:0 eien15 eien14 eien13 eien12 eien11 eien10 eien9 eien8 eien7 eien6 eien5 eien4 eien3 eien2 eien1 eien0 0000 b0f4 adceien2 31:16 0000 15:0 eien44 eien43 eien42 (2) eien41 (2) eien40 (2) eien39 (2) eien38 (2) eien37 (2) eien36 (2) eien35 (2) eien34 (1) eien33 (1) eien32 (1) 0000 b0f8 adceistat1 31:16 eirdy31 (1) eirdy30 (1) eirdy29 (1) eirdy28 (1) eirdy27 (1) eirdy26 (1) eirdy25 (1) eirdy24 (1) eirdy23 (1) eirdy22 (1) eirdy21 (1) eirdy20 (1) eirdy19 (1) eirdy18 eirdy17 eirdy16 0000 15:0 eirdy15 eirdy14 eirdy13 eirdy12 eirdy11 eirdy10 eirdy9 eirdy8 eirdy7 eirdy6 eirdy5 eirdy4 eirdy3 eirdy2 eirdy1 eirdy0 0000 b0fc adceistat2 31:16 0000 15:0 eirdy44 eirdy43 eirdy42 (2) eirdy41 (2) eirdy40 (2) eirdy39 (2) eirdy38 (2) eirdy37 (2) eirdy36 (2) eirdy35 (2) eirdy34 (1) eirdy33 (1) eirdy32 (1) 0000 b100 adcancon 31:16 wkupclkcnt<3:0> wkien7 wkien4 wkien3 wkien2 wkien1 wkien0 0000 15:0 wkrdy7 wkrdy4 wkrdy3 wkrdy2 wkrdy1 wkrdy0 anen7 anen4 anen3 anen2 anen1 anen0 0000 b180 adc0cfg (3) 31:16 adccfg<31:16> 0000 15:0 adccfg<15:0> 0000 b184 adc1cfg (3) 31:16 adccfg<31:16> 0000 15:0 adccfg<15:0> 0000 table 28-1: adc register map (continued) virtual address (bf84_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 note 1: this bit or register is not available on 64-pin devices. 2: this bit or register is not available on 64-pin and 100-pin devices. 3: before enabling the adc, the user application must initialize the adc calibration values by copying them from the factory-progr ammed devadcx flash registers into the corresponding adcxcfg registers.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 434 ? 2015-2016 microchip technology inc. b188 adc2cfg (3) 31:16 adccfg<31:16> 0000 15:0 adccfg<15:0> 0000 b18c adc3cfg (3) 31:16 adccfg<31:16> 0000 15:0 adccfg<15:0> 0000 b190 adc4cfg (3) 31:16 adccfg<31:16> 0000 15:0 adccfg<15:0> 0000 b19c adc7cfg (3) 31:16 adccfg<31:16> 0000 15:0 adccfg<15:0> 0000 b1c0 adcsyscfg1 31:16 an<31:16> xxxf 15:0 an<15:0> ffff b1c4 adcsyscfg2 31:16 0000 15:0 an<44:32> 1xxx b200 adcdata0 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b204 adcdata1 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b208 adcdata2 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b20c adcdata3 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b210 adcdata4 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b214 adcdata5 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b218 adcdata6 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b21c adcdata7 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b220 adcdata8 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b224 adcdata9 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b228 adcdata10 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b22c adcdata11 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b230 adcdata12 31:16 data<31:16> 0000 15:0 data<15:0> 0000 table 28-1: adc register map (continued) virtual address (bf84_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 note 1: this bit or register is not available on 64-pin devices. 2: this bit or register is not available on 64-pin and 100-pin devices. 3: before enabling the adc, the user application must initialize the adc calibration values by copying them from the factory-progr ammed devadcx flash registers into the corresponding adcxcfg registers.
? 2015-2016 microchip technology inc. ds60001320d-page 435 pic32mz embedded connectivity with floating point unit (ef) family b234 adcdata13 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b238 adcdata14 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b23c adcdata15 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b240 adcdata16 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b244 adcdata17 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b248 adcdata18 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b24c adcdata19 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b250 adcdata20 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b254 adcdata21 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b258 adcdata22 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b25c adcdata23 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b260 adcdata24 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b264 adcdata25 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b268 adcdata26 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b26c adcdata27 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b270 adcdata28 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b274 adcdata29 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b278 adcdata30 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b27c adcdata31 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 table 28-1: adc register map (continued) virtual address (bf84_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 note 1: this bit or register is not available on 64-pin devices. 2: this bit or register is not available on 64-pin and 100-pin devices. 3: before enabling the adc, the user application must initialize the adc calibration values by copying them from the factory-progr ammed devadcx flash registers into the corresponding adcxcfg registers.
? 2015-2016 microchip technology inc. ds60001320d-page 436 pic32mz embedded connectivity with floating point unit (ef) family b280 adcdata32 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b284 adcdata33 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b288 adcdata34 (1) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b28c adcdata35 (2) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b290 adcdata36 (2) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b294 adcdata37 (2) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b298 adcdata38 (2) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b29c adcdata39 (2) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b2a0 adcdata40 (2) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b2a4 adcdata41 (2) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b2a8 adcdata42 (2) 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b2ac adcdata43 31:16 data<31:16> 0000 15:0 data<15:0> 0000 b2b0 adcdata44 31:16 data<31:16> 0000 15:0 data<15:0> 0000 table 28-1: adc register map (continued) virtual address (bf84_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 note 1: this bit or register is not available on 64-pin devices. 2: this bit or register is not available on 64-pin and 100-pin devices. 3: before enabling the adc, the user application must initialize the adc calibration values by copying them from the factory-progr ammed devadcx flash registers into the corresponding adcxcfg registers.
? 2015-2016 microchip technology inc. ds60001320d-page 437 pic32mz embedded connectivity with floating point unit (ef) family register 28-1: adccon1: a dc control register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r-0, hs, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trben trberr trbmst<2:0> trbslv<2:0> 23:16 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fract selres<1:0> strgsrc<4:0> 15:8 r/w-0 u-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 u-0 on sidl aicpmpen cvden fssclken fspbclken 7:0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 irqvs<2:0> strglvl legend: hc = hardware set hs = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 trben: turbo channel enable bit 1 = enable the turbo channel 0 = disable the turbo channel bit 30 trberr: turbo channel error status bit 1 = an error occurred while setting the turbo channel and turbo channel function to be disabled regardless of the trben bit being set to 1 . 0 = turbo channel error did not occur note: the status of this bit is valid only after the trben bit is set. bit 29-27 trbmst<2:0>: turbo master adcx bits 111 = reserved 110 = adc4 is selected as the turbo master 000 = adc0 is selected as the turbo master bit 26-24 trbslv<2:0>: turbo slave adcx bits 111 = reserved 110 = adc4 is selected as the turbo slave 000 = adc0 is selected as the turbo slave bit 23 fract: fractional data output format bit 1 = fractional 0 = integer bit 22-21 selres<1:0>: shared adc (adc7) resolution bits 11 = 12 bits (default) 10 = 10 bits 01 = 8 bits 00 = 6 bits note: changing the resolution of the adc does not shift the result in the corre sponding adcdatax register. the result will still occupy 12 bits, with the corresponding lower unused bits set to 0 . for example, a resolution of 6 bits will result in adcdatax<5:0> being set to 0 , and adcdatax<11:6> holding the result.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 438 ? 2015-2016 microchip technology inc. bit 20-16 strgsrc<4:0>: scan trigger source select bits 11111 = reserved 01101 = reserved 01100 = comparator 2 (cout) 01011 = comparator 1 (cout) 01010 = ocmp5 01001 = ocmp3 01000 = ocmp1 00111 = tmr5 match 00110 = tmr3 match 00101 = tmr1 match 00100 = int0 external interrupt 00011 = reserved 00010 = global level software trigger (glswtrg) 00001 = global software edge trigger (gswtrg) 00000 = no trigger bit 15 on: adc module enable bit 1 = adc module is enabled 0 = adc module is disabled note: the on bit should be set only after the adc module has been configured. bit 14 unimplemented: read as 0 bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 aicpmpen: analog input charge pump enable bit 1 = analog input charge pump is enabled (default) 0 = analog input charge pump is disabled bit 11 cvden: capacitive voltage division enable bit 1 = cvd operation is enabled 0 = cvd operation is disabled bit 10 fssclken: fast synchronous system clock to adc control clock bit 1 = fast synchronous system clock to adc control clock is enabled 0 = fast synchronous system clock to adc control clock is disabled bit 9 fspbclken: fast synchronous peripheral clock to adc control clock bit 1 = fast synchronous peripheral clock to adc control clock is enabled 0 = fast synchronous peripheral clock to adc control clock is disabled bit 8-7 unimplemented: read as 0 bit 6-4 irqvs<2:0>: interrupt vector shift bits to determine interrupt vector address, this bit specifies the amount of left shift done to the ardyx status bits in the adcdstat1 and adcdstat2 registers, prior to adding with the adcbase registe r. interrupt vector address = read value of adc base and read value of adcbase = value written to adcbase + x << irqvs<2:0>, where x is the smallest active input id from the adcdstat1 or adcdstat2 registers (which has highest priority). 111 = shift x left 7 bit position 110 = shift x left 6 bit position 101 = shift x left 5 bit position 100 = shift x left 4 bit position 011 = shift x left 3 bit position 010 = shift x left 2 bit position 001 = shift x left 1 bit position 000 = shift x left 0 bit position register 28-1: adccon1: adc cont rol register 1 (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 439 pic32mz embedded connectivity with floating point unit (ef) family bit 3 strglvl: scan trigger high level/positive edge sensitivity bit 1 = scan trigger is high level sensitive. once strig mode is selected (trgsrcx<4:0> in the adctrgx register), the scan trigger will continue for all selected analog inputs, until the strig option is removed . 0 = scan trigger is positive edge sensitive. once strig mode is selected (trgsrcx<4:0> in the adctrgx register), only a single scan trigger will be generated, which will complete the scan of all selected analog inputs. bit 2-0 unimplemented: read as 0 register 28-1: adccon1: adc cont rol register 1 (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 440 ? 2015-2016 microchip technology inc. register 28-2: adccon2: adc control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0, hs, hc r-0, hs, hc r-0, hs, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bgvrrdy refflt eosrdy cvdcpl<2:0> samc<9:8> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 samc<7:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 bgvrien reffltien eosien adceiovr adceis<2:0> 7:0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcdiv<6:0> legend: hc = hardware set hs = hardware cleared r = reserved r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 bgvrrdy: band gap voltage/adc reference voltage status bit 1 = both band gap voltage and adc reference voltages (v ref ) are ready 0 = either or both band gap voltage and adc reference voltages (v ref ) are not ready data processing is valid only after bgvrrdy is set by hardware, so the a pplication code must check that the bgvrrdy bit is set to ensure data validity. this bit set to 0 when on (adccon1<15>) = 0 . bit 30 refflt: band gap/v ref /av dd bor fault status bit 1 = fault in band gap or the v ref voltage while the on bit (adccon1<15>) was set. most likely a band gap or v ref fault will be caused by a bor of the analog v dd supply. 0 = band gap and v ref voltage are working properly this bit is cleared when the on bit (adccon1<15>) = 0 and the bgvrrdy bit = 1 . bit 29 eosrdy: end of scan interrupt status bit 1 = all analog inputs are considered for scanning through the scan trigger (all analog inputs specified in the adccss1 and adccss2 registers) have completed scanning 0 = scanning has not completed this bit is cleared when adccon2<31:24> are read in software. bit 28-26 cvdcpl<2:0>: capacitor voltage divider (cvd) setting bit 111 = 7 * 2.5 pf = 17.5 pf 110 = 6 * 2.5 pf = 15 pf 101 = 5 * 2.5 pf = 12.5 pf 100 = 4 * 2.5 pf = 10 pf 011 = 3 * 2.5 pf = 7.5 pf 010 = 2 * 2.5 pf = 5 pf 001 = 1 * 2.5 pf = 2.5 pf 000 = 0 * 2.5 pf = 0 pf bit 25-16 samc<9:0>: sample time for the shared adc (adc7) bits 1111111111 = 1025 t ad 7 0000000001 = 3 t ad 7 0000000000 = 2 t ad 7 where t ad 7 = period of the adc conversion clock for the shared adc (adc7) controlled by the adcdiv<6:0> bits. bit 15 bgvrien: band gap/v ref voltage ready interrupt enable bit 1 = interrupt will be generated when the bgvrddy bit is set 0 = no interrupt is generated when the bgvrrdy bit is set
? 2015-2016 microchip technology inc. ds60001320d-page 441 pic32mz embedded connectivity with floating point unit (ef) family bit 14 reffltien: band gap/v ref voltage fault interrupt enable bit 1 = interrupt will be generated when the refflt bit is set 0 = no interrupt is generated when the refflt bit is set bit 13 eosien: end of scan interrupt enable bit 1 = interrupt will be generated when eosrdy bit is set 0 = no interrupt is generated when the eosrdy bit is set bit 12 adceiovr: early interrupt request override bit 1 = early interrupt generation is not overridden and interrupt generation is controlled by the adceien1 and adceien2 registers 0 = early interrupt generation is overridden and interrupt generation is controlled by the adcgirqen1 and adcgirqen2 registers bit 11 unimplemented: read as 0 bit 10-8 adceis<2:0>: shared adc (adc7) early interrupt select bits these bits select the number of clocks (t ad 7) prior to the arrival of valid data that the associated interrupt is generated. 111 = the data ready interrupt is generated 8 adc clocks prior to end of conversion 110 = the data ready interrupt is generated 7 adc clocks prior to end of conversion 001 = the data ready interrupt is generated 2 adc module clocks prior to end of conversion 000 = the data ready interrupt is generated 1 adc module clock prior to end of conversion note: all options are available when the selected resolution, set by the selres<1:0> bits (adccon1<22:21>), is 12-bit or 10-bit. for a selected resolution of 8-bit, opt ions from 000 to 101 are valid. for a selected resolution of 6-bit, options from 000 to 011 are valid. bit 7 unimplemented: read as 0 bit 6-0 adcdiv<6:0>: shared adc (adc7) clock divider bits 1111111 = 254 * t q = t ad 7 0000011 = 6 * t q = t ad 7 0000010 = 4 * t q = t ad 7 0000001 = 2 * t q = t ad 7 0000000 = reserved the adcdiv<6:0> bits divide the adc control clock (t q ) to generate the clock for the shared adc, adc7 (t ad 7 ). register 28-2: adccon2: adc contro l register 2 (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 442 ? 2015-2016 microchip technology inc. register 28-3: adccon3: adc control register 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcsel<1:0> conclkdiv<5:0> 23:16 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 digen7 digen4 digen3 digen2 digen1 digen0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0, hs, hc r/w-0 r-0, hs, hc vrefsel<2:0> trgsusp updien updrdy samp (1,2,3,4) rqcnvrt 7:0 r/w-0 r/w-0, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 glswtrg gswtrg adinsel<5:0> legend: hc = hardware set hs = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-30 adcsel<1:0>: analog-to-digital clock source (t clk ) bits 11 = frc 10 = refclk3 01 = system clock (tcy) 00 = pbclk3 bit 29-24 conclkdiv<5:0>: analog-to-digital control clock (t q ) divider bits 111111 = 64 * t clk = t q 000011 = 4 * t clk = t q 000010 = 3 * t clk = t q 000001 = 2 * t clk = t q 000000 = t clk = t q bit 23 digen7: shared adc (adc7) digital enable bit 1 = adc7 is digital enabled 0 = adc7 is digital disabled bit 22-21 unimplemented: read as 0 bit 20 digen4: adc4 digital enable bit 1 = adc4 is digital enabled 0 = adc4 is digital disabled bit 19 digen3: adc3 digital enable bit 1 = adc3 is digital enabled 0 = adc3 is digital disabled note 1: the samp bit has the highest priority and setting this bit will keep the s&h circuit in sample mode until the bit is cleared. also, usage of the samp bit will cause settings of samc<9:0> bits (adccon2<25:16>) to be ignored. 2: the samp bit only connects class 2 and class 3 analog inputs to the shared adc, adc7. all class 1 analog inputs are not affected by the samp bit. 3: the samp bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit and only after setting the rqcnvrt bit to start the analog-to-digital conversi on. 4: normally, when the samp and rqcnvrt bits are used by software routines, all trgsrcx<4:0> bits and strgsrc<4:0> bits should be set to 00000 to disable all external hardware triggers and prevent them from interfering with the software-controlled sampling command signal samp and with the software-controlled trigger rqcnvrt.
? 2015-2016 microchip technology inc. ds60001320d-page 443 pic32mz embedded connectivity with floating point unit (ef) family bit 18 digen2: adc2 digital enable bit 1 = adc2 is digital enabled 0 = adc2 is digital disabled bit 17 digen1: adc1 digital enable bit 1 = adc1 is digital enabled 0 = adc1 is digital disabled bit 16 digen0: adc0 digital enable bit 1 = adc0 is digital enabled 0 = adc0 is digital disabled bit 15-13 vrefsel<2:0>: voltage reference (v ref ) input selection bits bit 12 trgsusp: trigger suspend bit 1 = triggers are blocked from starting a new analog-to-digital conversion, but the adc module is not disabled 0 = triggers are not blocked bit 11 updien: update ready interrupt enable bit 1 = interrupt will be generated when the updrdy bit is set by hardware 0 = no interrupt is generated bit 10 updrdy: adc update ready status bit 1 = adc sfrs can be updated 0 = adc sfrs cannot be updated note: this bit is only active while the trgsusp bit is set and there are no more running conversions of any adc modules. bit 9 samp: class 2 and class 3 analog input sampling enable bit (1,2,3,4) 1 = the adc s&h amplifier is sampling 0 = the adc s&h amplifier is holding bit 8 rqcnvrt: individual adc input conversion request bit this bit and its associated adinsel<5:0> bits enable the user to individually request an analog-to-digital conversion of an analog input through software. 1 = trigger the conversion of the selected adc input as specified by the adinsel<5:0> bits 0 = do not trigger the conversion note: this bit is automatically cleared in the next adc clock cycle. bit 7 glswtrg: global level software trigger bit 1 = trigger conversion for adc inputs that have selected the glswtrg bit as the trigger signal, either through the associated trgsrc<4:0> bits in the adctrgx registers or through the strgsrc<4:0> bits in the adccon1 register 0 = do not trigger an analog-to-digital conversion register 28-3: adccon3: adc contro l register 3 (continued) note 1: the samp bit has the highest priority and setting this bit will keep the s&h circuit in sample mode until the bit is cleared. also, usage of the samp bit will cause settings of samc<9:0> bits (adccon2<25:16>) to be ignored. 2: the samp bit only connects class 2 and class 3 analog inputs to the shared adc, adc7. all class 1 analog inputs are not affected by the samp bit. 3: the samp bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit and only after setting the rqcnvrt bit to start the analog-to-digital conversi on. 4: normally, when the samp and rqcnvrt bits are used by software routines, all trgsrcx<4:0> bits and strgsrc<4:0> bits should be set to 00000 to disable all external hardware triggers and prevent them from interfering with the software-controlled sampling command signal samp and with the software-controlled trigger rqcnvrt. vrefsel<2:0> ad ref +a d ref - 1xx reserved; do not use 011 external v refh external v refl 010 av dd external v refl 001 external v refh avss 000 av dd avss
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 444 ? 2015-2016 microchip technology inc. bit 6 gswtrg: global software trigger bit 1 = trigger conversion for adc inputs that have selected the gswtrg bit as the trigger signal, either through the associated trgsrc<4:0> bits in the adctrgx registers or through the strgsrc<4:0> bits in the adccon1 register 0 = do not trigger an analog-to-digital conversion note: this bit is automatically cleared in the next adc clock cycle. bit 5-0 adinsel<5:0>: analog input select bits these bits select the analog input to be converted when the rqcnvrt bit is set. as a general rule: 111111 = reserved 101101 = reserved 101100 = max_an_input + 2 = iv temp 101011 = max_an_input + 1 = iv ref 101010 = max_an_input = an[max_an_input] 000001 = an1 000000 = an0 register 28-3: adccon3: adc contro l register 3 (continued) note 1: the samp bit has the highest priority and setting this bit will keep the s&h circuit in sample mode until the bit is cleared. also, usage of the samp bit will cause settings of samc<9:0> bits (adccon2<25:16>) to be ignored. 2: the samp bit only connects class 2 and class 3 analog inputs to the shared adc, adc7. all class 1 analog inputs are not affected by the samp bit. 3: the samp bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit and only after setting the rqcnvrt bit to start the analog-to-digital conversi on. 4: normally, when the samp and rqcnvrt bits are used by software routines, all trgsrcx<4:0> bits and strgsrc<4:0> bits should be set to 00000 to disable all external hardware triggers and prevent them from interfering with the software-controlled sampling command signal samp and with the software-controlled trigger rqcnvrt.
? 2015-2016 microchip technology inc. ds60001320d-page 445 pic32mz embedded connectivity with floating point unit (ef) family register 28-4: adctrgmode: adc triggering mode for dedicated adc register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 s h 4 a l t < 1 : 0 > 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sh3alt<1:0> sh2alt<1:0> sh1alt<1:0> sh0alt<1:0> 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 strgen4 strgen3 strgen2 strgen1 strgen0 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssampen4 ssampen3 ssampen2 ssampen1 ssampen0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-26 unimplemented: read as 0 bit 25-24 sh4alt<1:0>: adc4 analog input select bit 11 = reserved 10 = reserved 01 = an49 00 = an4 bit 23-22 sh3alt<1:0>: adc3 analog input select bit 11 = reserved 10 = reserved 01 = an48 00 = an3 bit 21-20 sh2alt<1:0>: adc2 analog input select bit 11 = reserved 10 = reserved 01 = an47 00 = an2 bit 19-18 sh1alt<1:0>: adc1 analog input select bit 11 = reserved 10 = reserved 01 = an46 00 = an1 bit 17-16 sh0alt<1:0>: adc0 analog input select bit 11 = reserved 10 = reserved 01 = an45 00 = an0 bit 15-13 unimplemented: read as 0 bit 12 strgen4: adc4 presynchronized triggers bit 1 = adc4 uses presynchronized triggers 0 = adc4 does not use presynchronized triggers bit 11 strgen3: adc3 presynchronized triggers bit 1 = adc3 uses presynchronized triggers 0 = adc3 does not use presynchronized triggers bit 10 strgen2: adc2 presynchronized triggers bit 1 = adc2 uses presynchronized triggers 0 = adc2 does not use presynchronized triggers
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 446 ? 2015-2016 microchip technology inc. bit 9 strgen1: adc1 presynchronized triggers bit 1 = adc1 uses presynchronized triggers 0 = adc1 does not use presynchronized triggers bit 8 strgen0: adc0 presynchronized triggers bit 1 = adc0 uses presynchronized triggers 0 = adc0 does not use presynchronized triggers bit 7-5 unimplemented: read as 0 bit 4 ssampen4: adc4 synchronous sampling bit 1 = adc4 uses synchronous sampling for the first sample after being idle or disabled 0 = adc4 does not use synchronous sampling bit 3 ssampen3: adc3 synchronous sampling bit 1 = adc3 uses synchronous sampling for the first sample after being idle or disabled 0 = adc3 does not use synchronous sampling bit 2 ssampen2: adc2synchronous sampling bit 1 = adc2 uses synchronous sampling for the first sample after being idle or disabled 0 = adc2 does not use synchronous sampling bit 1 ssampen1: adc1 synchronous sampling bit 1 = adc1 uses synchronous sampling for the first sample after being idle or disabled 0 = adc1 does not use synchronous sampling bit 0 ssampen0: adc0 synchronous sampling bit 1 = adc0 uses synchronous sampling for the first sample after being idle or disabled 0 = adc0 does not use synchronous sampling register 28-4: adctrgmode: adc triggering mode for dedicated adc register
? 2015-2016 microchip technology inc. ds60001320d-page 447 pic32mz embedded connectivity with floating point unit (ef) family register 28-5: adcimcon1: adc inpu t mode control register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff15 sign15 diff14 sign14 diff13 sign13 diff12 sign12 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff11 sign11 diff10 sign10 diff9 sign9 diff8 sign8 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff7 sign7 diff6 sign6 diff5 sign5 diff4 sign4 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff3 sign3 diff2 sign2 diff1 sign1 diff0 sign0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 diff15: an15 mode bit 1 = an15 is using differential mode 0 = an15 is using single-ended mode bit 30 sign:15 an15 signed data mode bit 1 = an15 is using signed data mode 0 = an15 is using unsigned data mode bit 29 diff14: an14 mode bit 1 = an14 is using differential mode 0 = an14 is using single-ended mode bit 28 sign14: an14 signed data mode bit 1 = an14 is using signed data mode 0 = an14 is using unsigned data mode bit 27 diff13: an13 mode bit 1 = an13 is using differential mode 0 = an13 is using single-ended mode bit 26 sign13: an13 signed data mode bit 1 = an13 is using signed data mode 0 = an13 is using unsigned data mode bit 25 diff12: an12 mode bit 1 = an12 is using differential mode 0 = an12 is using single-ended mode bit 24 sign12: an12 signed data mode bit 1 = an12 is using signed data mode 0 = an12 is using unsigned data mode bit 23 diff11: an11 mode bit 1 = an11 is using differential mode 0 = an11 is using single-ended mode bit 22 sign11: an11 signed data mode bit 1 = an11 is using signed data mode 0 = an11 is using unsigned data mode bit 21 diff10: an10 mode bit 1 = an10 is using differential mode 0 = an10 is using single-ended mode
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 448 ? 2015-2016 microchip technology inc. bit 20 sign10: an10 signed data mode bit 1 = an10 is using signed data mode 0 = an10 is using unsigned data mode bit 19 diff9: an9 mode bit 1 = an9 is using differential mode 0 = an9 is using single-ended mode bit 18 sign9: an9 signed data mode bit 1 = an9 is using signed data mode 0 = an9 is using unsigned data mode bit 17 diff8: an 8 mode bit 1 = an8 is using differential mode 0 = an8 is using single-ended mode bit 16 sign8: an8 signed data mode bit 1 = an8 is using signed data mode 0 = an8 is using unsigned data mode bit 15 diff7: an7 mode bit 1 = an7 is using differential mode 0 = an7 is using single-ended mode bit 14 sign7: an7 signed data mode bit 1 = an7 is using signed data mode 0 = an7 is using unsigned data mode bit 13 diff6: an6 mode bit 1 = an6 is using differential mode 0 = an6 is using single-ended mode bit 12 sign6: an6 signed data mode bit 1 = an6 is using signed data mode 0 = an6 is using unsigned data mode bit 11 diff5: an5 mode bit 1 = an5 is using differential mode 0 = an5 is using single-ended mode bit 10 sign5: an5 signed data mode bit 1 = an5 is using signed data mode 0 = an5 is using unsigned data mode bit 9 diff4: an4 mode bit 1 = an4 is using differential mode 0 = an4 is using single-ended mode bit 8 sign4: an4 signed data mode bit 1 = an4 is using signed data mode 0 = an4 is using unsigned data mode bit 7 diff3: an3 mode bit 1 = an3 is using differential mode 0 = an3 is using single-ended mode bit 6 sign3: an3 signed data mode bit 1 = an3 is using signed data mode 0 = an3 is using unsigned data mode bit 5 diff2: an2 mode bit 1 = an2 is using differential mode 0 = an2 is using single-ended mode register 28-5: adcimcon1: adc input mo de control register 1 (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 449 pic32mz embedded connectivity with floating point unit (ef) family bit 4 sign2: an2 signed data mode bit 1 = an2 is using signed data mode 0 = an2 is using unsigned data mode bit 3 diff1: an1 mode bit 1 = an1 is using differential mode 0 = an1 is using single-ended mode bit 2 sign1: an1 signed data mode bit 1 = an1 is using signed data mode 0 = an1 is using unsigned data mode bit 1 diff0: an0 mode bit 1 = an0 is using differential mode 0 = an0 is using single-ended mode bit 0 sign0: an0 signed data mode bit 1 = an0 is using signed data mode 0 = an0 is using unsigned data mode register 28-5: adcimcon1: adc input mo de control register 1 (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 450 ? 2015-2016 microchip technology inc. register 28-6: adcimcon2: adc inpu t mode control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff31 (1) sign31 (1) diff30 (1) sign30 (1) diff29 (1) sign29 (1) diff28 (1) sign28 (1) 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff27 (1) sign27 (1) diff26 (1) sign26 (1) diff25 (1) sign25 (1) diff24 (1) sign24 (1) 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff23 (1) sign23 (1) diff22 (1) sign22 (1) diff21 (1) sign21 (1) diff20 (1) sign20 (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff19 (1) sign19 (1) diff18 sign18 diff17 sign17 diff16 sign16 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 diff31: an31 mode bit (1) 1 = an31 is using differential mode 0 = an31 is using single-ended mode bit 30 sign31: an31 signed data mode bit (1) 1 = an31 is using signed data mode 0 = an31 is using unsigned data mode bit 29 diff30: an30 mode bit (1) 1 = an30 is using differential mode 0 = an30 is using single-ended mode bit 28 sign30: an30 signed data mode bit (1) 1 = an30 is using signed data mode 0 = an30 is using unsigned data mode bit 27 diff29: an29 mode bit (1) 1 = an29 is using differential mode 0 = an29 is using single-ended mode bit 26 sign29: an29 signed data mode bit (1) 1 = an29 is using signed data mode 0 = an29 is using unsigned data mode bit 25 diff28: an28 mode bit (1) 1 = an28 is using differential mode 0 = an28 is using single-ended mode bit 24 sign28: an28 signed data mode bit (1) 1 = an28 is using signed data mode 0 = an28 is using unsigned data mode bit 23 diff27: an27 mode bit (1) 1 = an27 is using differential mode 0 = an27 is using single-ended mode bit 22 sign27: an27 signed data mode bit (1) 1 = an27 is using signed data mode 0 = an27 is using unsigned data mode note 1: this bit is not available on 64-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 451 pic32mz embedded connectivity with floating point unit (ef) family bit 21 diff26: an26 mode bit (1) 1 = an26 is using differential mode 0 = an26 is using single-ended mode bit 20 sign26: an26 signed data mode bit (1) 1 = an26 is using signed data mode 0 = an26 is using unsigned data mode bit 19 diff25: an25 mode bit (1) 1 = an25 is using differential mode 0 = an25 is using single-ended mode bit 18 sign25: an25 signed data mode bit (1) 1 = an25 is using signed data mode 0 = an25 is using unsigned data mode bit 17 diff24: an24 mode bit (1) 1 = an24 is using differential mode 0 = an24 is using single-ended mode bit 16 sign24: an24 signed data mode bit (1) 1 = an24 is using signed data mode 0 = an24 is using unsigned data mode bit 15 diff23: an23 mode bit (1) 1 = an23 is using differential mode 0 = an23 is using single-ended mode bit 14 sign23: an23 signed data mode bit (1) 1 = an23 is using signed data mode 0 = an23 is using unsigned data mode bit 13 diff22: an22 mode bit (1) 1 = an22 is using differential mode 0 = an22 is using single-ended mode bit 12 sign22: an22 signed data mode bit (1) 1 = an22 is using signed data mode 0 = an22 is using unsigned data mode bit 11 diff21: an21 mode bit (1) 1 = an21 is using differential mode 0 = an21 is using single-ended mode bit 10 sign21: an21 signed data mode bit (1) 1 = an21 is using signed data mode 0 = an21 is using unsigned data mode bit 9 diff20: an20 mode bit (1) 1 = an20 is using differential mode 0 = an20 is using single-ended mode bit 8 sign20: an20 signed data mode bit (1) 1 = an20 is using signed data mode 0 = an20 is using unsigned data mode bit 7 diff19: an19 mode bit (1) 1 = an19 is using differential mode 0 = an19 is using single-ended mode register 28-6: adcimcon2: adc input mo de control register 2 (continued) note 1: this bit is not available on 64-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 452 ? 2015-2016 microchip technology inc. bit 6 sign19: an19 signed data mode bit (1) 1 = an19 is using signed data mode 0 = an19 is using unsigned data mode bit 5 diff18: an18 mode bit 1 = an18 is using differential mode 0 = an18 is using single-ended mode bit 4 sign18: an18 signed data mode bit 1 = an18 is using signed data mode 0 = an18 is using unsigned data mode bit 3 diff17: an17 mode bit 1 = an17 is using differential mode 0 = an17 is using single-ended mode bit 2 sign17: an17 signed data mode bit 1 = an17 is using signed data mode 0 = an17 is using unsigned data mode bit 1 diff16: an16 mode bit 1 = an16 is using differential mode 0 = an16 is using single-ended mode bit 0 sign16: an16 signed data mode bit 1 = an16 is using signed data mode 0 = an16 is using unsigned data mode register 28-6: adcimcon2: adc input mo de control register 2 (continued) note 1: this bit is not available on 64-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 453 pic32mz embedded connectivity with floating point unit (ef) family register 28-7: adcimcon3: adc inpu t mode control register 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 diff44 sign44 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff43 sign43 diff42 (2) sign42 (2) diff41 (2) sign41 (2) diff40 (2) sign40 (2) 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff39 (2) sign39 (2) diff38 (2) sign38 (2) diff37 (2) sign37 (2) diff36 (2) sign36 (2) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 diff35 (2) sign35 (2) diff34 (1) sign34 (1) diff33 (1) sign33 (1) diff32 (1) sign32 (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-26 unimplemented: read as 0 bit 25 diff44: an44 mode bit 1 = an44 is using differential mode 0 = an44 is using single-ended mode bit 24 sign44: an44 signed data mode bit 1 = an44 is using signed data mode 0 = an44 is using unsigned data mode bit 23 diff43: an43 mode bit 1 = an43 is using differential mode 0 = an43 is using single-ended mode bit 22 sign43: an43 signed data mode bit 1 = an43 is using signed data mode 0 = an43 is using unsigned data mode bit 21 diff42: an42 mode bit (2) 1 = an42 is using differential mode 0 = an42 is using single-ended mode bit 20 sign42: an42 signed data mode bit (2) 1 = an42 is using signed data mode 0 = an42 is using unsigned data mode bit 19 diff41: an41 mode bit (2) 1 = an41 is using differential mode 0 = an41 is using single-ended mode bit 18 sign41: an41 signed data mode bit (2) 1 = an41 is using signed data mode 0 = an41 is using unsigned data mode bit 17 diff40: an40 mode bit (2) 1 = an40 is using differential mode 0 = an40 is using single-ended mode note 1: this bit is not available on 64-pin devices. 2: this bit is not available on 64-pin and 100-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 454 ? 2015-2016 microchip technology inc. bit 16 sign40: an40 signed data mode bit (2) 1 = an40 is using signed data mode 0 = an40 is using unsigned data mode bit 15 diff39: an39 mode bit (2) 1 = an39 is using differential mode 0 = an39 is using single-ended mode bit 14 sign39: an39 signed data mode bit (2) 1 = an39 is using signed data mode 0 = an39 is using unsigned data mode bit 13 diff38: an38 mode bit (2) 1 = an38 is using differential mode 0 = an38 is using single-ended mode bit 12 sign38: an38 signed data mode bit (2) 1 = an38 is using signed data mode 0 = an38 is using unsigned data mode bit 11 diff37: an37 mode bit (2) 1 = an37 is using differential mode 0 = an37 is using single-ended mode bit 10 sign37: an37 signed data mode bit (2) 1 = an37 is using signed data mode 0 = an37 is using unsigned data mode bit 9 diff36: an36 mode bit (2) 1 = an36 is using differential mode 0 = an36 is using single-ended mode bit 8 sign36: an36 signed data mode bit (2) 1 = an36 is using signed data mode 0 = an36 is using unsigned data mode bit 7 diff35: an35 mode bit (2) 1 = an35 is using differential mode 0 = an35 is using single-ended mode bit 6 sign35: an35 signed data mode bit (2) 1 = an35 is using signed data mode 0 = an35 is using unsigned data mode bit 5 diff34: an34 mode bit (1) 1 = an34 is using differential mode 0 = an34 is using single-ended mode bit 4 sign34: an34 signed data mode bit (1) 1 = an34 is using signed data mode 0 = an34 is using unsigned data mode bit 3 diff33: an33 mode bit (1) 1 = an33 is using differential mode 0 = an33 is using single-ended mode bit 2 sign33: an33 signed data mode bit (1) 1 = an33 is using signed data mode 0 = an33 is using unsigned data mode register 28-7: adcimcon3: adc input mo de control register 3 (continued) note 1: this bit is not available on 64-pin devices. 2: this bit is not available on 64-pin and 100-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 455 pic32mz embedded connectivity with floating point unit (ef) family bit 1 diff32: an32 mode bit (1) 1 = an32 is using differential mode 0 = an32 is using single-ended mode bit 0 sign32: an32 signed data mode bit (1) 1 = an32 is using signed data mode 0 = an32 is using unsigned data mode register 28-7: adcimcon3: adc input mo de control register 3 (continued) note 1: this bit is not available on 64-pin devices. 2: this bit is not available on 64-pin and 100-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 456 ? 2015-2016 microchip technology inc. register 28-8: adcgirqen1: adc global interrupt enable register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 agien31 (1) agien30 (1) agien29 (1) agien28 (1) agien27 (1) agien26 (1) agien25 (1) agien24 (1) 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 agien23 (1) agien22 (1) agien21 (1) agien20 (1) agien19 (1) agien18 agien17 agien16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 agien15 agien14 agien13 agien12 agien11 agien10 agien9 agien8 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 agien7 agien6 agien5 agien4 agien3 agien2 agien1 agien0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 agien31:agien0: adc global interrupt enable bits 1 = interrupts are enabled for the selected analog input. the interrupt is generated after the converted data is ready (indicated by the ardy x bit (x = 31-0) of the adcdstat1 register) 0 = interrupts are disabled note 1: this bit is not available on 64-pin devices. register 28-9: adcgirqen2: adc global interrupt enable register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 agien44 agien43 agien42 (2) agien41 (2) agien40 (2) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 agien39 (2) agien38 (2) agien37 (2) agien36 (2) agien35 (2) agien34 (1) agien33 (1) agien32 (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as 0 bit 12-0 agien44:agien32 adc global interrupt enable bits 1 = interrupts are enabled for the selected analog input. the interrupt is generated after the converted data is ready (indicated by the ardy x bit (x = 44-32) of the adcdstat2 register) 0 = interrupts are disabled note 1: this bit is not available on 64-pin devices. 2: this bit is not available on 64-pin and 100-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 457 pic32mz embedded connectivity with floating point unit (ef) family register 28-10: adccss1: adc common scan select register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css31 (1) css30 (1) css29 (1) css28 (1) css27 (1) css26 (1) css25 (1) css24 (1) 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css23 (1) css22 (1) css21 (1) css20 (1) css19 (1) css18 css17 css16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css15 css14 css13 css12 css11 css10 css9 css8 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css7 css6 css5 css4 css3 css2 css1 css0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 css31:css0: analog common scan select bits (2,3) 1 = select an x for input scan 0 = skip an x for input scan note 1: this bit is not available on 64-pin devices. 2: in addition to setting the appropriate bits in this register, class 1 and class 2 analog inputs must select the strig input as the trigger source if they are to be scanned through the css x bits. refer to the bit descriptions in the adctrgx registers for selecting the strig option. 3: if a class 1 or class 2 input is included in the scan by setting the cssx bit to 1 and by setting the trgsrcx<4:0> bits to strig mode ( 0b11 ), the user application must ensure that no other triggers are generated for that input using the rqcnvrt bit in the adccon3 register or the hardware input or any digital filter. otherwise, the scan behavior is unpredictable.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 458 ? 2015-2016 microchip technology inc. register 28-11: adccss2: adc common scan select register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css44 css43 css42 (2) css41 (2) css40 (2) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css39 (2) css38 (2) css37 (2) css36 (2) css35 (2) css34 (1) css33 (1) css32 (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as 0 bit 12-0 css44:css32: analog common scan select bits analog inputs 44 to 32 are always class 3, as there are only 32 triggers available. 1 = select an x for input scan 0 = skip an x for input scan note 1: this bit is not available on 64-pin devices. 2: this bit is not available on 64-pin and 100-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 459 pic32mz embedded connectivity with floating point unit (ef) family register 28-12: adcdstat1: adc data ready status register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc ardy31 (1) ardy30 (1) ardy29 (1) ardy28 (1) ardy27 (1) ardy26 (1) ardy25 (1) ardy24 (1) 23:16 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc ardy23 (1) ardy22 (1) ardy21 (1) ardy20 (1) ardy19 (1) ardy18 ardy17 ardy16 15:8 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc ardy15 ardy14 ardy13 ardy12 ardy11 ardy10 ardy9 ardy8 7:0 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc ardy7 ardy6 ardy5 ardy4 ardy3 ardy2 ardy1 ardy0 legend: hs = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 ardy31:ardy0: conversion data ready for corresponding analog input ready bits 1 = this bit is set when converted data is ready in the data register 0 = this bit is cleared when the associated data register is read note 1: this bit is not available on 64-pin devices. register 28-13: adcdstat2: adc data ready status register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc ardy44 ardy43 ardy42 (2) ardy41 (2) ardy40 (2) 7:0 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc ardy39 (2) ardy38 (2) ardy37 (2) ardy36 (2) ardy35 (2) ardy34 (1) ardy33 (1) ardy32 (1) legend: hs = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as 0 bit 12-0 ardy44:ardy32: conversion data ready for corresponding analog input ready bits 1 = this bit is set when converted data is ready in the data register 0 = this bit is cleared when the associated data register is read note 1: this bit is not available on 64-pin devices. 2: this bit is not available on 64 -pin and 100-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 460 ? 2015-2016 microchip technology inc. register 28-14: adccmpenx: adc digital comparator x enable register ? (x = 1 through 6) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cmpe31 (1) cmpe30 (1) cmpe29 (1) cmpe28 (1) cmpe27 (1) cmpe26 (1) cmpe25 (1) cmpe24 (1) 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cmpe23 (1) cmpe22 (1) cmpe21 (1) cmpe20 (1) cmpe19 (1) cmpe18 cmpe17 cmpe16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cmpe15 cmpe14 cmpe13 cmpe12 cmpe11 cmpe10 cmpe9 cmpe8 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cmpe7 cmpe6 cmpe5 cmpe4 cmpe3 cmpe2 cmpe1 cmpe0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 cmpe31:cmpe0: adc digital comparator x enable bits (2,3) these bits enable conversion results corresponding to the analog input to be processed by the digital comparator. cmpe0 enables an0, cmpe1 enables an1, and so on. note 1: this bit is not available on 64-pin devices. 2: cmpe x = an x , where x = 0-31 (digital comparator inputs are limited to an0 through an31). 3: changing the bits in this register while the digital comparator is en abled (endcmp = 1 ) can result in unpredictable behavior.
? 2015-2016 microchip technology inc. ds60001320d-page 461 pic32mz embedded connectivity with floating point unit (ef) family register 28-15: adccmpx: adc digital comparator x limit value register ? (x = 1 through 6) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcmphi<15:8> (1,2,3) 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcmphi<7:0> (1,2,3) 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcmplo<15:8> (1,2,3) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcmplo<7:0> (1,2,3) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 dcmphi<15:0>: digital comparator x high limit value bits (1,2,3) these bits store the high limit value, which is used by digital comparator for comparisons with adc converted data. bit 15-0 dcmplo<15:0>: digital comparator x low limit value bits (1,2,3) these bits store the low limit value, which is used by digital comparator for comparisons with adc converted data. note 1: changing theses bits while the digital comparator is enabled (endcmp = 1 ) can result in unpredictable behavior. 2: the format of the limit values should match the format of the adc converted value in terms of sign and fractional settings. 3: for digital comparator 0 used in cvd mode, the dcmphi<15:0> and dcmplo<15:0> bits must a lways be specified in signed format, as the cvd output data is differential and is always signed.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 462 ? 2015-2016 microchip technology inc. register 28-16: adcfltrx: adc digital filter x register (x = 1 through 6) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0, hs, hc afen data16en dfmode ovrsam<2:0> afgien afrdy 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chnlid<4:0> 15:8 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc fltrdata<15:8> 7:0 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc fltrdata<7:0> legend: hs = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 afen: digital filter x enable bit 1 = digital filter is enabled 0 = digital filter is disabled and the afrdy status bit is cleared bit 30 data16en: filter significant data length bit 1 = all 16 bits of the filter output data are significant 0 = only the first 12 bits are significant, followed by four zeros note: this bit is significant only if dfmode = 1 (averaging mode) and fract (adccon1<23>) = 1 (fractional output mode). bit dfmode: adc filter mode bit 1 = filter x works in averaging mode 0 = filter x works in oversampling filter mode (default) bit 28-26 ovrsam<2:0>: oversampling filter ratio bits if dfmode is 0 : 111 = 128 samples (shift sum 3 bits to right, output data is in 15.1 format) 110 = 32 samples (shift sum 2 bits to right, output data is in 14.1 format) 101 = 8 samples (shift sum 1 bit to right, output data is in 13.1 format) 100 = 2 samples (shift sum 0 bits to right, output data is in 12.1 format) 011 = 256 samples (shift sum 4 bits to right, output data is 16 bits) 010 = 64 samples (shift sum 3 bits to right, output data is 15 bits) 001 = 16 samples (shift sum 2 bits to right, output data is 14 bits) 000 = 4 samples (shift sum 1 bit to right, output data is 13 bits) if dfmode is 1 : 111 = 256 samples (256 samples to be averaged) 110 = 128 samples (128 samples to be averaged) 101 = 64 samples (64 samples to be averaged) 100 = 32 samples (32 samples to be averaged) 011 = 16 samples (16 samples to be averaged) 010 = 8 samples (8 samples to be averaged) 001 = 4 samples (4 samples to be averaged) 000 = 2 samples (2 samples to be averaged) bit 25 afgien: digital filter x interrupt enable bit 1 = digital filter interrupt is enabled and is generated by the afrdy status bit 0 = digital filter is disabled
? 2015-2016 microchip technology inc. ds60001320d-page 463 pic32mz embedded connectivity with floating point unit (ef) family bit 24 afrdy: digital filter x data ready status bit 1 = data is ready in the fltrdata<15:0> bits 0 = data is not ready note: this bit is cleared by reading the fltrdata<15:0> bits or by disabling the digital filter module (by setting afen to 0 ). bit 23-21 unimplemented: read as 0 bit 20-16 chnlid<4:0>: digital filter analog input selection bits these bits specify the analog input to be used as the oversampling filter data source. 11111 = reserved 01100 = reserved 01011 = an11 00010 = an2 00001 = an1 00000 = an0 note: only the first 12 analog inputs, class 1 (an0-an11) and class 2 (an5-an11), can use a digital filter. bit 15-0 fltrdata<15:0>: digital filter x data output value bits the filter output data is as per the fractional format set in the fract bit (adccon1<23>). the fract bit should not be changed while the filter is enabled. changing the state of the fract bit after the operation of the filter ended will not update the value of the fltrdata<15:0> bits to reflect the new format. register 28-16: adcfltrx: adc digital filter x register (x = 1 through 6)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 464 ? 2015-2016 microchip technology inc. register 28-17: adctrg1: ad c trigger source 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc3<4:0> 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc2<4:0> 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc1<4:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc0<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28-24 trgsrc3<4:0>: trigger source for conversion of analog input an3 select bits 11111 = reserved 01101 = reserved 01100 = comparator 2 (cout) 01011 = comparator 1 (cout) 01010 = ocmp5 01001 = ocmp3 01000 = ocmp1 00111 = tmr5 match 00110 = tmr3 match 00101 = tmr1 match 00100 = int0 external interrupt 00011 = strig 00010 = global level software trigger (glswtrg) 00001 = global software edge trigger (gswtrg) 00000 = no trigger for strig, in addition to setting the trigger, it also requires programming of the strgsrc<4:0> bits (adccon1<20:16>) to select the trigger source, and requires the appropriate css bits to be set in the adccss x registers. bit 23-21 unimplemented: read as 0 bit 20-16 trgsrc2<4:0>: trigger source for conversion of analog input an2 select bits see bits 28-24 for bit value definitions. bit 15-13 unimplemented: read as 0 bit 12-8 trgsrc1<4:0>: trigger source for conversion of analog input an1 select bits see bits 28-24 for bit value definitions. bit 7-5 unimplemented: read as 0 bit 4-0 trgsrc0<4:0>: trigger source for conversion of analog input an0 select bits see bits 28-24 for bit value definitions.
? 2015-2016 microchip technology inc. ds60001320d-page 465 pic32mz embedded connectivity with floating point unit (ef) family register 28-18: adctrg2: ad c trigger source 2 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc7<4:0> 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc6<4:0> 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc5<4:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc4<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28-24 trgsrc7<4:0>: trigger source for conversion of analog input an7 select bits 11111 = reserved 01101 = reserved 01100 = comparator 2 (cout) 01011 = comparator 1 (cout) 01010 = ocmp5 01001 = ocmp3 01000 = ocmp1 00111 = tmr5 match 00110 = tmr3 match 00101 = tmr1 match 00100 = int0 external interrupt 00011 = strig 00010 = global level software trigger (glswtrg) 00001 = global software edge trigger (gswtrg) 00000 = no trigger for strig, in addition to setting the trigger, it also requires programming of the strgsrc<4:0> bits (adccon1<20:16>) to select the trigger source, and requires the appropriate css bits to be set in the adccss x registers. bit 23-21 unimplemented: read as 0 bit 20-16 trgsrc6<4:0>: trigger source for conversion of analog input an6 select bits see bits 28-24 for bit value definitions. bit 15-13 unimplemented: read as 0 bit 12-8 trgsrc5<4:0>: trigger source for conversion of analog input an5 select bits see bits 28-24 for bit value definitions. bit 7-5 unimplemented: read as 0 bit 4-0 trgsrc4<4:0>: trigger source for conversion of analog input an4 select bits see bits 28-24 for bit value definitions.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 466 ? 2015-2016 microchip technology inc. register 28-19: adctrg3: ad c trigger source 3 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc11<4:0> 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc10<4:0> 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc9<4:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgsrc8<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28-24 trgsrc11<4:0>: trigger source for conversion of analog input an11 select bits 11111 = reserved 01101 = reserved 01100 = comparator 2 (cout) 01011 = comparator 1 (cout) 01010 = ocmp5 01001 = ocmp3 01000 = ocmp1 00111 = tmr5 match 00110 = tmr3 match 00101 = tmr1 match 00100 = int0 external interrupt 00011 = strig 00010 = global level software trigger (glswtrg) 00001 = global software edge trigger (gswtrg) 00000 = no trigger for strig, in addition to setting the trigger, it also requires programming of the strgsrc<4:0> bits (adccon1<20:16>) to select the trigger source, and requires the appropriate css bits to be set in the adccss x registers. bit 23-21 unimplemented: read as 0 bit 20-16 trgsrc10<4:0>: trigger source for conversion of analog input an10 select bits see bits 28-24 for bit value definitions. bit 15-13 unimplemented: read as 0 bit 12-8 trgsrc9<4:0>: trigger source for conversion of analog input an9 select bits see bits 28-24 for bit value definitions. bit 7-5 unimplemented: read as 0 bit 4-0 trgsrc8<4:0>: trigger source for conversion of analog input an8 select bits see bits 28-24 for bit value definitions.
? 2015-2016 microchip technology inc. ds60001320d-page 467 pic32mz embedded connectivity with floating point unit (ef) family register 28-20: adccmpcon1: adc digital comparator 1 control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc cvddata<15:8> 23:16 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc cvddata<7:0> 15:8 u-0 u-0 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc ainid<5:0> 7:0 r/w-0 r/w-0 r-0, hs, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 endcmp dcmpgien dcmped iebtwn iehihi iehilo ielohi ielolo legend: hs = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 cvddata<15:0>: cvd data status bits in cvd mode, these bits obtain the cvd differential output data (subtraction of cvd p ositive and negative measurement), whenever a digital comparator interrupt is generated. the value in these bits is compliant with the fract bit (adccon1<23>) and is always signed. bit 15-14 unimplemented: read as 0 bit 13-8 ainid<5:0>: digital comparator 0 analog input identification (id) bits when a digital comparator event occurs (dcmped = 1 ), these bits identify the analog input being monitored by digital comparator 0. note: in normal adc mode, only analog inputs <31:0> can be processed by the digital comparator 0. the digital comparator 0 also supports the cvd mode, in which all class 2 and class 3 analog inputs may be stored in the ainid<5:0> bits. 111111 = reserved 101101 = reserved 101100 = an44 is being monitored 101011 = an43 is being monitored 000001 = an1 is being monitored 000000 = an0 is being monitored bit 7 endcmp: digital comparator 0 enable bit 1 = digital comparator 0 is enabled 0 = digital comparator 0 is not enabled, and the dcmped status bit (adccmp0con<5>) is cleare d bit 6 dcmpgien: digital comparator 0 global interrupt enable bit 1 = a digital comparator 0 interrupt is generated when the dcmped status bi t (adccmp0con<5>) is set 0 = a digital comparator 0 interrupt is disabled bit 5 dcmped: digital comparator 0 output true event status bit the logical conditions under which the digital comparator gets true are defined by the iebtwn, iehih i, iehilo, ielohi, and ielolo bits. note: this bit is cleared by reading the ainid<5:0> bits or by disabling the digital comparator module (by setting endcmp to 0 ). 1 = digital comparator 0 output true event has occurred (output of comparator is 1 ) 0 = digital comparator 0 output is false (output of comparator is 0 ) bit 4 iebtwn: between low/high digital comparator 0 event bit 1 = generate a digital comparator event when dcmplo<15:0> ? data<31:0> < dcmphi<15:0> 0 = do not generate a digital comparator event
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 468 ? 2015-2016 microchip technology inc. bit 3 iehihi: high/high digital comparator 0 event bit 1 = generate a digital comparator 0 event when dcmphi<15:0> ? data<31:0> 0 = do not generate an event bit 2 iehilo: high/low digital comparator 0 event bit 1 = generate a digital comparator 0 event when data<31:0> < dcmphi<15:0> 0 = do not generate an event bit 1 ielohi: low/high digital comparator 0 event bit 1 = generate a digital comparator 0 event when dcmplo<15:0> ? data<31:0> 0 = do not generate an event bit 0 ielolo: low/low digital comparator 0 event bit 1 = generate a digital comparator 0 event when data<31:0> < dcmplo<15:0> 0 = do not generate an event register 28-20: adccmpcon1: adc digital comparator 1 control register
? 2015-2016 microchip technology inc. ds60001320d-page 469 pic32mz embedded connectivity with floating point unit (ef) family register 28-21: adccmpconx: adc digita l comparator x control register ? (x = 2 through 6) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc ainid<4:0> 7:0 r/w-0 r/w-0 r-0, hs, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 endcmp dcmpgien dcmped iebtwn iehihi iehilo ielohi ielolo legend: hs = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as 0 bit 12-8 ainid<4:0>: digital comparator x analog input identification (id) bits when a digital comparator event occurs (dcmped = 1 ), these bits identify the analog input being monitored by the digital comparator. note: only analog inputs <31:0> can be processed by the digital comparator module x (x = 1-5). 11111 = an31 is being monitored 11110 = an30 is being monitored 00001 = an1 is being monitored 00000 = an0 is being monitored bit 7 endcmp: digital comparator x enable bit 1 = digital comparator x is enabled 0 = digital comparator x is not enabled, and the dcmped status bit (adccmp x con<5>) is cleared bit 6 dcmpgien: digital comparator x global interrupt enable bit 1 = a digital comparator x interrupt is generated when the dcmped status bit (adccm p x con<5>) is set 0 = a digital comparator x interrupt is disabled bit 5 dcmped: digital comparator x output true event status bit the logical conditions under which the digital comparator gets true are defined by the iebtwn, iehihi, iehilo, ielohi and ielolo bits. note: this bit is cleared by reading the ainid<5:0> bits (adccmp0con<13:8>) or by disabling the digital comparator module (by setting endcmp to 0 ). 1 = digital comparator x output true event has occurred (output of comparator is 1 ) 0 = digital comparator x output is false (output of comparator is 0 ) bit 4 iebtwn: between low/high digital comparator x event bit 1 = generate a digital comparator event when the dcmplo<15:0> bits ? data<31:0> bits ? < dcmphi<15:0> bits 0 = do not generate a digital comparator event bit 3 iehihi: high/high digital comparator x event bit 1 = generate a digital comparator x event when the dcmphi<15:0> bits ? data<31:0> bits 0 = do not generate an event bit 2 iehilo: high/low digital comparator x event bit 1 = generate a digital comparator x event when the data<31:0> bits < dcmphi<15:0> bits 0 = do not generate an event
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 470 ? 2015-2016 microchip technology inc. bit 1 ielohi: low/high digital comparator x event bit 1 = generate a digital comparator x event when the dcmplo<15:0> bits ? data<31:0> bits 0 = do not generate an event bit 0 ielolo: low/low digital comparator x event bit 1 = generate a digital comparator x event when the data<31:0> bits < dcmplo<15:0> bits 0 = do not generate an event register 28-21: adccmpconx: adc digita l comparator x control register ? (x = 2 through 6) (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 471 pic32mz embedded connectivity with floating point unit (ef) family register 28-22: adcfstat: adc fifo status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fen adc4en adc3en adc2en adc1en adc0en 23:16 r/w-0 r-0, hs, hc r-0, hs, hc u-0 u-0 u-0 u-0 u-0 fien frdy fwroverr 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 fcnt<7:0> 7:0 r-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 fsign a d c i d < 2 : 0 > legend: hs = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 fen: fifo enable bit 1 = fifo is enabled 0 = fifo is disabled; no data is being saved into the fifo bit 30-29 unimplemented: read as 0 bit 28-24 adc4en:adc0en: adcx enable bits (x = 0 through 4) 1 = converted output data of adcx is stored in the fifo 0 = converted output data of adcx is not stored in the fifo note: while using fifo, the output data is additionally stored in the respective output data register (adcdatax). bit 23 fien: fifo interrupt enable bit 1 = fifo interrupts are enabled; an interrupt is generated once the frdy bit is set 0 = fifo interrupts are disabled bit 22 frdy: fifo data ready interrupt status bit 1 = fifo has data to be read 0 = no data is available in the fifo note: this bit is cleared when the fifo output data in adcfifo has been read and there is no additional data ready in the fifo (that is, the fifo is empty). bit 21 fwroverr: fifo write overflow error status bit 1 = a write overflow error in the fifo has occurred (circular fifo) 0 = a write overflow error in the fifo has not occurred note: this bit is cleared after adcfstat<23:16> are read by software. bit 15-8 fcnt<7:0>: fifo data entry count status bit the value in these bits indicates the number of data entries in the fifo. bit 7 fsign: fifo sign setting bit this bit reflects the sign of data stored in the adcfifo register. bit 6-3 unimplemented: read as 0 bit 2-0 adcid<2:0>: adcx identifier bits (x = 0 through 4) these bits specify the adc module whose data is stored in the fifo. 111 = reserved 110 = reserved 101 = reserved 100 = converted data of adc4 is stored in fifo 000 = converted data of adc0 is stored in fifo
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 472 ? 2015-2016 microchip technology inc. register 28-23: adcfifo: adc fifo data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 data<31:0>: fifo data output value bits note: when an alternate input is used as the input source for a dedicated adc module, the data output is still read from the primary input data output register.
? 2015-2016 microchip technology inc. ds60001320d-page 473 pic32mz embedded connectivity with floating point unit (ef) family register 28-24: adcbase: adc base register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcbase<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcbase<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 unimplemented: read as 0 bit 15-0 adcbase<15:0>: adc isr base address bits this register, when read, contains the base address of the user's adc isr jump table. the interrupt vector address is determined by the irqvs<2:0> bits of the adccon1 register specifying th e amount of left shift done to the ardyx status bits in the adcdstat1 and adcdstat2 registers, pr ior to adding with adcbase register. interrupt vector address = read value of adc base and read value of adcbase = value written to adcbase + x << irqvs<2:0>, where x is the smallest active analog input id from the adcdstat1 or adcdstat2 registers (which has highest priority).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 474 ? 2015-2016 microchip technology inc. register 28-25: adcdatax: adc output data register (x = 0 through 44) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 data<31:0>: adc converted data output bits. note 1: the registers, adcdata19 through adcdata34, are not available on 64-pin de vices. 2: the registers, adcdata35 through adcdata42, are not available on 64-pin a nd 100-pin devices. 3: when an alternate input is used as the input source for a dedicated adc module, the data output is still read from the primary input data output register. 4: reading the adcdatax register value after changing the fract bit converts the data into the format specified by fract bit.
? 2015-2016 microchip technology inc. ds60001320d-page 475 pic32mz embedded connectivity with floating point unit (ef) family register 28-26: adctrgsns: adc trigge r level/edge sensitivity register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 lvl11 lvl10 lvl9 lvl8 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lvl7 lvl6 lvl5 lvl4 lvl3 lvl2 lvl1 lvl0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-12 unimplemented: read as 0 bit 11 lvl11:lvl0: trigger level and edge sensitivity bits 1 = analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high) 0 = analog input is sensitive to the positive edge of its trigger (this is the value after a reset) note 1: this register specifies the trigger level for analog inputs 0 to 31. 2: the higher analog input id belongs to class 3, and therefore, is only scan triggered. all class 3 analog inputs use the scan trigger, for which the level/edge is defined by th e strglvl bit (adccon1<3>).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 476 ? 2015-2016 microchip technology inc. register 28-27: adcxtime: dedicated adcx timing register x (x = 0 through 4) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 adceis<2:0> selres<1:0> 23:16 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcdiv<6:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 samc<9:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 samc<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as 0 bit 28-26 adceis<2:0>: adcx early interrupt select bits 111 = the data ready interrupt is generated 8 adc clocks prior to the end of conversion 110 = the data ready interrupt is generated 7 adc clocks prior to the end of conversion 001 = the data ready interrupt is generated 2 adc clocks prior to the end of conversion 000 = the data ready interrupt is generated 1 adc clock prior to the end of conversion note: all options are available when the selected resolution, specified by the selres<1:0> bits (adcxtime<25:24>), is 12-bit or 10-bit. for a selected resolution of 8-bit, options from 000 to 101 are valid. for a selected resolution of 6-bit, options from 000 to 011 are valid. bit 25-24 selres<1:0>: adcx resolution select bits 11 = 12 bits 10 = 10 bits 01 = 8 bits 00 = 6 bits note: changing the resolution of the adc does not shift the result in the corresponding adcda tax register. the result will still occupy 12 bits, with the corresponding lower unused bits set to 0 . for example, a resolution of 6 bits will result in adcdatax<5:0> being set to 0 , and adcdatax<11:6> holding the result. bit 23 unimplemented: read as 0 bit 22-16 adcdiv<6:0>: adcx clock divisor bits these bits divide the adc control clock with period t q to generate the clock for adcx (t ad x ). 1111111 = 254 * t q = t ad x 0000011 = 6 * t q = t ad x 0000010 = 4 * t q = t ad x 0000001 = 2 * t q = t ad x 0000000 = reserved bit 15-10 unimplemented: read as 0 bit 9-0 samc<9:0>: adcx sample time bits where t ad x = period of the adc conversion clock for the dedicated adc controlled by the adcdiv<6:0> bits. 1111111111 = 1025 t ad x 0000000001 = 3 t ad x 0000000000 = 2 t ad x
? 2015-2016 microchip technology inc. ds60001320d-page 477 pic32mz embedded connectivity with floating point unit (ef) family register 28-28: adceien1: adc early interrupt enable register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eien31 (1) eien30 (1) eien29 (1) eien28 (1) eien27 (1) eien26 (1) eien25 (1) eien24 (1) 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eien23 (1) eien22 (1) eien21 (1) eien20 (1) eien19 (1) eien18 eien17 eien16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eien15 eien14 eien13 eien12 eien11 eien10 eien9 eien8 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eien7 eien6 eien5 eien4 eien3 eien2 eien1 eien0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 eien31:eien0: early interrupt enable for analog input bits 1 = early interrupts are enabled for the selected analog input. the interrupt is generated after the early interrupt event occurs (indicated by the eirdyx bit ('x' = 31-0) of the adceistat1 register) 0 = interrupts are disabled note 1: this bit is not available on 64-pin devices. register 28-29: adceien2: adc early interrupt enable register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eien44 (2) eien43 (2) eien42 (2) eien41 (2) eien40 (2) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eien39 (2) eien38 (2) eien37 (2) eien36 (2) eien35 (2) eien34 (1) eien33 (1) eien32 (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as 0 bit 12-0 eien44:eien32: early interrupt enable for analog input bits 1 = early interrupts are enabled for the selected analog input. the interrupt is generated after the early interrupt event occurs (indicated by the eirdyx bit ('x' = 44-32) of the adceistat2 register) 0 = interrupts are disabled note 1: this bit is not available on 64-pin devices. 2: this bit is not available on 64-pin and 100-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 478 ? 2015-2016 microchip technology inc. register 28-30: adceistat1: adc early interrupt status register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc eirdy31 (1) eirdy30 (1) eirdy29 (1) eirdy28 (1) eirdy27 (1) eirdy26 (1) eirdy25 (1) eirdy24 (1) 23:16 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc eirdy23 (1) eirdy22 (1) eirdy21 (1) eirdy20 (1) eirdy19 (1) eirdy18 eirdy17 eirdy16 15:8 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc eirdy15 eirdy14 eirdy13 eirdy12 eirdy11 eirdy10 eirdy9 eirdy8 7:0 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc eirdy7 eirdy6 eirdy5 eirdy4 eirdy3 eirdy2 eirdy1 eirdy0 legend: hs = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 eirdy31:eirdy0: early interrupt for corresponding analog input ready bits 1 = this bit is set when the early interrupt event occurs for the specified analog input. an interrupt will be generated if early interrupts are enabled in the adceien1 register. for the class 1 analog inputs, this bit will set as per the configuration of the adceis<2:0> bits in the adcxtime register. for the shared adc module, this bit will be set as per the configuration of the adceis<2:0> bits in the adccon2 register. 0 = interrupts are disabled note 1: this bit is not available on 64-pin devices.
? 2015-2016 microchip technology inc. ds60001320d-page 479 pic32mz embedded connectivity with floating point unit (ef) family register 28-31: adceistat2: adc early interrupt status register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc eirdy44 (2) eirdy43 (2) eirdy42 (2) eirdy41 (2) eirdy40 (2) 7:0 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc eirdy39 (2) eirdy38 (2) eirdy37 (2) eirdy36 (2) eirdy35 (2) eirdy34 (1) eirdy33 (1) eirdy32 (1) legend: hs = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as 0 bit 31-0 eirdy44:eirdy32: early interrupt for corresponding analog input ready bits 1 = this bit is set when the early interrupt event occurs for the specified analog input. an interrupt will be generated if early interrupts are enabled in the adceien2 register. for the class 1 analog inputs, this bit will set as per the configuration of the adceis<2:0> bits in the adcxtime register. for the shared adc module, this bit will be set as per the configuration of the adceis<2:0> bits in the adccon2 register. 0 = interrupts are disabled note 1: this bit is not available on 64-pin devices. 2: this bit is not available on 64-pin and 100-pin devices.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 480 ? 2015-2016 microchip technology inc. register 28-32: adcancon: adc analog warm-up control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 wkupclkcnt<3:0> 23:16 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wkien7 wkien4 wkien3 wkien2 wkien1 wkien0 15:8 r-0, hs, hc u-0 u-0 r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc r-0, hs, hc wkrdy7 wkrdy4 wkrdy3 wkrdy2 wkrdy1 wkrdy0 7:0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 anen7 anen4 anen3 anen2 anen1 anen0 legend: hs = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-28 unimplemented: read as 0 bit 27-24 wkupclkcnt<3:0>: wake-up clock count bits these bits represent the number of adc clocks required to warm-up the adc module before it can perform conversion. although the clocks are specific to each adc, the wkupclkcnt bit is common to all adc modules. 1111 = 2 15 = 32,768 clocks 0110 = 2 6 = 64 clocks 0101 = 2 5 = 32 clocks 0100 = 2 4 = 16 clocks 0011 = 2 4 = 16 clocks 0010 = 2 4 = 16 clocks 0001 = 2 4 = 16 clocks 0000 = 2 4 = 16 clocks bit 23 wkien7: shared adc (adc7) wake-up interrupt enable bit 1 = enable interrupt and generate interrupt when the wkrdy7 status bit is set 0 = disable interrupt bit 22-21 unimplemented: read as 0 bit 20-16 wkien4:wkien0: adc4-adc0 wake-up interrupt enable bit 1 = enable interrupt and generate interrupt when the wkrdyx status bit is set 0 = disable interrupt bit 15 wkrdy7: shared adc (adc7) wake-up status bit 1 = adc7 analog and bias circuitry ready after the wake-up count number 2 wkupexp clocks after setting anen7 to 1 0 = adc7 analog and bias circuitry is not ready note: this bit is cleared by hardware when the anen7 bit is cleared bit 14-13 unimplemented: read as 0 bit 12-8 wkrdy4:wkrdy0: adc4-adc0 wake-up status bit 1 = adcx analog and bias circuitry ready after the wake-up count number 2 wkupexp clocks after setting anen x to 1 0 = adcx analog and bias circuitry is not ready note: these bits are cleared by hardware when the anen x bit is cleared
? 2015-2016 microchip technology inc. ds60001320d-page 481 pic32mz embedded connectivity with floating point unit (ef) family bit 7 anen7: shared adc (adc7) analog and bias circuitry enable bit 1 = analog and bias circuitry enabled. once the analog and bias circuit is enabled, the adc module needs a warm-up time, as defined by the wkupclkcnt<3:0> bits. 0 = analog and bias circuitry disabled bit 5-6 unimplemented: read as 0 bit 4-0 anen4:anen0: adc4-adc0 analog and bias circuitry enable bits 1 = analog and bias circuitry enabled. once the analog and bias circuit is enabled, the adc module needs a warm-up time, as defined by the wkupclkcnt<3:0> bits. 0 = analog and bias circuitry disabled register 28-32: adcancon: adc analog warm-up control register (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 482 ? 2015-2016 microchip technology inc. register 28-33: adcxcfg: adcx configuration register x (x = 0 through 4 and 7) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adccfg<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adccfg<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adccfg<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adccfg<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 adccfg<31:0>: adc module configuration data bits prior to enabling the adc, these registers should be written with the corresponding value stored in devadcx in software during adc initialization. note: the bits in this register can only change when the applicable anen x bit in the adcancon register is cleared.
? 2015-2016 microchip technology inc. ds60001320d-page 483 pic32mz embedded connectivity with floating point unit (ef) family register 28-34: adcsyscfg1: adc sys tem configuration register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-y r-y r-y r-y r-y r-y r-y r-y an<31:23> 23:16 r-y r-y r-y r-y r-y r-1 r-1 r-1 an<23:16> 15:8 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 an<15:8> 7:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 an<7:0> legend: y = por value is determined by the specific device r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 an<31:0>: adc analog input bits these bits reflect the system configuration and are updated during boot-up time. by reading these read- only bits, the user application can determine whether or not an analog input in the device is available. an<31:0>: reflects the presence or absence of the respective analog input (an31-an0). register 28-35: adcsyscfg2: adc system configuration register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r-1 r-1 r-y r-y r-y an<44:40> 7:0 r-y r-y r-y r-y r-y r-y r-y r-y an<39:32> legend: y = por value is determined by the specific device r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as 0 bit 12-0 an<44:32>: adc analog input bits these bits reflect the system configuration and are updated during boot-up time. by reading these read- only bits, the user application can determine whether or not an analog input in the device is available. an<63:32>: reflects the presence or absence of the respective analog input (an63-an32).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 484 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 485 pic32mz embedded connectivity with floating point unit (ef) family 29.0 controller area network (can) the controller area network (can) module supports the following key features: standards compliance: - full can 2.0b compliance - programmable bit rate up to 1 mbps message reception and transmission: - 32 message fifos - each fifo can have up to 32 messages for a total of 1024 messages - fifo can be a transmit message fifo or a receive message fifo - user-defined priority levels for message fifos used for transmission - 32 acceptance filters for message filtering - four acceptance filter mask registers for message filtering - automatic response to remote transmit request - devicenet? addressing support additional features: - loopback, listen all messages and listen only modes for self-test, system diagnostics and bus monitoring - low-power operating modes - can module is a bus master on the pic32 system bus - use of dma is not required - dedicated time-stamp timer - dedicated dma channels - data-only message reception mode figure 29-1 illustrates the general structure of the can module. figure 29-1: pic32 c an module block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 34. controller area network (can) (ds60001154) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). message buffer 31 message buffer 1 message buffer 0 message buffer 31 message buffer 1 message buffer 0 message buffer 31 message buffer 1 message buffer 0 fifo0 fifo1 fifo31 system ram up to 32 message buffers can message fifo (up to 32 fifos) message buffer size 2 or 4 words system bus cpu can module 32 filters 4 masks cxtx cxrx pbclk5 (x = 1-2)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 486 ? 2015-2016 microchip technology inc. 29.1 can control registers note: the i shown in register names denotes can1 or can2. table 29-1: can1 register summary for pic32mzxxxxecf and pic32mzxxxxech devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0000 c1con 31:16 abat reqop<2:0> opmod<2:0> cancap 0480 15:0 on sidle canbusy dncnt<4:0> 0000 0010 c1cfg 31:16 wakfil seg2ph<2:0> 0000 15:0 seg2phts sam seg1ph<2:0> prseg<2:0> sjw<1:0> brp<5:0> 0000 0020 c1int 31:16 ivrie wakie cerrie serrie rbovie modie ctmrie rbie tbie 0000 15:0 ivrif wakif cerrif serrif rbovif modif ctmrif rbif tbif 0000 0030 c1vec 31:16 0000 15:0 filhit<4:0> icode<6:0> 0040 0040 c1trec 31:16 txbo txbp rxbp txwarn rxwarn ewarn 0000 15:0 terrcnt<7:0> rerrcnt<7:0> 0000 0050 c1fstat 31:16 fifoip31 fifoip30 fifoip29 fifoip28 fifoip27 fifoip26 fifoip25 fifoip24 fifoip23 fifoip22 fifoip21 fifoip20 fifoip19 fifoip18 fifoip17 fifoip16 0000 15:0 fifoip15 fifoip14 fifoip13 fifoip12 fifoip11 fifoip10 fifoip9 fifoip8 fifoip7 fifoip6 fifoip5 fifoip4 fifoip3 fifoip2 fifoip1 fifoip0 0000 0060 c1rxovf 31:16 rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf25 rxovf24 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 0000 15:0 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxovf9 rxovf8 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 0000 0070 c1tmr 31:16 cants<15:0> 0000 15:0 cantspre<15:0> 0000 0080 c1rxm0 31:16 sid<10:0> - mide eid<17:16> xxxx 15:0 eid<15:0> xxxx 0090 c1rxm1 31:16 sid<10:0> - mide eid<17:16> xxxx 15:0 eid<15:0> xxxx 00a0 c1rxm2 31:16 sid<10:0> - mide eid<17:16> xxxx 15:0 eid<15:0> xxxx 00b0 c1rxm3 31:16 sid<10:0> - mide eid<17:16> xxxx 15:0 eid<15:0> xxxx 00c0 c1fltcon0 31:16 flten3 msel3<1:0> fsel3<4:0> flten2 msel2<1:0> fsel2<4:0> 0000 15:0 flten1 msel1<1:0> fsel1<4:0> flten0 msel0<1:0> fsel0<4:0> 0000 00d0 c1fltcon1 31:16 flten7 msel7<1:0> fsel7<4:0> flten6 msel6<1:0> fsel6<4:0> 0000 15:0 flten5 msel5<1:0> fsel5<4:0> flten4 msel4<1:0> fsel4<4:0> 0000 00e0 c1fltcon2 31:16 flten11 msel11<1:0> fsel11<4:0> flten10 msel10<1:0> fsel10<4:0> 0000 15:0 flten9 msel9<1:0> fsel9<4:0> flten8 msel8<1:0> fsel8<4:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 487 pic32mz embedded connectivity with floating point unit (ef) family 00f0 c1fltcon3 31:16 flten15 msel15<1:0> fsel15<4:0> flten14 msel14<1:0> fsel14<4:0> 0000 15:0 flten13 msel13<1:0> fsel13<4:0> flten12 msel12<1:0> fsel12<4:0> 0000 0100 c1fltcon4 31:16 flten19 msel19<1:0> fsel19<4:0> flten18 msel18<1:0> fsel18<4:0> 0000 15:0 flten17 msel17<1:0> fsel17<4:0> flten16 msel16<1:0> fsel16<4:0> 0000 0110 c1fltcon5 31:16 flten23 msel23<1:0> fsel23<4:0> flten22 msel22<1:0> fsel22<4:0> 0000 15:0 flten21 msel21<1:0> fsel21<4:0> flten20 msel20<1:0> fsel20<4:0> 0000 0120 c1fltcon6 31:16 flten27 msel27<1:0> fsel27<4:0> flten26 msel26<1:0> fsel26<4:0> 0000 15:0 flten25 msel25<1:0> fsel25<4:0> flten24 msel24<1:0> fsel24<4:0> 0000 0130 c1fltcon7 31:16 flten31 msel31<1:0> fsel31<4:0> flten30 msel30<1:0> fsel30<4:0> 0000 15:0 flten29 msel29<1:0> fsel29<4:0> flten28 msel28<1:0> fsel28<4:0> 0000 0140- 0330 c1rxfn (n = 0-31) 31:16 sid<10:0> - exid eid<17:16> xxxx 15:0 eid<15:0> xxxx 0340 c1fifoba 31:16 c1fifoba<31:0> 0000 15:0 0000 0350 c1fifoconn (n = 0) 31:16 fsize<4:0> 0000 15:0 freset uinc donly txen txabat txlarb txerr txreq rtren txpri<1:0> 0000 0360 c1fifointn (n = 0) 31:16 txnfullie txhalfie txemptyie rxovflie rxfullie rxhalfie rxn emptyie 0000 15:0 txnfullif txhalfif txemptyif rxovflif rxfullif rxhalfif rxn emptyif 0000 0370 c1fifouan (n = 0) 31:16 c1fifoua<31:0> 0000 15:0 0000 0380 c1fifocin (n = 0) 31:16 0000 15:0 c1fifoci<4:0> 0000 0390- 0b40 c1fifoconn c1fifointn c1fifouan c1fifocin (n = 1-31) 31:16 fsize<4:0> 0000 15:0 freset uinc donly txen txabat txlarb txerr txreq rtren txpri<1:0> 0000 31:16 txnfullie txhalfie txemptyie rxovflie rxfullie rxhalfie rxn emptyie 0000 15:0 txnfullif txhalfif txemptyif rxovflif rxfullif rxhalfif rxn emptyif 0000 31:16 c1fifoua<31:0> 0000 15:0 0000 31:16 0000 15:0 c1fifoci<4:0> 0000 table 29-1: can1 register summary for pic32mzxxxxecf and pic32mzxxxxech devices (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 488 ? 2015-2016 microchip technology inc. table 29-2: can2 register summary for pic32mzxxxxecf and pic32mzxxxxech devices virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 c2con 31:16 abat reqop<2:0> opmod<2:0> cancap 0480 15:0 on sidle canbusy dncnt<4:0> 0000 1010 c2cfg 31:16 w a k f i l seg2ph<2:0> 0000 15:0 seg2phts sam seg1ph<2:0> prseg<2:0> sjw<1:0> brp<5:0> 0000 1020 c2int 31:16 ivrie wakie cerrie serrie rbovie modie ctmrie rbie tbie 0000 15:0 ivrif wakif cerrif serrif rbovif modif ctmrif rbif tbif 0000 1030 c2vec 31:16 0000 15:0 filhit<4:0> icode<6:0> 0040 1040 c2trec 31:16 txbo txbp rxbp txwarn rxwarn ewarn 0000 15:0 terrcnt<7:0> rerrcnt<7:0> 0000 1050 c2fstat 31:16 fifoip31 fifoip30 fifoip29 fifoip28 fifoip27 fifoip26 fifoip25 fifoip24 fifoip23 fifoip22 fifoip21 fifoip20 fifoip19 fifoip18 fifoip17 fi foip16 0000 15:0 fifoip15 fifoip14 fifoip13 fifoip12 fifoip11 fifoip10 fifoip9 fifoip8 fifoip7 fifoip6 fifoip5 fifoip4 fifoip3 fifoip2 fifoip1 fifoip0 0000 1060 c2rxovf 31:16 rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf25 rxovf24 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 0000 15:0 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxovf9 rxovf8 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 0000 1070 c2tmr 31:16 cants<15:0> 0000 15:0 cantspre<15:0> 0000 1080 c2rxm0 31:16 sid<10:0> - mide eid<17:16> xxxx 15:0 eid<15:0> xxxx 10a0 c2rxm1 31:16 sid<10:0> - mide eid<17:16> xxxx 15:0 eid<15:0> xxxx 10b0 c2rxm2 31:16 sid<10:0> - mide eid<17:16> xxxx 15:0 eid<15:0> xxxx 10b0 c2rxm3 31:16 sid<10:0> - mide eid<17:16> xxxx 15:0 eid<15:0> xxxx 1010 c2fltcon0 31:16 flten3 msel3<1:0> fsel3<4:0> flten2 msel2<1:0> fsel2<4:0> 0000 15:0 flten1 msel1<1:0> fsel1<4:0> flten0 msel0<1:0> fsel0<4:0> 0000 10d0 c2fltcon1 31:16 flten7 msel7<1:0> fsel7<4:0> flten6 msel6<1:0> fsel6<4:0> 0000 15:0 flten5 msel5<1:0> fsel5<4:0> flten4 msel4<1:0> fsel4<4:0> 0000 10e0 c2fltcon2 31:16 flten11 msel11<1:0> fsel11<4:0> flten10 msel10<1:0> fsel10<4:0> 0000 15:0 flten9 msel9<1:0> fsel9<4:0> flten8 msel8<1:0> fsel8<4:0> 0000 10f0 c2fltcon3 31:16 flten15 msel15<1:0> fsel15<4:0> flten14 msel14<1:0> fsel14<4:0> 0000 15:0 flten13 msel13<1:0> fsel13<4:0> flten12 msel12<1:0> fsel12<4:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 489 pic32mz embedded connectivity with floating point unit (ef) family 1100 c2fltcon4 31:16 flten19 msel19<1:0> fsel19<4:0> flten18 msel18<1:0> fsel18<4:0> 0000 15:0 flten17 msel17<1:0> fsel17<4:0> flten16 msel16<1:0> fsel16<4:0: 0000 1110 c2fltcon5 31:16 flten23 msel23<1:0> fsel23<4:0> flten22 msel22<1:0> fsel22<4:0> 0000 15:0 flten21 msel21<1:0> fsel21<4:0> flten20 msel20<1:0> fsel20<4:0> 0000 1120 c2fltcon6 31:16 flten27 msel27<1:0> fsel27<4:0> flten26 msel26<1:0> fsel26<4:0> 0000 15:0 flten25 msel25<1:0> fsel25<4:0> flten24 msel24<1:0> fsel24<4:0> 0000 1130 c2fltcon7 31:16 flten31 msel31<1:0> fsel31<4:0> flten30 msel30<1:0> fsel30<4:0> 0000 15:0 flten29 msel29<1:0> fsel29<4:0> flten28 msel28<1:0> fsel28<4:0> 0000 1140- 1330 c2rxfn (n = 0-31) 31:16 sid<10:0> - exid eid<17:16> xxxx 15:0 eid<15:0> xxxx 1340 c2fifoba 31:16 c2fifoba<31:0> 0000 15:0 0000 1350 c2fifoconn (n = 0) 31:16 fsize<4:0> 0000 15:0 freset uinc donly txen txabat txlarb txerr txreq rtren txpri<1:0> 0000 1360 c2fifointn (n = 0) 31:16 txnfullie txhalfie txemptyie rxovflie rxfullie rxhalfie rxn emptyie 0000 15:0 txnfullif txhalfif txemptyif rxovflif rxfullif rxhalfif rxn emptyif 0000 1370 c2fifouan (n = 0) 31:16 c2fifoua<31:0> 0000 15:0 0000 1380 c2fifocin (n = 0) 31:16 0000 15:0 c2fifoci<4:0> 0000 1390- 1b40 c2fifoconn c2fifointn c2fifouan c2fifocin (n = 1-31) 31:16 fsize<4:0> 0000 15:0 freset uinc donly txen txabat txlarb txerr txreq rtren txpri<1:0> 0000 31:16 txnfullie txhalfie txemptyie rxovflie rxfullie rxhalfie rxn emptyie 0000 15:0 txnfullif txhalfif txemptyif rxovflif rxfullif rxhalfif rxn emptyif 0000 31:16 c2fifoua<31:0> 0000 15:0 0000 31:16 0000 15:0 c2fifoci<4:0> 0000 table 29-2: can2 register summary for pic32mzxxxxecf and pic32mzxxxxech devices (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 490 ? 2015-2016 microchip technology inc. register 29-1: cicon: can module control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 s/hc-0 r/w-1 r/w-0 r/w-0 abat reqop<2:0> 23:16 r-1 r-0 r-0 r/w-0 u-0 u-0 u-0 u-0 opmod<2:0> cancap 15:8 r/w-0 u-0 r/w-0 u-0 r-0 u-0 u-0 u-0 on (1) s i d l e canbusy 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dncnt<4:0> legend: hc = hardware clear s = settable bit r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (0, 1, x = unknown) bit 31-28 unimplemented: read as 0 bit 27 abat: abort all pending transmissions bit 1 = signal all transmit buffers to abort transmission 0 = module will clear this bit when all transmissions aborted bit 26-24 reqop<2:0>: request operation mode bits 111 = set listen all messages mode 110 = reserved - do not use 101 = reserved - do not use 100 = set configuration mode 011 = set listen only mode 010 = set loopback mode 001 = set disable mode 000 = set normal operation mode bit 23-21 opmod<2:0>: operation mode status bits 111 = module is in listen all messages mode 110 = reserved 101 = reserved 100 = module is in configuration mode 011 = module is in listen only mode 010 = module is in loopback mode 001 = module is in disable mode 000 = module is in normal operation mode bit 20 cancap: can message receive time stamp timer capture enable bit 1 = cantmr value is stored on valid message reception and is stored with the message 0 = disable can message receive time stamp timer capture and stop cantmr to co nserve power bit 19-16 unimplemented: read as 0 bit 15 on: can on bit (1) 1 = can module is enabled 0 = can module is disabled bit 14 unimplemented: read as 0 note 1: if the user application clears this bit, it may take a number of cycles before the can module completes the current transaction and responds to this request. the user application should poll the canbusy bit to verify that the request has been honored.
? 2015-2016 microchip technology inc. ds60001320d-page 491 pic32mz embedded connectivity with floating point unit (ef) family bit 13 sidle: can stop in idle bit 1 = can stops operation when system enters idle mode 0 = can continues operation when system enters idle mode bit 12 unimplemented: read as 0 bit 11 canbusy: can module is busy bit 1 = the can module is active 0 = the can module is completely disabled bit 10-5 unimplemented: read as 0 bit 4-0 dncnt<4:0>: device net filter bit number bits 10011-11111 = invalid selection (compare up to 18-bits of data with eid) 10010 = compare up to data byte 2 bit 6 with eid17 (cirxfn<17>) 00001 = compare up to data byte 0 bit 7 with eid0 (cirxfn<0>) 00000 = do not compare data bytes register 29-1: cicon: can module control register (continued) note 1: if the user application clears this bit, it may take a number of cycles before the can module completes the current transaction and responds to this request. the user application should poll the canbusy bit to verify that the request has been honored.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 492 ? 2015-2016 microchip technology inc. register 29-2: cicfg: can baud rate configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 wakfil seg2ph<2:0> (1,4) 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 seg2phts (1) sam (2) seg1ph<2:0> prseg<2:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sjw<1:0> (3) brp<5:0> legend: hc = hardware clear s = settable bit r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (0, 1, x = unknown) bit 31-23 unimplemented: read as 0 bit 22 wakfil: can bus line filter enable bit 1 = use can bus line filter for wake-up 0 = can bus line filter is not used for wake-up bit 21-19 unimplemented: read as 0 bit 18-16 seg2ph<2:0>: phase buffer segment 2 bits (1,4) 111 = length is 8 x t q 000 = length is 1 x t q bit 15 seg2phts: phase segment 2 time select bit (1) 1 = freely programmable 0 = maximum of seg1ph or information processing time, whichever is greater bit 14 sam: sample of the can bus line bit (2) 1 = bus line is sampled three times at the sample point 0 = bus line is sampled once at the sample point bit 13-11 seg1ph<2:0>: phase buffer segment 1 bits (4) 111 = length is 8 x t q 000 = length is 1 x t q note 1: seg2ph ?? seg1ph. if seg2phts is clear, seg2ph will be set automatically. 2: 3 time bit sampling is not allowed for brp < 2. 3: sjw ? seg2ph. 4: the time quanta per bit must be greater than 7 (that is, t qbit > 7). note: this register can only be modified when the can module is in configuration mode (opmod<2:0> (cicon<23:21>) = 100) .
? 2015-2016 microchip technology inc. ds60001320d-page 493 pic32mz embedded connectivity with floating point unit (ef) family bit 10-8 prseg<2:0>: propagation time segment bits (4) 111 = length is 8 x t q 000 = length is 1 x t q bit 7-6 sjw<1:0>: synchronization jump width bits (3) 11 = length is 4 x t q 10 = length is 3 x t q 01 = length is 2 x t q 00 = length is 1 x t q bit 5-0 brp<5:0>: baud rate prescaler bits 111111 = t q = (2 x 64)/t pbclk 5 111110 = t q = (2 x 63)/t pbclk 5 000001 = t q = (2 x 2)/t pbclk 5 000000 = t q = (2 x 1)/t pbclk 5 register 29-2: cicfg: can baud rate co nfiguration register (continued) note 1: seg2ph ?? seg1ph. if seg2phts is clear, seg2ph will be set automatically. 2: 3 time bit sampling is not allowed for brp < 2. 3: sjw ? seg2ph. 4: the time quanta per bit must be greater than 7 (that is, t qbit > 7). note: this register can only be modified when the can module is in configuration mode (opmod<2:0> (cicon<23:21>) = 100) .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 494 ? 2015-2016 microchip technology inc. register 29-3: ciint: can interrupt register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 ivrie wakie cerrie serrie rbovie 23:16 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 modie ctmrie rbie tbie 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 ivrif wakif cerrif serrif (1) rbovif 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 modif ctmrif rbif tbif legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 ivrie: invalid message received interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 30 wakie: can bus activity wake-up interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 29 cerrie: can bus error interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 28 serrie: system error interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 27 rbovie: receive buffer overflow interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 26-20 unimplemented: read as 0 bit 19 modie: mode change interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 18 ctmrie: can timestamp timer interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 17 rbie: receive buffer interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 16 tbie: transmit buffer interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 15 ivrif: invalid message received interrupt flag bit 1 = an invalid messages interrupt has occurred 0 = an invalid message interrupt has not occurred note 1: this bit can only be cleared by turning the can module off and on by clearing or setting the on bit (cicon<15>).
? 2015-2016 microchip technology inc. ds60001320d-page 495 pic32mz embedded connectivity with floating point unit (ef) family bit 14 wakif: can bus activity wake-up interrupt flag bit 1 = a bus wake-up activity interrupt has occurred 0 = a bus wake-up activity interrupt has not occurred bit 13 cerrif: can bus error interrupt flag bit 1 = a can bus error has occurred 0 = a can bus error has not occurred bit 12 serrif: system error interrupt flag bit 1 = a system error occurred (typically an illegal address was presented to the system bus) 0 = a system error has not occurred bit 11 rbovif: receive buffer overflow interrupt flag bit 1 = a receive buffer overflow has occurred 0 = a receive buffer overflow has not occurred bit 10-4 unimplemented: read as 0 bit 3 modif: can mode change interrupt flag bit 1 = a can module mode change has occurred (opmod<2:0> has changed to reflect reqop) 0 = a can module mode change has not occurred bit 2 ctmrif: can timer overflow interrupt flag bit 1 = a can timer (cantmr) overflow has occurred 0 = a can timer (cantmr) overflow has not occurred bit 1 rbif: receive buffer interrupt flag bit 1 = a receive buffer interrupt is pending 0 = a receive buffer interrupt is not pending bit 0 tbif: transmit buffer interrupt flag bit 1 = a transmit buffer interrupt is pending 0 = a transmit buffer interrupt is not pending register 29-3: ciint: can interrupt register (continued) note 1: this bit can only be cleared by turning the can module off and on by clearing or setting the on bit (cicon<15>).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 496 ? 2015-2016 microchip technology inc. register 29-4: civec: can interrupt code register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 f i l h i t < 4 : 0 > 7:0 u-0 r-1 r-0 r-0 r-0 r-0 r-0 r-0 i c o d e < 6 : 0 > (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as 0 bit 12-8 filhit<4:0>: filter hit number bit 11111 = filter 31 11110 = filter 30 00001 = filter 1 00000 = filter 0 bit 7 unimplemented: read as 0 bit 6-0 icode<6:0>: interrupt flag code bits (1) 1001000-1111111 = reserved 1001000 = invalid message received (ivrif) 1000111 = can module mode change (modif) 1000110 = can timestamp timer (ctmrif) 1000101 = bus bandwidth error (serrif) 1000100 = address error interrupt (serrif) 1000011 = receive fifo overflow interrupt (rbovif) 1000010 = wake-up interrupt (wakif) 1000001 = error interrupt (cerrif) 1000000 = no interrupt 0100000-0111111 = reserved 0011111 = fifo31 interrupt (cifstat<31> set) 0011110 = fifo30 interrupt (cifstat<30> set) 0000001 = fifo1 interrupt (cifstat<1> set) 0000000 = fifo0 interrupt (cifstat<0> set) note 1: these bits are only updated for enabled interrupts.
? 2015-2016 microchip technology inc. ds60001320d-page 497 pic32mz embedded connectivity with floating point unit (ef) family register 29-5: citrec: can transmit/receive error count register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 txbo txbp rxbp txwarn rxwarn ewarn 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 terrcnt<7:0> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rerrcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-22 unimplemented: read as 0 bit 21 txbo: transmitter in error state bus off (terrcnt ? 256) bit 20 txbp: transmitter in error state bus passive (terrcnt ? 128) bit 19 rxbp: receiver in error state bus passive (rerrcnt ? 128) bit 18 txwarn: transmitter in error state warning (128 > terrcnt ? 96) bit 17 rxwarn: receiver in error state warning (128 > rerrcnt ? 96) bit 16 ewarn: transmitter or receiver is in error state warning bit 15-8 terrcnt<7:0>: transmit error counter bit 7-0 rerrcnt<7:0>: receive error counter register 29-6: cifstat: can fifo status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 fifoip31 fifoip30 fifoip29 fifoip28 fifoip27 fifoip26 fifoip25 fifoip24 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 fifoip23 fifoip22 fifoip21 fifoip20 fifoip19 fifoip18 fifoip17 fifoip16 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 fifoip15 fifoip14 fifoip13 fifoip12 fifoip11 fifoip10 fifoip9 fifoip8 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 fifoip7 fifoip6 fifoip5 fifoip4 fifoip3 fifoip2 fifoip1 fifoip0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 fifoip<31:0>: fifox interrupt pending bits 1 = one or more enabled fifo interrupts are pending 0 = no fifo interrupts are pending
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 498 ? 2015-2016 microchip technology inc. register 29-7: cirxovf: can receive fifo overflow status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf25 rxovf24 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxovf9 rxovf8 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 rxovf<31:0>: fifox receive overflow interrupt pending bit 1 = fifo has overflowed 0 = fifo has not overflowed register 29-8: citmr: can timer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cants<15:8> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cants<7:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cantspre<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cantspre<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 cants<15:0>: can time stamp timer bits this is a free-running timer that increments every cantspre system clocks when the cancap bit (cicon<20>) is set. bit 15-0 cantspre<15:0>: can time stamp timer prescaler bits 1111 1111 1111 1111 = can time stamp timer (cants) increments every 65,535 system clocks 0000 0000 0000 0000 = can time stamp timer (cants) increments every system clock note 1: citmr will be frozen when cancap = 0 . 2: the citmr prescaler count will be reset on any write to citmr (cantspre will be unaffected).
? 2015-2016 microchip technology inc. ds60001320d-page 499 pic32mz embedded connectivity with floating point unit (ef) family register 29-9: cirxmn: can acceptance filter mask n register (n = 0-3) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sid<10:3> 23:16 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 r/w-0 r/w-0 sid<2:0> m i d e eid<17:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eid<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eid<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-21 sid<10:0>: standard identifier bits 1 = include bit, sidx, in filter comparison 0 = bit sidx is dont care in filter operation bit 20 unimplemented: read as 0 bit 19 mide: identifier receive mode bit 1 = match only message types (standard/extended address) that correspond to the exid bit in filter 0 = match either standard or extended address message if filters match (that is, if (filter sid) = (message sid) or if (filter sid/eid) = (message sid/eid)) bit 18 unimplemented: read as 0 bit 17-0 eid<17:0>: extended identifier bits 1 = include bit, eidx, in filter comparison 0 = bit eidx is dont care in filter operation note: this register can only be modified when the can module is in configur ation mode (opmod<2:0> (cicon<23:21>) = 100 ).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 500 ? 2015-2016 microchip technology inc. register 29-10: cifltcon0: can filter control register 0 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten3 msel3<1:0> fsel3<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten2 msel2<1:0> fsel2<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten1 msel1<1:0> fsel1<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten0 msel0<1:0> fsel0<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 flten3: filter 3 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel3<1:0>: filter 3 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel3<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten2: filter 2 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel2<1:0>: filter 2 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel2<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 501 pic32mz embedded connectivity with floating point unit (ef) family bit 15 flten1: filter 1 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel1<1:0>: filter 1 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel1<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten0: filter 0 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel0<1:0>: filter 0 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel0<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 29-10: cifltcon0: can filter control register 0 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 502 ? 2015-2016 microchip technology inc. register 29-11: cifltcon1: can filter control register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten7 msel7<1:0> fsel7<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten6 msel6<1:0> fsel6<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten5 msel5<1:0> fsel5<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten4 msel4<1:0> fsel4<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 flten7: filter 7 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel7<1:0>: filter 7 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel7<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten6: filter 6 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel6<1:0>: filter 6 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel6<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 503 pic32mz embedded connectivity with floating point unit (ef) family bit 15 flten5: filter 17 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel5<1:0>: filter 5 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel5<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten4: filter 4 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel4<1:0>: filter 4 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel4<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 29-11: cifltcon1: can filter control register 1 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 504 ? 2015-2016 microchip technology inc. register 29-12: cifltcon2: can filter control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten11 msel11<1:0> fsel11<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten10 msel10<1:0> fsel10<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten9 msel9<1:0> fsel9<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten8 msel8<1:0> fsel8<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 flten11: filter 11 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel11<1:0>: filter 11 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel11<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten10: filter 10 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel10<1:0>: filter 10 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel10<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 505 pic32mz embedded connectivity with floating point unit (ef) family bit 15 flten9: filter 9 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel9<1:0>: filter 9 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel9<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten8: filter 8 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel8<1:0>: filter 8 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel8<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 29-12: cifltcon2: can filter control register 2 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 506 ? 2015-2016 microchip technology inc. register 29-13: cifltcon3: can filter control register 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten15 msel15<1:0> fsel15<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten14 msel14<1:0> fsel14<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten13 msel13<1:0> fsel13<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten12 msel12<1:0> fsel12<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 flten15: filter 15 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel15<1:0>: filter 15 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel15<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten14: filter 14 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel14<1:0>: filter 14 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel14<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 507 pic32mz embedded connectivity with floating point unit (ef) family bit 15 flten13: filter 13 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel13<1:0>: filter 13 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel13<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten12: filter 12 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel12<1:0>: filter 12 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel12<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 29-13: cifltcon3: can filter control register 3 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 508 ? 2015-2016 microchip technology inc. ,4 register 29-14: cifltcon4: can filter control register 4 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten19 msel19<1:0> fsel19<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten18 msel18<1:0> fsel18<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten17 msel17<1:0> fsel17<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten16 msel16<1:0> fsel16<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 flten19: filter 19 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel19<1:0>: filter 19 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel19<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten18: filter 18 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel18<1:0>: filter 18 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel18<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 509 pic32mz embedded connectivity with floating point unit (ef) family bit 15 flten17: filter 13 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel17<1:0>: filter 17 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel17<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten16: filter 16 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel16<1:0>: filter 16 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel16<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 29-14: cifltcon4: can filter control register 4 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 510 ? 2015-2016 microchip technology inc. register 29-15: cifltcon5: can filter control register 5 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten23 msel23<1:0> fsel23<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten22 msel22<1:0> fsel22<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten21 msel21<1:0> fsel21<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten20 msel20<1:0> fsel20<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 flten23: filter 23 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel23<1:0>: filter 23 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel23<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten22: filter 22 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel22<1:0>: filter 22 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel22<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 511 pic32mz embedded connectivity with floating point unit (ef) family bit 15 flten21: filter 21 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel21<1:0>: filter 21 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel21<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten20: filter 20 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel20<1:0>: filter 20 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel20<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 29-15: cifltcon5: can filter control register 5 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 512 ? 2015-2016 microchip technology inc. register 29-16: cifltcon6: can filter control register 6 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten27 msel27<1:0> fsel27<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten26 msel26<1:0> fsel26<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten25 msel25<1:0> fsel25<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten24 msel24<1:0> fsel24<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 flten27: filter 27 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel27<1:0>: filter 27 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel27<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten26: filter 26 enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel26<1:0>: filter 26 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel26<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 513 pic32mz embedded connectivity with floating point unit (ef) family bit 15 flten25: filter 25 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel25<1:0>: filter 25 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel25<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten24: filter 24 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel24<1:0>: filter 24 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel24<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 29-16: cifltcon6: can filter control register 6 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 514 ? 2015-2016 microchip technology inc. register 29-17: cifltcon7: can filter control register 7 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten31 msel31<1:0> fsel31<4:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten30 msel30<1:0> fsel30<4:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten29 msel29<1:0> fsel29<4:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 flten28 msel28<1:0> fsel28<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 flten31: filter 31 enable bit 1 = filter is enabled 0 = filter is disabled bit 30-29 msel31<1:0>: filter 31 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 28-24 fsel31<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 23 flten30: filter 30enable bit 1 = filter is enabled 0 = filter is disabled bit 22-21 msel30<1:0>: filter 30mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 20-16 fsel30<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 515 pic32mz embedded connectivity with floating point unit (ef) family bit 15 flten29: filter 29 enable bit 1 = filter is enabled 0 = filter is disabled bit 14-13 msel29<1:0>: filter 29 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 12-8 fsel29<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 bit 7 flten28: filter 28 enable bit 1 = filter is enabled 0 = filter is disabled bit 6-5 msel28<1:0>: filter 28 mask select bits 11 = acceptance mask 3 selected 10 = acceptance mask 2 selected 01 = acceptance mask 1 selected 00 = acceptance mask 0 selected bit 4-0 fsel28<4:0>: fifo selection bits 11111 = message matching filter is stored in fifo buffer 31 11110 = message matching filter is stored in fifo buffer 30 00001 = message matching filter is stored in fifo buffer 1 00000 = message matching filter is stored in fifo buffer 0 register 29-17: cifltcon7: can filter control register 7 (continued) note: the bits in this register can only be modified if the corresponding filter enable (fltenn) bit is 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 516 ? 2015-2016 microchip technology inc. register 29-18: cirxfn: can acceptance filter n register 7 (n = 0-31) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid<10:3> 23:16 r/w-x r/w-x r/w-x u-0 r/w-0 u-0 r/w-x r/w-x sid<2:0> exid e i d < 1 7 : 1 6 > 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-21 sid<10:0>: standard identifier bits 1 = message address bit sidx must be 1 to match filter 0 = message address bit sidx must be 0 to match filter bit 20 unimplemented: read as 0 bit 19 exid: extended identifier enable bits 1 = match only messages with extended identifier addresses 0 = match only messages with standard identifier addresses bit 18 unimplemented: read as 0 bit 17-0 eid<17:0>: extended identifier bits 1 = message address bit eidx must be 1 to match filter 0 = message address bit eidx must be 0 to match filter note: this register can only be modified when the filter is disabled (fltenn = 0 ).
? 2015-2016 microchip technology inc. ds60001320d-page 517 pic32mz embedded connectivity with floating point unit (ef) family register 29-19: cififo ba: can message buffer base address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cififoba<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cififoba<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cififoba<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 (1) r-0 (1) cififoba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 cififoba<31:0>: can fifo base address bits these bits define the base address of all message buffers. individual message buffers are located based on the size of the previous message buffers. this address is a physical address. note that bits <1:0> are read-only and read 0 , forcing the messages to be 32-bit word-aligned in device ram. note 1: this bit is unimplemented and will always read 0 , which forces word-alignment of messages. note: this register can only be modified when the can module is in configuratio n mode (opmod<2:0> (cicon<23:21>) = 100 ).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 518 ? 2015-2016 microchip technology inc. register 29-20: cififoconn: can fifo control register n (n = 0-31) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f s i z e < 4 : 0 > (1) 15:8 u-0 s/hc-0 s/hc-0 r/w-0 u-0 u-0 u-0 u-0 freset uinc donly (1) 7:0 r/w-0 r-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 txen txabat (2) txlarb (3) txerr (3) txreq rtren txpr<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-21 unimplemented: read as 0 bit 20-16 fsize<4:0>: fifo size bits (1) 11111 = fifo is 32 messages deep 00010 = fifo is 3 messages deep 00001 = fifo is 2 messages deep 00000 = fifo is 1 message deep bit 15 unimplemented: read as 0 bit 14 freset: fifo reset bits 1 = fifo will be reset when bit is set, cleared by hardware when fifo is reset. after setting, the user application should poll whether this bit is clear before taking any action 0 = no effect bit 13 uinc: increment head/tail bit txen = 1 : (fifo configured as a transmit fifo) when this bit is set, the fifo head will increment by a single message txen = 0 : (fifo configured as a receive fifo) when this bit is set, the fifo tail will increment by a single message bit 12 donly: store message data only bit (1) txen = 1 : (fifo configured as a transmit fifo) this bit is not used and has no effect. txen = 0 : (fifo configured as a receive fifo) 1 = only data bytes will be stored in the fifo 0 = full message is stored, including identifier bit 11-8 unimplemented: read as 0 bit 7 txen: tx/rx buffer selection bit 1 = fifo is a transmit fifo 0 = fifo is a receive fifo note 1: these bits can only be modified when the can module is in configuration mode (opmod<2:0> bits (cicon<23:21>) = 100 ). 2: this bit is updated when a message completes (or aborts) or when the fifo is reset. 3: this bit is reset on any read of this register or when the fifo is reset.
? 2015-2016 microchip technology inc. ds60001320d-page 519 pic32mz embedded connectivity with floating point unit (ef) family bit 6 txabat: message aborted bit (2) 1 = message was aborted 0 = message completed successfully bit 5 txlarb: message lost arbitration bit (3) 1 = message lost arbitration while being sent 0 = message did not lose arbitration while being sent bit 4 txerr: error detected during transmission bit (3) 1 = a bus error occurred while the message was being sent 0 = a bus error did not occur while the message was being sent bit 3 txreq: message send request txen = 1 : (fifo configured as a transmit fifo) setting this bit to 1 requests sending a message. the bit will automatically clear when all the messages queued in the fifo are successfully sent. clearing the bit to 0 while set ( 1 ) will request a message abort. txen = 0 : (fifo configured as a receive fifo) this bit has no effect. bit 2 rtren: auto rtr enable bit 1 = when a remote transmit is received, txreq will be set 0 = when a remote transmit is received, txreq will be unaffected bit 1-0 txpr<1:0>: message transmit priority bits 11 = highest message priority 10 = high intermediate message priority 01 = low intermediate message priority 00 = lowest message priority register 29-20: cififoconn: can fifo control register n (n = 0-31) (continued) note 1: these bits can only be modified when the can module is in configuration mode (opmod<2:0> bits (cicon<23:21>) = 100 ). 2: this bit is updated when a message completes (or aborts) or when the fifo is reset. 3: this bit is reset on any read of this register or when the fifo is reset.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 520 ? 2015-2016 microchip technology inc. register 29-21: cififointn: can fifo interrupt register n (n = 0-31) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 txnfullie txhalfie txemptyie 23:16 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 rxovflie rxfullie rxhalfie rxnemptyie 15:8 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 t x n f u l l i f (1) txhalfif txemptyif (1) 7:0 u-0 u-0 u-0 u-0 r/w-0 r-0 r-0 r-0 rxovflif rxfullif (1) rxhalfif (1) rxnemptyif (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-27 unimplemented: read as 0 bit 26 txnfullie: transmit fifo not full interrupt enable bit 1 = interrupt enabled for fifo not full 0 = interrupt disabled for fifo not full bit 25 txhalfie: transmit fifo half full interrupt enable bit 1 = interrupt enabled for fifo half full 0 = interrupt disabled for fifo half full bit 24 txemptyie: transmit fifo empty interrupt enable bit 1 = interrupt enabled for fifo empty 0 = interrupt disabled for fifo empty bit 23-20 unimplemented: read as 0 bit 19 rxovflie: overflow interrupt enable bit 1 = interrupt enabled for overflow event 0 = interrupt disabled for overflow event bit 18 rxfullie: full interrupt enable bit 1 = interrupt enabled for fifo full 0 = interrupt disabled for fifo full bit 17 rxhalfie: fifo half full interrupt enable bit 1 = interrupt enabled for fifo half full 0 = interrupt disabled for fifo half full bit 16 rxnemptyie: empty interrupt enable bit 1 = interrupt enabled for fifo not empty 0 = interrupt disabled for fifo not empty bit 15-11 unimplemented: read as 0 bit 10 txnfullif: transmit fifo not full interrupt flag bit (1) txen = 1 : (fifo configured as a transmit buffer) 1 = fifo is not full 0 = fifo is full txen = 0 : (fifo configured as a receive buffer) unused, reads 0 note 1: this bit is read-only and reflects the status of the fifo.
? 2015-2016 microchip technology inc. ds60001320d-page 521 pic32mz embedded connectivity with floating point unit (ef) family bit 9 txhalfif: fifo transmit fifo half empty interrupt flag bit (1) txen = 1 : (fifo configured as a transmit buffer) 1 = fifo is ? half full 0 = fifo is > half full txen = 0 : (fifo configured as a receive buffer) unused, reads 0 bit 8 txemptyif: transmit fifo empty interrupt flag bit (1) txen = 1 : (fifo configured as a transmit buffer) 1 = fifo is empty 0 = fifo is not empty, at least 1 message queued to be transmitted txen = 0 : (fifo configured as a receive buffer) unused, reads 0 bit 7-4 unimplemented: read as 0 bit 3 rxovflif: receive fifo overflow interrupt flag bit txen = 1 : (fifo configured as a transmit buffer) unused, reads 0 txen = 0 : (fifo configured as a receive buffer) 1 = overflow event has occurred 0 = no overflow event occurred bit 2 rxfullif: receive fifo full interrupt flag bit (1) txen = 1 : (fifo configured as a transmit buffer) unused, reads 0 txen = 0 : (fifo configured as a receive buffer) 1 = fifo is full 0 = fifo is not full bit 1 rxhalfif: receive fifo half full interrupt flag bit (1) txen = 1 : (fifo configured as a transmit buffer) unused, reads 0 txen = 0 : (fifo configured as a receive buffer) 1 = fifo is ?? half full 0 = fifo is < half full bit 0 rxnemptyif: receive buffer not empty interrupt flag bit (1) txen = 1 : (fifo configured as a transmit buffer) unused, reads 0 txen = 0 : (fifo configured as a receive buffer) 1 = fifo is not empty, has at least 1 message 0 = fifo is empty register 29-21: cififointn: can fifo interrupt register n (n = 0-31) (continued) note 1: this bit is read-only and reflects the status of the fifo.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 522 ? 2015-2016 microchip technology inc. register 29-22: cififouan: can fifo user address register n (n = 0-31) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-x r-x r-x r-x r-x r-x r-x r-x cififouan<31:24> 23:16 r-x r-x r-x r-x r-x r-x r-x r-x cififouan<23:16> 15:8 r-x r-x r-x r-x r-x r-x r-x r-x cififouan<15:8> 7:0 r-x r-x r-x r-x r-x r-x r-0 (1) r-0 (1) cififouan<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 cififouan<31:0>: can fifo user address bits txen = 1 : (fifo configured as a transmit buffer) a read of this register will return the address where the next message is to be written (fifo head). txen = 0 : (fifo configured as a receive buffer) a read of this register will return the address where the next message is to be read (fifo tail). note 1: this bit will always read 0 , which forces byte-alignment of messages. note: this register is not guaranteed to read correctly in configuration mode, and should only be accessed when the module is not in configuration mode. register 29-23: cififocin: can module message index register n (n = 0-31) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 cififocin<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-5 unimplemented: read as 0 bit 4-0 cififocin<4:0>: can side fifo message index bits txen = 1 : (fifo configured as a transmit buffer) a read of this register will return an index to the message that the fifo will next attempt to transmit. txen = 0 : (fifo configured as a receive buffer) a read of this register will return an index to the message that the fifo will use to save the next message.
? 2015-2016 microchip technology inc. ds60001320d-page 523 pic32mz embedded connectivity with floating point unit (ef) family 30.0 ethernet controller the ethernet controller is a bus master module that interfaces with an off-chip physical layer (phy) to implement a complete ethernet node in a system. key features of the ethernet controller include: supports 10/100 mbps data transfer rates supports full-duplex and half-duplex operation supports rmii and mii phy interface supports miim phy management interface supports both manual and automatic flow control ram descriptor-based dma operation for both receive and transmit path fully configurable interrupts configurable receive packet filtering - crc check - 64-byte pattern match - broadcast, multicast and unicast packets - magic packet? - 64-bit hash table - runt packet supports packet payload checksum calculation supports various hardware statistics counters figure 30-1 illustrates a block diagram of the ethernet controller. figure 30-1: ethernet co ntroller block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 35. ethernet controller (ds60001155) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). tx bus master system bus rx bus master tx dma tx flow control host if rx dma rx filter checksum mac external phy mii/rmii if miim if mac control and configuration registers tx function rx function dma control registers fast peripheral bus ethernet controller rx flow control ethernet dma rx bm tx bm tx fifo rx fifo pbclk5
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 524 ? 2015-2016 microchip technology inc. table 30-1 , table 30-2 , tab l e 30-3 and tab l e 30-4 show four interfaces and the associated pins that can be used with the ethernet controller. table 30-1: mii mode default interface signals ? (fmiien = 1 , fethio = 1 ) pin name description emdc management clock emdio management i/o etxclk transmit clock etxen transmit enable etxd0 transmit data etxd1 transmit data etxd2 transmit data etxd3 transmit data etxerr transmit error erxclk receive clock erxdv receive data valid erxd0 receive data erxd1 receive data erxd2 receive data erxd3 receive data erxerr receive error ecrs carrier sense ecol collision indication table 30-2: rmii mode default interface signals ? (fmiien = 0 , fethio = 1 ) pin name description emdc management clock emdio management i/o etxen transmit enable etxd0 transmit data etxd1 transmit data erefclk reference clock ecrsdv carrier sense C receive data valid erxd0 receive data erxd1 receive data erxerr receive error note: ethernet controller pins that are not used by selected interface can be used by other peripherals. table 30-3: mii mode alternate interface signals ? (fmiien = 1 , fethio = 0 ) pin name description aemdc management clock aemdio management i/o aetxclk transmit clock aetxen transmit enable aetxd0 transmit data aetxd1 transmit data aetxd2 transmit data aetxd3 transmit data aetxerr transmit error aerxclk receive clock aerxdv receive data valid aerxd0 receive data aerxd1 receive data aerxd2 receive data aerxd3 receive data aerxerr receive error aecrs carrier sense aecol collision indication note: the mii mode alternate interface is not available on 64-pin devices. table 30-4: rmii mode alternate interface signals ? (fmiien = 0 , fethio = 0 ) pin name description aemdc management clock aemdio management i/o aetxen transmit enable aetxd0 transmit data aetxd1 transmit data aerefclk reference clock aecrsdv carrier sense C receive data valid aerxd0 receive data aerxd1 receive data aerxerr receive error
? 2015-2016 microchip technology inc. ds60001320d-page 525 pic32mz embedded connectivity with floating point unit (ef) family 30.1 ethernet control registers table 30-5: ethernet controller register summary virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 ethcon1 31:16 ptv<15:0> 0000 15:0 on sidl txrts rxen autofc manfc bufcdec 0000 2010 ethcon2 31:16 0000 15:0 rxbufsz<6:0> 0000 2020 ethtxst 31:16 txstaddr<31:16> 0000 15:0 txstaddr<15:2> 0000 2030 ethrxst 31:16 rxstaddr<31:16> 0000 15:0 rxstaddr<15:2> 0000 2040 ethht0 31:16 ht<31:0> 0000 15:0 0000 2050 ethht1 31:16 ht<63:32> 0000 15:0 0000 2060 ethpmm0 31:16 pmm<31:0> 0000 15:0 0000 2070 ethpmm1 31:16 pmm<63:32> 0000 15:0 0000 2080 ethpmcs 31:16 0000 15:0 pmcs<15:0> 0000 2090 ethpmo 31:16 0000 15:0 pmo<15:0> 0000 20a0 ethrxfc 31:16 0000 15:0 hten mpen notpm pmmode<3:0> crc erren crc oken runt erren runten ucen not meen mcen bcen 0000 20b0 ethrxwm 31:16 rxfwm<7:0> 0000 15:0 rxewm<7:0> 0000 20c0 ethien 31:16 0000 15:0 tx buseie rx buseie ew markie fw markie rx doneie pk tpendie rx actie tx doneie tx abortie rx bufnaie rx ovflwie 0000 20d0 ethirq 31:16 0000 15:0 txbuse rxbuse ewmark fwmark rxdone pktpend rxact txdone txabort rxbufna rxovflw 0000 20e0 ethstat 31:16 bufcnt<7:0> 0000 15:0 busy txbusy rxbusy 0000 2100 eth rxovflow 31:16 0000 15:0 rxovflwcnt<15:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table (with the exception of ethstat) have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: reset values default to the factory programmed value.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 526 ? 2015-2016 microchip technology inc. 2110 eth frmtxok 31:16 0000 15:0 frmtxokcnt<15:0> 0000 2120 eth scolfrm 31:16 0000 15:0 scolfrmcnt<15:0> 0000 2130 eth mcolfrm 31:16 0000 15:0 mcolfrmcnt<15:0> 0000 2140 eth frmrxok 31:16 0000 15:0 frmrxokcnt<15:0> 0000 2150 eth fcserr 31:16 0000 15:0 fcserrcnt<15:0> 0000 2160 eth algnerr 31:16 0000 15:0 algnerrcnt<15:0> 0000 2200 emac1 cfg1 31:16 0000 15:0 soft reset sim reset reset rmcs reset rfun reset tmcs reset tfun loopback txpause rxpause passall rxenable 800d 2210 emac1 cfg2 31:16 0000 15:0 excess dfr bp nobkoff nobkoff longpre purepre autopad vlanpad pad enable crc enable delaycrc hugefrm lengthck fulldplx 4082 2220 emac1 ipgt 31:16 0000 15:0 b2bipktgp<6:0> 0012 2230 emac1 ipgr 31:16 0000 15:0 nb2bipktgp1<6:0> nb2bipktgp2<6:0> 0c12 2240 emac1 clrt 31:16 0000 15:0 cwindow<5:0> retx<3:0> 370f 2250 emac1 maxf 31:16 0000 15:0 macmaxf<15:0> 05ee 2260 emac1 supp 31:16 0000 15:0 reset rmii speed rmii 1000 2270 emac1 test 31:16 0000 15:0 testbp testpause shrtqnta 0000 2280 emac1 mcfg 31:16 0000 15:0 reset mgmt clksel<3:0> nopre scaninc 0020 2290 emac1 mcmd 31:16 0000 15:0 scan read 0000 22a0 emac1 madr 31:16 0000 15:0 phyaddr<4:0> regaddr<4:0> 0100 table 30-5: ethernet controller register summary (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table (with the exception of ethstat) have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: reset values default to the factory programmed value.
? 2015-2016 microchip technology inc. ds60001320d-page 527 pic32mz embedded connectivity with floating point unit (ef) family 22b0 emac1 mwtd 31:16 0000 15:0 mwtd<15:0> 0000 22c0 emac1 mrdd 31:16 0000 15:0 mrdd<15:0> 0000 22d0 emac1 mind 31:16 0000 15:0 linkfail notvalid scan miimbusy 0000 2300 emac1 sa0 (2) 31:16 xxxx 15:0 stnaddr6<7:0> stnaddr5<7:0> xxxx 2310 emac1 sa1 (2) 31:16 xxxx 15:0 stnaddr4<7:0> stnaddr3<7:0> xxxx 2320 emac1 sa2 (2) 31:16 xxxx 15:0 stnaddr2<7:0> stnaddr1<7:0> xxxx table 30-5: ethernet controller register summary (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table (with the exception of ethstat) have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information. 2: reset values default to the factory programmed value.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 528 ? 2015-2016 microchip technology inc. register 30-1: ethcon1: ethernet controller control register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ptv<15:8> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ptv<7:0> 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 on s i d l txrts rxen (1) 7:0 r/w-0 u-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 autofc m a n f c bufcdec legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 ptv<15:0>: pause timer value bits pause timer value used for flow control. this register should only be written when rxen (ethcon1<8>) is not set. these bits are only used for flow control operations. bit 15 on: ethernet on bit 1 = ethernet module is enabled 0 = ethernet module is disabled bit 14 unimplemented: read as 0 bit 13 sidl: ethernet stop in idle mode bit 1 = ethernet module transfers are paused during idle mode 0 = ethernet module transfers continue during idle mode bit 12-10 unimplemented: read as 0 bit 9 txrts: transmit request to send bit 1 = activate the tx logic and send the packet(s) defined in the tx edt 0 = stop transmit (when cleared by software) or transmit done (when cleared by hardware) after the bit is written with a 1 , it will clear to a 0 whenever the transmit logic has finished transmitting the requested packets in the ethernet descriptor table (edt). if a 0 is written by the cpu, the transmit logic finishes the current packets transmission and then stops any further. this bit only affects tx operations. bit 8 rxen: receive enable bit (1) 1 = enable rx logic, packets are received and stored in the rx buffer as controlled by the filter ? configuration 0 = disable rx logic, no packets are received in the rx buffer this bit only affects rx operations. note 1: it is not recommended to clear the rxen bit and then make changes to any rx related field/register. the ethernet controller must be reinitialized (on cleared to 0 ), and then the rx changes applied.
? 2015-2016 microchip technology inc. ds60001320d-page 529 pic32mz embedded connectivity with floating point unit (ef) family bit 7 autofc: automatic flow control bit 1 = automatic flow control enabled 0 = automatic flow control disabled setting this bit will enable automatic flow control. if set, the full and empty watermarks are used to automatically enable and disable the flow control, respectively. when the number of received buffers bufcnt (ethstat<16:23>) rises to the full watermark, flow c ontrol is automatically enabled. when the bufcnt falls to the empty watermark, flow control is automatically disabled. this bit is only used for flow control operations and affects both tx and rx operations. bit 6-5 unimplemented: read as 0 bit 4 manfc: manual flow control bit 1 = manual flow control is enabled 0 = manual flow control is disabled setting this bit will enable manual flow control. if set, the flow control logic will send a pause frame using the pause timer value in the ptv register. it will then r esend a pause frame every 128 * ptv<15:0>/2 tx clock cycles until the bit is cleared. note: for 10 mbps operation, tx clock runs at 2.5 mhz. for 100 mbps operation, tx clock runs at 25 mhz. when this bit is cleared, the flow control logic will automatically send a pause frame with a 0x0000 pause timer value to disable flow control. this bit is only used for flow control operations and affects both tx and rx operations. bit 3-1 unimplemented: read as 0 bit 0 bufcdec: descriptor buffer count decrement bit the bufcdec bit is a write-1 bit that reads as 0 . when written with a 1 , the descriptor buffer counter, bufcnt, will decrement by one. if bufcnt is incremented by the rx logic at the same time that this bit is written, the bufcnt value will remain unchanged. writing a 0 will have no effect. this bit is only used for rx operations. register 30-1: ethcon1: ethernet contro ller control register 1 (continued) note 1: it is not recommended to clear the rxen bit and then make changes to any rx related field/register. the ethernet controller must be reinitialized (on cleared to 0 ), and then the rx changes applied.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 530 ? 2015-2016 microchip technology inc. register 30-2: ethcon2: ethernet controller control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 rxbufsz<6:4> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 rxbufsz<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-11 unimplemented: read as 0 bit 10-4 rxbufsz<6:0>: rx data buffer size for all rx descriptors (in 16-byte increments) bits 1111111 = rx data buffer size for descriptors is 2032 bytes 1100000 = rx data buffer size for descriptors is 1536 bytes 0000011 = rx data buffer size for descriptors is 48 bytes 0000010 = rx data buffer size for descriptors is 32 bytes 0000001 = rx data buffer size for descriptors is 16 bytes 0000000 = reserved bit 3-0 unimplemented: read as 0 note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 531 pic32mz embedded connectivity with floating point unit (ef) family register 30-3: ethtxst: ethernet cont roller tx packet descriptor start address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txstaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txstaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txstaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 txstaddr<7:2> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-2 txstaddr<31:2>: starting address of first transmit descriptor bits this register should not be written while any transmit, receive or dma operations are in progress. this address must be 4-byte aligned (bits 1-0 must be 00 ). bit 1-0 unimplemented: read as 0 note 1: this register is only used for tx operations. 2: this register will be updated by hardware with the last descriptor used by the last successfully transmitted packet. register 30-4: ethrxst: ethernet cont roller rx packet descriptor start address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxstaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxstaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxstaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 rxstaddr<7:2> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-2 rxstaddr<31:2>: starting address of first receive descriptor bits this register should not be written while any transmit, receive or dma operations are in progress. this address must be 4-byte aligned (bits 1-0 must be 00 ). bit 1-0 unimplemented: read as 0 note 1: this register is only used for rx operations. 2: this register will be updated by hardware with the last descriptor used by the last successfully trans mitted packet.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 532 ? 2015-2016 microchip technology inc. register 30-5: ethht0: ethernet co ntroller hash table 0 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 ht<31:0>: hash table bytes 0-3 bits note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 or the hten bit (ethrxfc<15>) = 0 . register 30-6: ethht1: ethernet co ntroller hash table 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<63:56> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<55:48> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<47:40> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ht<39:32> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 ht<63:32>: hash table bytes 4-7 bits note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 or the hten bit (ethrxfc<15>) = 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 533 pic32mz embedded connectivity with floating point unit (ef) family register 30-7: ethpmm0: ethernet controller pattern match mask 0 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 pmm<31:24>: pattern match mask 3 bits bit 23-16 pmm<23:16>: pattern match mask 2 bits bit 15-8 pmm<15:8>: pattern match mask 1 bits bit 7-0 pmm<7:0>: pattern match mask 0 bits note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 or the pmmode bit (ethrxfc<11:8>) = 0 . register 30-8: ethpmm1: ethernet controller pattern match mask 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<63:56> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<55:48> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<47:40> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmm<39:32> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 pmm<63:56>: pattern match mask 7 bits bit 23-16 pmm<55:48>: pattern match mask 6 bits bit 15-8 pmm<47:40>: pattern match mask 5 bits bit 7-0 pmm<39:32>: pattern match mask 4 bits note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 or the pmmode bit (ethrxfc<11:8>) = 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 534 ? 2015-2016 microchip technology inc. register 30-9: ethpmcs: ethernet controller pattern match checksum register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmcs<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmcs<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-8 pmcs<15:8>: pattern match checksum 1 bits bit 7-0 pmcs<7:0>: pattern match checksum 0 bits note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 or the pmmode bit (ethrxfc<11:8>) = 0 . register 30-10: ethpmo: ethernet controller pattern match offset register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmo<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmo<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 pmo<15:0>: pattern match offset 1 bits note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 or the pmmode bit (ethrxfc<11:8>) = 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 535 pic32mz embedded connectivity with floating point unit (ef) family register 30-11: ethrxfc: ethernet co ntroller receive fi lter configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 hten mpen notpm pmmode<3:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 crcerren crcoken runterren runten ucen notmeen mcen bcen legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 hten: enable hash table filtering bit 1 = enable hash table filtering 0 = disable hash table filtering bit 14 mpen: magic packet? enable bit 1 = enable magic packet filtering 0 = disable magic packet filtering bit 13 unimplemented: read as 0 bit 12 notpm: pattern match inversion bit 1 = the pattern match checksum must not match for a successful pattern match to occur 0 = the pattern match checksum must match for a successful pattern match to occur this bit determines whether pattern match checksum must match in order for a successful pattern match to occur. bit 11-8 pmmode<3:0>: pattern match mode bits 1001 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and ? (packet = magic packet) (1,3) 1000 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and ? (hash table filter match) (1,1) 0111 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and ? (destination address = broadcast address) (1) 0110 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and ? (destination address = broadcast address) (1) 0101 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and ? (destination address = unicast address) (1) 0100 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and ? (destination address = unicast address) (1) 0011 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and ? (destination address = station address) (1) 0010 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) and ? (destination address = station address) (1) 0001 = pattern match is successful if (notpm = 1 xor pattern match checksum matches) (1) 0000 = pattern match is disabled; pattern match is always unsuccessful note 1: xor = true when either one or the other conditions are true, but not both. 2: this hash table filter match is active regardless of the value of the hten bit. 3: this magic packet filter match is active regardless of the value of the mpen bit. note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 536 ? 2015-2016 microchip technology inc. bit 7 crcerren: crc error collection enable bit 1 = the received packet crc must be invalid for the packet to be accepted 0 = disable crc error collection filtering this bit allows the user to collect all packets that have an invalid crc. bit 6 crcoken: crc ok enable bit 1 = the received packet crc must be valid for the packet to be accepted 0 = disable crc filtering this bit allows the user to reject all packets that have an invalid crc. bit 5 runterren: runt error collection enable bit 1 = the received packet must be a runt packet for the packet to be accepted 0 = disable runt error collection filtering this bit allows the user to collect all packets that are runt packets. for this filter, a runt packet is defined as any packet with a size of less than 64 bytes (when crcoken = 0 ) or any packet with a size of less than 64 bytes that has a valid crc (when crcoken = 1 ). bit 4 runten: runt enable bit 1 = the received packet must not be a runt packet for the packet to be accepted 0 = disable runt filtering this bit allows the user to reject all runt packets. for this filter, a runt packet is defined as an y packet with a size of less than 64 bytes. bit 3 ucen: unicast enable bit 1 = enable unicast filtering 0 = disable unicast filtering this bit allows the user to accept all unicast packets whose destination address matches the station address. bit 2 notmeen: not me unicast enable bit 1 = enable not me unicast filtering 0 = disable not me unicast filtering this bit allows the user to accept all unicast packets whose destination address does not match the station address. bit 1 mcen: multicast enable bit 1 = enable multicast filtering 0 = disable multicast filtering this bit allows the user to accept all multicast address packets. bit 0 bcen: broadcast enable bit 1 = enable broadcast filtering 0 = disable broadcast filtering this bit allows the user to accept all broadcast address packets. register 30-11: ethrxfc: ethernet co ntroller receive fi lter configuration register (continued) note 1: xor = true when either one or the other conditions are true, but not both. 2: this hash table filter match is active regardless of the value of the hten bit. 3: this magic packet filter match is active regardless of the value of the mpen bit. note 1: this register is only used for rx operations. 2: the bits in this register may only be changed while the rxen bit (ethcon1<8>) = 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 537 pic32mz embedded connectivity with floating point unit (ef) family register 30-12: ethrxwm: ethernet co ntroller receive watermarks register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxfwm<7:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxewm<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as 0 bit 23-16 rxfwm<7:0>: receive full watermark bits the software controlled rx buffer full watermark pointer is compared against the rx bufcnt to determine the full watermark condition for the fwmark interrupt and for enabling flow control when automatic flow control is enabled. the full watermark pointer should always be greater than the em pty watermark pointer. bit 15-8 unimplemented: read as 0 bit 7-0 rxewm<7:0>: receive empty watermark bits the software controlled rx buffer empty watermark pointer is compared against the rx bufcnt to determine the empty watermark condition for the ewmark interrupt and for disabling flow control when automatic flow control is enabled. the empty watermark pointer should always be less than the full watermark pointer. note: this register is only used for rx operations.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 538 ? 2015-2016 microchip technology inc. register 30-13: ethien: ethernet controller interrupt enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 txbuseie (1) rxbuseie (2) ewmarkie (2) fwmarkie (2) 7:0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 rxdoneie (2) pktpendie (2) rxactie (2) txdoneie (1) txabortie (1) rxbufnaie (2) rxovflwie (2) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as 0 bit 14 txbuseie: transmit bvci bus error interrupt enable bit (1) 1 = enable txbus error interrupt 0 = disable txbus error interrupt bit 13 rxbuseie: receive bvci bus error interrupt enable bit (2) 1 = enable rxbus error interrupt 0 = disable rxbus error interrupt bit 12-10 unimplemented: read as 0 bit 9 ewmarkie: empty watermark interrupt enable bit (2) 1 = enable ewmark interrupt 0 = disable ewmark interrupt bit 8 fwmarkie: full watermark interrupt enable bit (2) 1 = enable fwmark interrupt 0 = disable fwmark interrupt bit 7 rxdoneie: receiver done interrupt enable bit (2) 1 = enable rxdone interrupt 0 = disable rxdone interrupt bit 6 pktpendie: packet pending interrupt enable bit (2) 1 = enable pktpend interrupt 0 = disable pktpend interrupt bit 5 rxactie: rx activity interrupt enable bit 1 = enable rxact interrupt 0 = disable rxact interrupt bit 4 unimplemented: read as 0 bit 3 txdoneie: transmitter done interrupt enable bit (1) 1 = enable txdone interrupt 0 = disable txdone interrupt bit 2 txabortie: transmitter abort interrupt enable bit (1) 1 = enable txabort interrupt 0 = disable txabort interrupt bit 1 rxbufnaie: receive buffer not available interrupt enable bit (2) 1 = enable rxbufna interrupt 0 = disable rxbufna interrupt bit 0 rxovflwie: receive fifo overflow interrupt enable bit (2) 1 = enable rxovflw interrupt 0 = disable rxovflw interrupt note 1: this bit is only used for tx operations. 2: this bit is only used for rx operations.
? 2015-2016 microchip technology inc. ds60001320d-page 539 pic32mz embedded connectivity with floating point unit (ef) family register 30-14: ethirq: ethernet controller interrupt request register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 txbuse rxbuse ewmark fwmark 7:0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 rxdone pktpend rxact txdone txabort rxbufna rxovflw legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as 0 bit 14 txbuse: transmit bvci bus error interrupt bit (2) 1 = bvci bus error has occurred 0 = bvci bus error has not occurred this bit is set when the tx dma encounters a bvci bus error during a memory access. it is cleared by either a reset or cpu write of a 1 to the clr register. bit 13 rxbuse: receive bvci bus error interrupt bit (2) 1 = bvci bus error has occurred 0 = bvci bus error has not occurred this bit is set when the rx dma encounters a bvci bus error during a memory access. it is cleared by either a reset or cpu write of a 1 to the clr register. bit 12-10 unimplemented: read as 0 bit 9 ewmark: empty watermark interrupt bit (2) 1 = empty watermark pointer reached 0 = no interrupt pending this bit is set when the rx descriptor buffer count is less than or equal to the value in the rxewm bit (ethrxwm<0:7>) value. it is cleared by bufcnt bit (ethstat<16:23>) being incremented by hardware. writing a 0 or a 1 has no effect. bit 8 fwmark: full watermark interrupt bit (2) 1 = full watermark pointer reached 0 = no interrupt pending this bit is set when the rx descriptor buffer count is greater than or equal to the value in the rxfwm bit (ethrxwm<16:23>) field. it is cleared by writing the bufcdec (ethcon1<0>) bit to decrement the bufcnt counter. writing a 0 or a 1 has no effect. note 1: this bit is only used for tx operations. 2: this bit is are only used for rx operations. note: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 540 ? 2015-2016 microchip technology inc. bit 7 rxdone: receive done interrupt bit (2) 1 = rx packet was successfully received 0 = no interrupt pending this bit is set whenever an rx packet is successfully received. it is cleared by either a reset or cpu write of a 1 to the clr register. bit 6 pktpend: packet pending interrupt bit (2) 1 = rx packet pending in memory 0 = rx packet is not pending in memory this bit is set when the bufcnt counter has a value other than 0 . it is cleared by either a reset or by writing the bufcdec bit to decrement the bufcnt counter. writing a 0 or a 1 has no effect. bit 5 rxact: receive activity interrupt bit (2) 1 = rx packet data was successfully received 0 = no interrupt pending this bit is set whenever rx packet data is stored in the rxbm fifo. it is cleared by either a reset or cpu write of a 1 to the clr register. bit 4 unimplemented: read as 0 bit 3 txdone: transmit done interrupt bit (2) 1 = tx packet was successfully sent 0 = no interrupt pending this bit is set when the currently transmitted tx packet completes transmission, and the transmit status vector is loaded into the first descriptor used for the packet. it is cleared by either a rese t or cpu write of a 1 to the clr register. bit 2 txabort: transmit abort condition interrupt bit (2) 1 = tx abort condition occurred on the last tx packet 0 = no interrupt pending this bit is set when the mac aborts the transmission of a tx packet for one of the following reasons: jumbo tx packet abort underrun abort excessive defer abort late collision abort excessive collisions abort this bit is cleared by either a reset or cpu write of a 1 to the clr register. bit 1 rxbufna: receive buffer not available interrupt bit (2) 1 = rx buffer descriptor not available condition has occurred 0 = no interrupt pending this bit is set by a rx buffer descriptor overrun condition. it is cleared by either a reset or a cpu writ e of a 1 to the clr register. bit 0 rxovflw: receive fifo over flow error bit (2) 1 = rx fifo overflow error condition has occurred 0 = no interrupt pending rxovflw is set by the rxbm logic for an rx fifo overflow condition. it is cleared by either a reset or cpu write of a 1 to the clr register. register 30-14: ethirq: ethernet controller interrupt request register note 1: this bit is only used for tx operations. 2: this bit is are only used for rx operations. note: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
? 2015-2016 microchip technology inc. ds60001320d-page 541 pic32mz embedded connectivity with floating point unit (ef) family register 30-15: ethstat: ethernet controller status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufcnt<7:0> (1) 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ethbusy (5) txbusy (2,6) rxbusy (3,6) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as 0 bit 23-16 bufcnt<7:0>: packet buffer count bits (1) number of packet buffers received in memory. once a packet has been successfully received, this regis ter is incremented by hardware based on the number of descriptors used by the packet. software decr ements the counter (by writing to the bufcdec bit (ethcon1<0>) for each descriptor used) after a packet has been read out of the buffer. the register does not roll over (0xff to 0x00) when hardware tries to increment the register and the register is already at 0xff. conv ersely, the register does not roll under (0x00 to 0xff) when software tries to decrement the register and the register is already at 0x0000. when software attempt s to decrement the counter at the same time that the hardware attempts to increment the counter, the counter value will remain unchanged. when this register value reaches 0xff, the rx logic will halt (only if automatic flow control is enabled) awaiting software to write the bufcdec bit in order to decrement the register below 0xff. if automatic flow control is disabled, the rxdma will continue process ing and the bufcnt will saturate at a value of 0xff. when this register is non-zero, the pktpend status bit will be set and an interrupt may be generated, depending on the value of the ethien bit register. when the ethrxst register is written, the bufcnt counter is automatically cleared to 0x00. note: bufcnt will not be cleared when on is set to 0 . this enables software to continue to utilize and decrement this count. bit 15-8 unimplemented: read as 0 bit 7 ethbusy: ethernet module busy bit (5) 1 = ethernet logic has been turned on (on (ethcon1<15>) = 1 ) or is completing a transaction 0 = ethernet logic is idle this bit indicates that the module has been turned on or is completing a transaction after being turned off. note 1: this bit is only used for rx operations. 2: this bit is only affected by tx operations. 3: this bit is only affected by rx operations. 4: this bit is affected by tx and rx operations. 5: this bit will be set when the on bit (ethcon1<15>) = 1 . 6: this bit will be cleared when the on bit (ethcon1<15>) = 0 .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 542 ? 2015-2016 microchip technology inc. bit 6 txbusy: transmit busy bit (2,6) 1 = tx logic is receiving data 0 = tx logic is idle this bit indicates that a packet is currently being transmitted. a change in this status bit is not necessarily reflected by the txdone interrupt, as tx packets may be aborted or rejected by the mac. bit 5 rxbusy: receive busy bit (3,6) 1 = rx logic is receiving data 0 = rx logic is idle this bit indicates that a packet is currently being received. a change in this status bit is not necessarily reflected by the rxdone interrupt, as rx packets may be aborted or rejected by the rx filter. bit 4-0 unimplemented: read as 0 register 30-15: ethstat: ethernet cont roller status register (continued) note 1: this bit is only used for rx operations. 2: this bit is only affected by tx operations. 3: this bit is only affected by rx operations. 4: this bit is affected by tx and rx operations. 5: this bit will be set when the on bit (ethcon1<15>) = 1 . 6: this bit will be cleared when the on bit (ethcon1<15>) = 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 543 pic32mz embedded connectivity with floating point unit (ef) family register 30-16: ethrxovflow: ethernet cont roller receive overflow statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxovflwcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rxovflwcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 rxovflwcnt<15:0>: dropped receive frames count bits increment counter for frames accepted by the rx filter and subsequently dropped due to internal receive error (rxfifo overrun). this event also sets the rxovflw bit (ethirq<0>) interrupt flag. note 1: this register is only used for rx operations. 2: this register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are 0 . 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 544 ? 2015-2016 microchip technology inc. register 30-17: ethfrmtxok: etherne t controller frames transmitted ok statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 frmtxokcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 frmtxokcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 frmtxokcnt<15:0>: frame transmitted ok count bits increment counter for frames successfully transmitted. note 1: this register is only used for tx operations. 2: this register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are 0 . 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
? 2015-2016 microchip technology inc. ds60001320d-page 545 pic32mz embedded connectivity with floating point unit (ef) family register 30-18: ethscolfrm: ethernet controller single collision frames statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 scolfrmcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 scolfrmcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 scolfrmcnt<15:0>: single collision frame count bits increment count for frames that were successfully transmitted on the second try. note 1: this register is only used for tx operations. 2: this register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are 0 . 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 546 ? 2015-2016 microchip technology inc. register 30-19: ethmcolfrm: ethernet controller multiple collision frames statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mcolfrmcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mcolfrmcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 mcolfrmcnt<15:0>: multiple collision frame count bits increment count for frames that were successfully transmitted after there was more than one collision. note 1: this register is only used for tx operations. 2: this register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are 0 . 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
? 2015-2016 microchip technology inc. ds60001320d-page 547 pic32mz embedded connectivity with floating point unit (ef) family register 30-20: ethfrmrxok: ethern et controller frames received ok statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 frmrxokcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 frmrxokcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 frmrxokcnt<15:0>: frames received ok count bits increment count for frames received successfully by the rx filter. this c ount will not be incremented if there is a frame check sequence (fcs) or alignment error. note 1: this register is only used for rx operations. 2: this register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are 0 . 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should only be done for debug/test purposes.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 548 ? 2015-2016 microchip technology inc. register 30-21: ethfcserr: ethernet cont roller frame check sequence error statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fcserrcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fcserrcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 fcserrcnt<15:0>: fcs error count bits increment count for frames received with fcs error and the frame length in bits is an integral multiple of 8 bits. note 1: this register is only used for rx operations. 2: this register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are 0 . 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should be only done for debug/test purposes.
? 2015-2016 microchip technology inc. ds60001320d-page 549 pic32mz embedded connectivity with floating point unit (ef) family register 30-22: ethalgnerr: ethernet co ntroller alignment errors statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 algnerrcnt<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 algnerrcnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 algnerrcnt<15:0>: alignment error count bits increment count for frames with alignment errors. note that an alignment error is a frame that has an fcs error and the frame length in bits is not an integral multiple of 8 bits (a.k.a., dribble nibble) note 1: this register is only used for rx operations. 2: this register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are 0 . 3: it is recommended to use the set, clr, or inv registers to set or clear any bit in this register. setting or clearing any bits in this register should be only done for debug/test purposes.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 550 ? 2015-2016 microchip technology inc. register 30-23: emac1cfg1: ethernet controller mac conf iguration 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-1 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 soft reset sim reset reset rmcs reset rfun reset tmcs reset tfun 7:0 u-0 u-0 u-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-1 loopback tx pause rx pause passall rx enable legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 softreset: soft reset bit setting this bit will put the macmii in reset. its default value is 1 . bit 14 simreset: simulation reset bit setting this bit will cause a reset to the random number generator within the transmit function. bit 13-12 unimplemented: read as 0 bit 11 resetrmcs: reset mcs/rx bit setting this bit will put the mac control sub-layer/receive domain logic in reset. bit 10 resetrfun: reset rx function bit setting this bit will put the mac receive function logic in reset. bit 9 resettmcs: reset mcs/tx bit setting this bit will put the mac control sub-layer/tx domain logic in reset. bit 8 resettfun: reset tx function bit setting this bit will put the mac transmit function logic in reset. bit 7-5 unimplemented: read as 0 bit 4 loopback: mac loopback mode bit 1 = mac transmit interface is loop backed to the mac receive interface 0 = mac normal operation bit 3 txpause: mac tx flow control bit 1 = pause flow control frames are allowed to be transmitted 0 = pause flow control frames are blocked bit 2 rxpause: mac rx flow control bit 1 = the mac acts upon received pause flow control frames 0 = received pause flow control frames are ignored bit 1 passall: mac pass all receive frames bit 1 = the mac will accept all frames regardless of type (normal vs. control) 0 = the received control frames are ignored bit 0 rxenable: mac receive enable bit 1 = enable the mac receiving of frames 0 = disable the mac receiving of frames note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). ? 8-bit accesses are not allowed and are ignored by the hardware.
? 2015-2016 microchip technology inc. ds60001320d-page 551 pic32mz embedded connectivity with floating point unit (ef) family register 30-24: emac1cfg2: ethernet controller mac conf iguration 2 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 25/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 excess dfr bpnobk off nobk off longpre purepre 7:0 r/w-1 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-1 r/w-0 auto pad (1,2) vlan pad (1,2) pad enable (1,3) crc enable delaycrc hugefrm lengthck fulldplx legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as 0 bit 14 excessder: excess defer bit 1 = the mac will defer to carrier indefinitely as per the standard 0 = the mac will abort when the excessive deferral limit is reached bit 13 bpnobkoff: backpressure/no backoff bit 1 = the mac after incidentally causing a collision during backpressure will immediately retransmit withou t backoff reducing the chance of further collisions and ensuring transmit packets get sent 0 = the mac will not remove the backoff bit 12 nobkoff: no backoff bit 1 = following a collision, the mac will immediately retransmit rather than using the binary exponential back- off algorithm as specified in the standard 0 = following a collision, the mac will use the binary exponential backoff algorithm bit 11-10 unimplemented: read as 0 bit 9 longpre: long preamble enforcement bit 1 = the mac only allows receive packets which contain preamble fields less than 12 bytes in length 0 = the mac allows any length preamble as per the standard bit 8 purepre: pure preamble enforcement bit 1 = the mac will verify the content of the preamble to ensure it contains 0x55 and is error-free. a packet with errors in its preamble is discarded 0 = the mac does not perform any preamble checking bit 7 autopad: automatic detect pad enable bit (1,2) 1 = the mac will automatically detect the type of frame, either tagged or untagged, by comparing the two octets following the source address with 0x8100 (vlan protocol id) and pad accordingly 0 = the mac does not perform automatic detection note 1: table 30-6 provides a description of the pad function based on the configuration of this register. 2: this bit is ignored if the padenable bit is cleared. 3: this bit is used in conjunction with the autopad and vlanpad bits. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). ? 8-bit accesses are not allowed and are ignored by the hardware
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 552 ? 2015-2016 microchip technology inc. table 30-6: pad operation bit 6 vlanpad: vlan pad enable bit (1,2) 1 = the mac will pad all short frames to 64 bytes and append a valid crc 0 = the mac does not perform padding of short frames bit 5 padenable: pad/crc enable bit (1,3) 1 = the mac will pad all short frames 0 = the frames presented to the mac have a valid length bit 4 crcenable: crc enable1 bit 1 = the mac will append a crc to every frame whether padding was required or not. must be set if the padenable bit is set. 0 = the frames presented to the mac have a valid crc bit 3 delaycrc: delayed crc bit this bit determines the number of bytes, if any, of proprietary header information that exist on the front of the ieee 802.3 frames. 1 = four bytes of header (ignored by the crc function) 0 = no proprietary header bit 2 hugefrm: huge frame enable bit 1 = frames of any length are transmitted and received 0 = huge frames are not allowed for receive or transmit bit 1 lengthck: frame length checking bit 1 = both transmit and receive frame lengths are compared to the length/type field. if the length/type field represents a length then the check is performed. mismatches are reported on the transmit/receive statistics vector. 0 = length/type field check is not performed bit 0 fulldplx: full-duplex operation bit 1 = the mac operates in full-duplex mode 0 = the mac operates in half-duplex mode register 30-24: emac1cfg2: ethernet controller mac conf iguration 2 register note 1: table 30-6 provides a description of the pad function based on the configuration of this register. 2: this bit is ignored if the padenable bit is cleared. 3: this bit is used in conjunction with the autopad and vlanpad bits. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). ? 8-bit accesses are not allowed and are ignored by the hardware type autopad vlanpad padenable action any x x 0 no pad, check crc any 0 0 1 pad to 60 bytes, append crc any x 1 1 pad to 64 bytes, append crc any 1 0 1 if untagged: pad to 60 bytes, append crc if vlan tagged: pad to 64 bytes, append crc
? 2015-2016 microchip technology inc. ds60001320d-page 553 pic32mz embedded connectivity with floating point unit (ef) family register 30-25: emac1ipgt: ethernet controller mac back-to-back interpacket gap register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-1 r/w-0 b2bipktgp<6:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-7 unimplemented: read as 0 bit 6-0 b2bipktgp<6:0>: back-to-back interpacket gap bits this is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet, to the beginning of the next. in full-duplex mode, the register value should be the desired period in nibble times minus 3. in half-duplex mode, the register value should be the desired period in nibble times minus 6. in full-duplex the recommended setting is 0x15 (21d), which re p- resents the minimum ipg of 0.96 s (in 100 mbps) or 9.6 s (in 10 mbps). in half-duplex mode, the rec- ommended setting is 0x12 (18d), which also represents the minimum ipg of 0.96 s (in 100 mbps) or 9.6 s (in 10 mbps). note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv regist ers). ? 8-bit accesses are not allowed and are ignored by the hardware.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 554 ? 2015-2016 microchip technology inc. register 30-26: emac1ipgr: ethe rnet controller mac non-back-to-back interpacket gap register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 nb2bipktgp1<6:0> 7:0 u-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-1 r/w-0 nb2bipktgp2<6:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as 0 bit 14-8 nb2bipktgp1<6:0>: non-back-to-back interpacket gap part 1 bits this is a programmable field representing the optional carriersense window referenced in section 4.2.3.2.1 deference of the ieee 80.23 specification. if carrier is detected during the timing of ipgr1, the mac defers to carrier. if, however, carrier becomes after ipgr1, the mac continues timing ipgr2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. its range of values is 0x0 to ipgr2. its recommend value is 0xc (12d). bit 7 unimplemented: read as 0 bit 6-0 nb2bipktgp2<6:0>: non-back-to-back interpacket gap part 2 bits this is a programmable field representing the non-back-to-back inter-packet-gap. its recommended value is 0x12 (18d), which represents the minimum ipg of 0.96 s (in 100 mbps) or 9.6 s (in 10 mbps). note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers) . ? 8-bit accesses are not allowed and are ignored by the hardware.
? 2015-2016 microchip technology inc. ds60001320d-page 555 pic32mz embedded connectivity with floating point unit (ef) family register 30-27: emac1clrt: ethernet co ntroller mac collision window/retry limit register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 r/w-1 r/w-1 r/w-0 r/w-1 r/w-1 r/w-1 cwindow<5:0> 7:0 u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 retx<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-14 unimplemented: read as 0 bit 13-8 cwindow<5:0>: collision window bits this is a programmable field representing the slot time or collision window during which co llisions occur in properly configured networks. since the collision window starts at the beginning of transmissio n, the pre- amble and sfd is included. its default of 0x37 (55d) corresponds to the count of frame bytes at the end of the window. bit 7-4 unimplemented: read as 0 bit 3-0 retx<3:0>: retransmission maximum bits this is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. the standard specifies the maximum number of attempts (attemptlimit) to be 0xf (15d). its default is 0xf. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv regist ers). ? 8-bit accesses are not allowed and are ignored by the hardware.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 556 ? 2015-2016 microchip technology inc. register 30-28: emac1maxf: ethernet controller mac maximum frame length register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 macmaxf<15:8> (1) 7:0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-1 r/w-1 r/w-1 r/w-0 macmaxf<7:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 macmaxf<15:0>: maximum frame length bits (1) these bits reset to 0x05ee, which represents a maximum receive frame of 1518 octets. an untagged maximum size ethernet frame is 1518 octets. a tagged frame adds four octets for a total of 1522 octets. if a shorter/longer maximum length restriction is desired, program this 16-bit field. note 1: if a proprietary header is allowed, this bit should be adjusted accordingly. for example, if 4-byte h eaders are prepended to frames, macmaxf could be set to 1527 octets. this would allow the maximum vlan tagged frame plus the 4-byte header. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers) . ? 8-bit accesses are not allowed and are ignored by the hardware.
? 2015-2016 microchip technology inc. ds60001320d-page 557 pic32mz embedded connectivity with floating point unit (ef) family register 30-29: emac1supp: ethernet controller mac phy support register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 r/w-0 u-0 u-0 r/w-0 resetrmii (1) speedrmii (1) 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-12 unimplemented: read as 0 bit 11 resetrmii: reset rmii logic bit (1) 1 = reset the mac rmii module 0 = normal operation. bit 10-9 unimplemented: read as 0 bit 8 speedrmii: rmii speed bit (1) this bit configures the reduced mii logic for the current operating speed. 1 = rmii is running at 100 mbps 0 = rmii is running at 10 mbps bit 7-0 unimplemented: read as 0 note 1: this bit is only used for the rmii module. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). ? 8-bit accesses are not allowed and are ignored by the hardware.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 558 ? 2015-2016 microchip technology inc. register 30-30: emac1test: etherne t controller mac test register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 testbp testpause (1) shrtqnta (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-3 unimplemented: read as 0 bit 2 testbp: test backpressure bit 1 = the mac will assert backpressure on the link. backpressure causes preamble to be transmitted, ra ising carrier sense. a transmit packet from the system will be sent during backpressure. 0 = normal operation bit 1 testpause: test pause bit (1) 1 = the mac control sub-layer will inhibit transmissions, just as if a pause receive control frame with a non-zero pause time parameter was received 0 = normal operation bit 0 shrtqnta: shortcut pause quanta bit (1) 1 = the mac reduces the effective pause quanta from 64 byte-times to 1 byte-time 0 = normal operation note 1: this bit is only used for testing purposes. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers) . ? 8-bit accesses are not allowed and are ignored by the hardware.
? 2015-2016 microchip technology inc. ds60001320d-page 559 pic32mz embedded connectivity with floating point unit (ef) family table 30-7: miim clock selection register 30-31: emac1mcfg: ethernet controller mac mii management configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 resetmgmt 7:0 u-0 u-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 clksel<3:0> (1) nopre scaninc legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 resetmgmt: test reset mii management bit 1 = reset the mii management module 0 = normal operation bit 14-6 unimplemented: read as 0 bit 5-2 clksel<3:0>: mii management clock select 1 bits (1) these bits are used by the clock divide logic in creating the mii management clock (mdc), which the ieee 802.3 specification defines to be no faster than 2.5 mhz. some phys support clock rates up to 12.5 mhz. bit 1 nopre: suppress preamble bit 1 = the mii management will perform read/write cycles without the 32-bit preamble field. some phys support suppressed preamble 0 = normal read/write cycles are performed bit 0 scaninc: scan increment bit 1 = the mii management module will perform read cycles across a range of phys. the read cycles will start from address 1 through the value set in emac1madr 0 = continuous reads of the same phy note 1: table 30-7 provides a description of the clock divider encoding. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). ? 8-bit accesses are not allowed and are ignored by the hardware. miim clock select emac1mcfg<5:2> t pbclk 5 divided by 4 000x t pbclk 5 divided by 6 0010 t pbclk 5 divided by 8 0011 t pbclk 5 divided by 10 0100 t pbclk 5 divided by 14 0101 t pbclk 5 divided by 20 0110 t pbclk 5 divided by 28 0111 t pbclk 5 divided by 40 1000 t pbclk 5 divided by 48 1001 t pbclk 5 divided by 50 1010 undefined any other combination
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 560 ? 2015-2016 microchip technology inc. register 30-32: emac1mcmd: ethernet controller mac mii management command register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 scan read legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-2 unimplemented: read as 0 bit 1 scan: mii management scan mode bit 1 = the mii management module will perform read cycles continuously (for example, useful for monitoring the link fail) 0 = normal operation bit 0 read: mii management read command bit 1 = the mii management module will perform a single read cycle. the read data is returned in the emac1mrdd register 0 = the mii management module will perform a write cycle. the write data is taken from the emac1mwtd register note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). ? 8-bit accesses are not allowed and are ignored by the hardware.
? 2015-2016 microchip technology inc. ds60001320d-page 561 pic32mz embedded connectivity with floating point unit (ef) family register 30-33: emac1madr: ethernet controller mac mii management address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 phyaddr<4:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 regaddr<4:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-13 unimplemented: read as 0 bit 12-8 phyaddr<4:0>: mii management phy address bits this field represents the 5-bit phy address field of management cycles. up to 31 phys can be addressed (0 is reserved). bit 7-5 unimplemented: read as 0 bit 4-0 regaddr<4:0>: mii management register address bits this field represents the 5-bit register address field of management cycles. up to 32 registers can be accessed. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv regist ers). ? 8-bit accesses are not allowed and are ignored by the hardware.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 562 ? 2015-2016 microchip technology inc. register 30-34: emac1mwtd: ethernet controller mac mii management write data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mwtd<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mwtd<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 mwtd<15:0>: mii management write data bits when written, a mii management write cycle is performed using the 16-bit data and the preconfigured ph y and register addresses from the emac1madr register. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). ? 8-bit accesses are not allowed and are ignored by the hardware. register 30-35: emac1mrdd: ethernet co ntroller mac mii management read data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mrdd<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mrdd<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-0 mrdd<15:0>: mii management read data bits following a mii management read cycle, the 16-bit data can be read from this location. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). ? 8-bit accesses are not allowed and are ignored by the hardware.
? 2015-2016 microchip technology inc. ds60001320d-page 563 pic32mz embedded connectivity with floating point unit (ef) family register 30-36: emac1mind: ethernet cont roller mac mii management indicators register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 linkfail notvalid scan miimbusy legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as 0 bit 3 linkfail: link fail bit when 1 is returned - indicates link fail has occurred. this bit reflects the value last read from the phy status register. bit 2 notvalid: mii management read data not valid bit when 1 is returned - indicates an mii management read cycle has not completed and the read data is not yet valid. bit 1 scan: mii management scanning bit when 1 is returned - indicates a scan operation (continuous mii management read cycles) is in progress. bit 0 miimbusy: mii management busy bit when 1 is returned - indicates mii management module is currently performing an mii management read or write cycle. note: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers) . ? 8-bit accesses are not allowed and are ignored by the hardware.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 564 ? 2015-2016 microchip technology inc. register 30-37: emac1sa0: ethernet co ntroller mac station address 0 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p stnaddr6<7:0> 7:0 r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p stnaddr5<7:0> legend: p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-8 stnaddr6<7:0>: station address octet 6 bits these bits hold the sixth transmitted octet of the station address. bit 7-0 stnaddr5<7:0>: station address octet 5 bits these bits hold the fifth transmitted octet of the station address. note 1: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). ? 8-bit accesses are not allowed and are ignored by the hardware. 2: this register is loaded at reset from the factory preprogrammed station address.
? 2015-2016 microchip technology inc. ds60001320d-page 565 pic32mz embedded connectivity with floating point unit (ef) family register 30-38: emac1sa1: ethernet co ntroller mac station address 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p stnaddr4<7:0> 7:0 r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p stnaddr3<7:0> legend: p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15-8 stnaddr4<7:0>: station address octet 4 bits these bits hold the fourth transmitted octet of the station address. bit 7-0 stnaddr3<7:0>: station address octet 3 bits these bits hold the third transmitted octet of the station address. note 1: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). ? 8-bit accesses are not allowed and are ignored by the hardware. 2: this register is loaded at reset from the factory preprogrammed station address.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 566 ? 2015-2016 microchip technology inc. register 30-39: emac1sa2: ethernet co ntroller mac station address 2 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p stnaddr2<7:0> 7:0 r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p r/w-p stnaddr1<7:0> legend: p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 reserved: maintain as 0 ; ignore read bit 15-8 stnaddr2<7:0>: station address octet 2 bits these bits hold the second transmitted octet of the station address. bit 7-0 stnaddr1<7:0>: station address octet 1 bits these bits hold the most significant (first transmitted) octet of the station address. note 1: both 16-bit and 32-bit accesses are allowed to these registers (including the set, clr and inv registers). ? 8-bit accesses are not allowed and are ignored by the hardware. 2: this register is loaded at reset from the factory preprogrammed station address.
? 2015-2016 microchip technology inc. ds60001320d-page 567 pic32mz embedded connectivity with floating point unit (ef) family 31.0 comparator the analog comparator module consists of two comparators that can be configured in a variety of ways. the following are key features of the analog compara - tor module: differential inputs rail-to-rail operation selectable output polarity selectable inputs: - analog inputs multiplexed with i/o pins - on-chip internal absolute voltage reference - comparator voltage reference (cv ref ) selectable interrupt generation a block diagram of the comparator module is illustrated in figure 31-1 . figure 31-1: compar ator block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 19. comparator (ds60001110) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). cv ref (1) internal (1.2v) c2ind c2ina c2out cmp2 coe (cm2con<14>) cref cch<1:0> (cm2con<1:0>) cpol c2inc c2inb c1ind c1ina c1out cmp1 coe (cm1con<14>) cref cch<1:0> (cm1con<1:0>) cpol c1inc c1inb cout (cm1con<8>) cout (cm2con<8>) and note 1: internally connected. see section 32.0 comparator voltage reference (cv ref ) for more information. (cm1con<4>) (cm1con<13>) (cm2con<4>) (cm2con<13>) dq pbclk3 c2out (cmstat<1>) trigger to adc dq pbclk3 c1out (cmstat<2>) and trigger to adc
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 568 ? 2015-2016 microchip technology inc. 31.1 comparator control registers table 31-1: comparator register map virtual address (bf84_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 c000 cm1con 31:16 0000 15:0 on coe cpol cout evpol<1:0> cref cch<1:0> 00c3 c010 cm2con 31:16 0000 15:0 on coe cpol cout evpol<1:0> cref cch<1:0> 00c3 c060 cmstat 31:16 0000 15:0 c2out c1out 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offs ets of 0x4, 0x8 and 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 569 pic32mz embedded connectivity with floating point unit (ef) family register 31-1: cmxcon: comparator control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 r-0 on coe cpol (1) c o u t 7:0 r/w-1 r/w-1 u-0 r/w-0 u-0 u-0 r/w-1 r/w-1 evpol<1:0> c r e f cch<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 on: comparator on bit 1 = module is enabled. setting this bit does not affect the other bits in this register 0 = module is disabled and does not consume current. clearing this bit does not affect the other bits in this register bit 14 coe: comparator output enable bit 1 = comparator output is driven on the output cxout pin 0 = comparator output is not driven on the output cxout pin bit 13 cpol: comparator output inversion bit (1) 1 = output is inverted 0 = output is not inverted bit 12-9 unimplemented: read as 0 bit 8 cout: comparator output bit 1 = output of the comparator is a 1 0 = output of the comparator is a 0 bit 7-6 evpol<1:0>: interrupt event polarity select bits 11 = comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = comparator interrupt is generated on a high-to-low transition of the comparator output 01 = comparator interrupt is generated on a low-to-high transition of the comparator output 00 = comparator interrupt generation is disabled bit 5 unimplemented: read as 0 bit 4 cref: comparator positive input configure bit 1 = comparator non-inverting input is connected to the internal cv ref 0 = comparator non-inverting input is connected to the c x ina pin bit 3-2 unimplemented: read as 0 bit 1-0 cch<1:0>: comparator negative input select bits for comparator 11 = comparator inverting input is connected to the iv ref 10 = comparator inverting input is connected to the cxind pin 01 = comparator inverting input is connected to the cxinc pin 00 = comparator inverting input is connected to the cxinb pin note 1: setting this bit will invert the signal to the comparator interrupt generator as well. this will result in an interrupt being generated on the opposite edge from the one selected by evpol<1:0>.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 570 ? 2015-2016 microchip technology inc. register 31-2: cmstat: comparator status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 7:0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 r-0 c2out c1out legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-2 unimplemented: read as 0 bit 1 c2out: comparator output bit 1 = output of comparator 2 is a 1 0 = output of comparator 2 is a 0 bit 0 c1out: comparator output bit 1 = output of comparator 1 is a 1 0 = output of comparator 1 is a 0
? 2015-2016 microchip technology inc. ds60001320d-page 571 pic32mz embedded connectivity with floating point unit (ef) family 32.0 comparator voltage reference (cv ref ) the cv ref module is a 16-tap, resistor ladder network that provides a selectable reference voltage. although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. the resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. the modules supply reference can be pro - vided from either device v dd /v ss or an external voltage reference. the cv ref output is available for the comparators and typically available for pin output. the comparator voltage reference has the following features: high and low range selection sixteen output levels available for each range internally connected to comparators to conserve device pins output can be connected to a pin a block diagram of the cv ref module is illustrated in figure 32-1 . figure 32-1: comparator voltage reference block diagram note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 20. comparator voltage reference (cv ref ) (ds60001109) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32) . 16-to-1 mux cvr<3:0> 8r r cvren cvrss = 0 av dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 rr r r r r 16 steps cvrr cv refout av ss cvrcon cv ref cv rsrc
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 572 ? 2015-2016 microchip technology inc. 32.1 comparator voltage reference control registers table 32-1: comparator voltage reference register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0e00 cvrcon 31:16 0000 15:0 on cvroe cvrr cvrss cvr<3:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: the register in this table has corresponding clr, set and inv registers at their virtual addresses, plu s offsets of 0x4, 0x8 an d 0xc, respectively. see section 12.3 clr, set, and inv registers for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 573 pic32mz embedded connectivity with floating point unit (ef) family register 32-1: cvrcon: comparator vo ltage reference control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 15:8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 on 7:0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cvroe cvrr cvrss cvr<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as 0 bit 15 on: comparator voltage reference on bit 1 = module is enabled ? setting this bit does not affect other bits in the register. 0 = module is disabled and does not consume current. ? clearing this bit does not affect the other bits in the register. bit 14-7 unimplemented: read as 0 bit 6 cvroe: cv refout enable bit 1 = voltage level is output on cv refout pin 0 = voltage level is disconnected from cv refout pin bit 5 cvrr: cv ref range selection bit 1 = 0 to 0.67 cv rsrc , with cv rsrc /24 step size 0 = 0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size bit 4 cvrss: cv ref source selection bit 1 = comparator voltage reference source, cv rsrc = (v ref +) C (v ref -) 0 = comparator voltage reference source, cv rsrc = av dd C av ss bit 3-0 cvr<3:0>: cv ref value selection 0 ? cvr<3:0> ? 15 bits when cvrr = 1 : cv ref = (cvr<3:0>/24) ? (cv rsrc ) when cvrr = 0 : cv ref = 1/4 ? (cv rsrc ) + (cvr<3:0>/32) ? (cv rsrc )
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 574 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 575 pic32mz embedded connectivity with floating point unit (ef) family 33.0 power-saving features this section describes power-saving features for the pic32mz ef devices. these devices offer various methods and modes that allow the user to balance power consumption with device performance. in all of the methods and modes described in this section, power-saving is controlled by software. 33.1 power saving with cpu running when the cpu is running, power consumption can be controlled by reducing the cpu clock frequency, lowering the speed of pbclk7, or selecting a lower power clock source (i.e., lprc or s osc ). in addition, the peripheral bus scaling mode is available for each peripheral bus where peripherals are clocked at reduced speed by selecting a higher divider for the associated pbclkx, or by disabling the clock completely. 33.2 power-saving with cpu halted peripherals and the cpu can be halted or disabled to further reduce power consumption. 33.2.1 sleep mode sleep mode has the lowest power consumption of the device power-saving operating modes. the cpu and most peripherals are halted and the associated clocks are disabled. select peripherals can continue to operate in sleep mode and can be used to wake the device from sleep. see the individual peripheral module sections for descriptions of behavior in sleep. sleep mode includes the following characteristics: there can be a wake-up delay based on the oscillator selection the fail-safe clock monitor (fscm) does not operate during sleep mode the bor circuit remains operative during sleep mode the wdt, if enabled, is not automatically cleared prior to entering sleep mode some peripherals can continue to operate at limited functionality in sleep mode. these peripherals include i/o pins that detect a change in the input signal, wdt, adc, uart and peripherals that use an external clock input or the internal lprc oscillator (e.g., rtcc, timer1 and input capture). i/o pins continue to sink or source current in the same manner as they do when the device is not in sleep the processor will exit, or wake-up, from sleep on one of the following events: on any interrupt from an enabled source that is operating in sleep. the interrupt priority must be greater than the current cpu priority. on any form of device reset on a wdt time-out if the interrupt priority is lower than or equal to the current priority, the cpu will remain halted, but the peripheral bus clocks will start running and the device will enter into idle mode. 33.2.2 idle mode in idle mode, the cpu is halted; however, all clocks are still enabled. this allows peripherals to continue to operate. peripherals can be individually configured to halt when entering idle by setting their respective sidl bit. latency, when exiting idle mode, is very low due to the cpu oscillator source remaining active. the device enters idle mode when the slpen bit (osccon<4>) is clear and a wait instruction is executed. the processor will wake or exit from idle mode on the following events: on any interrupt event for which the interrupt source is enabled. the priority of the interrupt event must be greater than the current priority of the cpu. if the priority of the interrupt event is lower than or equal to current priority of the cpu, the cpu will remain halted and the device will remain in idle mode. on any form of device reset on a wdt time-out interrupt note: this data sheet summarizes the features of the pic32mz ef family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 10. power- saving features (ds60001130) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 576 ? 2015-2016 microchip technology inc. 33.3 peripheral module disable the peripheral module disable (pmd) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. when a peripheral is disabled using the appropriate pmd control bit, the peripheral is in a minimum power consumption state. the control and status registers associated with the peripheral are also disabled, so writes to those registers do not have effect and read values are invalid. to disable a peripheral, the associated pmdx bit must be set to 1 . to enable a peripheral, the associated pmdx bit must be cleared (default). see table 33-1 for more information. note: disabling a peripheral module while its on bit is set, may result in undefined behavior. the on bit for the associated peripheral module must be cleared prior to disable a module via the pmdx bits. table 33-1: peripheral module disable bits and locations (1) peripheral pmdx bit name register name and bit location adc adcmd pmd1<0> comparator voltage reference cvrmd pmd1<12> comparator 1 cmp1md pmd2<0> comparator 2 cmp2md pmd2<1> input capture 1 ic1md pmd3<0> input capture 2 ic2md pmd3<1> input capture 3 ic3md pmd3<2> input capture 4 ic4md pmd3<3> input capture 5 ic5md pmd3<4> input capture 6 ic6md pmd3<5> input capture 7 ic7md pmd3<6> input capture 8 ic8md pmd3<7> input capture 9 ic9md pmd3<8> output compare 1 oc1md pmd3<16> output compare 2 oc2md pmd3<17> output compare 3 oc3md pmd3<18> output compare 4 oc4md pmd3<19> output compare 5 oc5md pmd3<20> output compare 6 oc6md pmd3<21> output compare 7 oc7md pmd3<22> output compare 8 oc8md pmd3<23> output compare 9 oc9md pmd3<24> timer1 t1md pmd4<0> timer2 t2md pmd4<1> timer3 t3md pmd4<2> timer4 t4md pmd4<3> timer5 t5md pmd4<4> timer6 t6md pmd4<5> timer7 t7md pmd4<6> timer8 t8md pmd4<7> timer9 t9md pmd4<8> uart1 u1md pmd5<0> uart2 u2md pmd5<1> note 1: not all modules and associated pmdx bits are available on all devices. see table 1: pic32mz ef family features for the lists of available peripherals. 2: module must not be busy after clearing the associated on bit and prior to setting the usbmd bit.
? 2015-2016 microchip technology inc. ds60001320d-page 577 pic32mz embedded connectivity with floating point unit (ef) family uart3 u3md pmd5<2> uart4 u4md pmd5<3> uart5 u5md pmd5<4> uart6 u6md pmd5<5> spi1 spi1md pmd5<8> spi2 spi2md pmd5<9> spi3 spi3md pmd5<10> spi4 spi4md pmd5<11> spi5 spi5md pmd5<12> spi6 spi6md pmd5<13> i2c1 i2c1md pmd5<16> i2c2 i2c2md pmd5<17> i2c3 i2c3md pmd5<18> i2c4 i2c4md pmd5<19> i2c5 i2c5md pmd5<20> usb (2) usbmd pmd5<24> can1 can1md pmd5<28> can2 can2md pmd5<29> rtcc rtccmd pmd6<0> reference clock output 1 refo1md pmd6<8> reference clock output 2 refo2md pmd6<9> reference clock output 3 refo3md pmd6<10> reference clock output 4 refo4md pmd6<11> pmp pmpmd pmd6<16> ebi ebimd pmd6<17> sqi1 sqi1md pmd6<23> ethernet ethmd pmd6<28> dma dmamd pmd7<4> random number generator rngmd pmd7<20> crypto cryptmd pmd7<22> table 33-1: peripheral module disable bits and locations (1) (continued) peripheral pmdx bit name register name and bit location note 1: not all modules and associated pmdx bits are available on all devices. see table 1: pic32mz ef family features for the lists of available peripherals. 2: module must not be busy after clearing the associated on bit and prior to setting the usbmd bit.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 578 ? 2015-2016 microchip technology inc. 33.3.1 controlling configuration changes because peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. pic32mz ef devices include two features to prevent alterations to enabled or disabled peripherals: control register lock sequence configuration bit select lock 33.3.1.1 control register lock under normal operation, writes to the pmdx registers are not allowed. attempted writes appear to execute normally, but the contents of the registers remain unchanged. to change these registers, they must be unlocked in hardware. the register lock is controlled by the pmdlock configuration bit (cfgcon<12>). set - ting pmdlock prevents writes to the control registers; ? clearing pmdlock allows writes. to set or clear pmdlock, an unlock sequence must be executed. refer to section 42. oscillators with enhanced pll (ds60001250) in the ?pic32 family reference manual? for details. 33.3.1.2 configuration bit select lock as an additional level of safety, the device can be configured to prevent more than one write session to the pmdx registers. the pmdl1way configuration bit (devcfg3<28>) blocks the pmdlock bit from being cleared after it has been set once. if pmdlock remains set, the register unlock procedure does not execute, and the pps control registers cannot be writ - ten to. the only way to clear the bit and re-enable pmd functionality is to perform a device reset.
? 2015-2016 microchip technology inc. ds60001320d-page 579 pic32mz embedded connectivity with floating point unit (ef) family table 33-2: peripheral module disable register summary virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0040 pmd1 31:16 0000 15:0 c v r m d adcmd 0000 0050 pmd2 31:16 0000 15:0 cmp2md cmp1md 0000 0060 pmd3 31:16 oc9md oc8md oc7md oc6md oc5md oc4md oc3md oc2md oc1md 0000 15:0 ic9md ic8md ic7md ic6md ic5md ic4md ic3md ic2md ic1md 0000 0070 pmd4 31:16 0000 15:0 t9md t8md t7md t6md t5md t4md t3md t2md t1md 0000 0080 pmd5 31:16 can2md can1md usbmd i2c5md i2c4md i2c3md i2c2md i2c1md 0000 15:0 spi6md spi5md spi4md spi3md spi2md spi1md u6md u5md u4md u3md u2md u1md 0000 0090 pmd6 31:16 e t h m d s q i 1 m d ebimd pmpmd 0000 15:0 refo4md refo3md refo2md refo1md rtccmd 0000 00a0 pmd7 31:16 cryptmd rngmd 0000 15:0 dmamd 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: all registers have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0 x8 and 0xc, respe ctively. see section 12.3 clr, set, and inv registers for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 580 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 581 pic32mz embedded connectivity with floating point unit (ef) family 34.0 special features pic32mz ef devices include several features intended to maximize application flexibility and reliability and minimize cost through elimination of external components. these are: flexible device configuration joint test action group (jtag) interface in-circuit serial programming? (icsp?) internal temperature sensor 34.1 configuration bits pic32mz ef devices contain two boot flash memo - ries (boot flash 1 and boot flash 2), each with an associated configuration space. these configuration spaces can be programmed to contain various device configurations. configuration space that is aliased by the lower boot alias memory region is used to provide values for the following configura - tion registers. see 4.1.1 boot flash sequence and configuration spaces for more information. devsign0/adevsign0: device signature word 0 register devcp0/adevcp0: device code-protect 0 register devcfg0/adevcfg0: device configuration word 0 devcfg1/adevcfg1: device configuration word 1 devcfg2/adevcfg2: device configuration word 2 devcfg3/adevcfg3: device configuration word 3 devadcx: device adc calibration word x (x = 0-4, 7) the following run-time programmable configuration registers provide additional configuration control: cfgcon: configuration control register cfgebia: external bus interface address pin configuration register cfgebic: external bus interface control pin configuration register cfgpg: permission group configuration register in addition, the devid register provides device and revision information, the devadc0-devadc4 and devadc7 registers provide adc module calibration/ configuration data, and the devsn0 and devsn1 registers contain a unique serial number of the device. note: this data sheet summarizes the features of the pic32mz ef family of devices. however, it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 32. configuration (ds60001124) and section 33. programming and diagnostics (ds60001129) in the ?pic32 family reference manual? , which are available from the microchip web site ( www.microchip.com/pic32 ). note: do not use word program operation (nvmop<3:0> = 0001 ) when programming the device words that are described in this section.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 582 ? 2015-2016 microchip technology inc. 34.2 registers table 34-1: devcfg: device configuration word summary virtual address (bfc0_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ffc0 devcfg3 31:16 fusbidio iol1way pmdl1way pgl1way fethio fmiien xxxx 15:0 userid<15:0> xxxx ffc4 devcfg2 31:16 upllfsel fpllodiv<2:0> xxxx 15:0 fpllmult<6:0> fplliclk fpllrng<2:0> fpllidiv<2:0> xxxx ffc8 devcfg1 31:16 fdmten dmtcnt<4:0> fwdtwinsz<1:0> fwdten windis wdtspgm wdtps<4:0> xxxx 15:0 fcksm<1:0> osciofnc poscmod<1:0> ieso fsoscen dmtintv<2:0> fnosc<2:0> xxxx ffcc devcfg0 31:16 ejtagben poscboost poscgain<1:0> soscboost soscgain<1:0> xxxx 15:0 smclr dbgper<2:0> fsleep fecccon<1:0> bootisa trcen icesel<1:0> jtagen debug<1:0> xxxx ffd0 devcp3 31:16 xxxx 15:0 xxxx ffd4 devcp2 31:16 xxxx 15:0 xxxx ffd8 devcp1 31:16 xxxx 15:0 xxxx ffdc devcp0 31:16 cp xxxx 15:0 xxxx ffe0 devsign3 31:16 xxxx 15:0 xxxx ffe4 devsign2 31:16 xxxx 15:0 xxxx ffe8 devsign1 31:16 xxxx 15:0 xxxx ffec devsign0 31:16 0 xxxx 15:0 xxxx legend: x = unknown value on reset; = reserved, read as 1 . reset values are shown in hexadecimal.
? 2015-2016 microchip technology inc. ds60001320d-page 583 pic32mz embedded connectivity with floating point unit (ef) family table 34-2: adevcfg: alternate de vice configuration word summary virtual address (bfc0_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ff40 adevcfg3 31:16 fusbidio iol1way pmdl1way pgl1way fethio fmiien xxxx 15:0 userid<15:0> xxxx ff44 adevcfg2 31:16 upllfsel fpllodiv<2:0> xxxx 15:0 fpllmult<6:0> fplliclk fpllrng<2:0> fpllidiv<2:0> xxxx ff48 adevcfg1 31:16 fdmten dmtcnt<4:0> fwdtwinsz<1:0> fwdten windis wdtspgm wdtps<4:0> xxxx 15:0 fcksm<1:0> osciofnc poscmod<1:0> ieso fsoscen dmtintv<2:0> fnosc<2:0> xxxx ff4c adevcfg0 31:16 ejtagben poscboost poscgain<1:0> soscboost soscgain<1:0> xxxx 15:0 smclr dbgper<2:0> fsleep fecccon<1:0> bootisa trcen icesel<1:0> jtagen debug<1:0> xxxx ff50 adevcp3 31:16 xxxx 15:0 xxxx ff54 adevcp2 31:16 xxxx 15:0 xxxx ff58 adevcp1 31:16 xxxx 15:0 xxxx ff5c adevcp0 31:16 c p xxxx 15:0 xxxx ff60 adevsign3 31:16 xxxx 15:0 xxxx ff64 adevsign2 31:16 xxxx 15:0 xxxx ff68 adevsign1 31:16 xxxx 15:0 xxxx ff6c adevsign0 31:16 0 xxxx 15:0 xxxx legend: x = unknown value on reset; = reserved, read as 1 . reset values are shown in hexadecimal.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 584 ? 2015-2016 microchip technology inc. table 34-3: device id, revision, and configuration summary virtual address (bf80_#) register name bit range bits all resets (1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0000 cfgcon 31:16 dmapri cpupri icaclk ocaclk 0000 15:0 iolock pmdlock pglock usbssen ioancpen ecccon<1:0> jtagen troen t d o e n 000b 0020 devid 31:16 ver<3:0> devid<27:16> xxxx 15:0 devid<15:0> xxxx 0030 syskey 31:16 syskey<31:0> 0000 15:0 0000 00c0 cfgebia (2) 31:16 ebipinen ebia23en ebia22en ebia21en ebia20en ebia19en ebia18en ebia17en ebia16en 0000 15:0 ebia15en ebia14en ebia13en ebia12en ebia11en ebia10en ebia9en ebia8en ebia7en ebia6en ebia5en ebia4en ebia3en ebia2en ebia1en ebia0en 0000 00d0 cfgebic (2) 31:16 ebi rdyinv3 ebi rdyinv2 ebi rdyinv1 ebi rdyen3 ebi rdyen2 ebi rdyen1 ebi rdylvl ebirpen 0000 15:0 ebiween ebioeen ebibsen1 ebibsen0 ebicsen3 ebicsen2 ebicsen1 ebicsen0 ebiden1 ebiden0 0000 00e0 cfgpg 31:16 icd1pg<1:0> cryptpg<1:0> fcpg<1:0> sqi1pg<1:0> ethpg<1:0> 0000 15:0 can2pg<1:0> can1pg<1:0> usbpg<1:0> dmapg<1:0> cpupg<1:0> 0000 legend: x = unknown value on reset; = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: reset values are dependent on the device variant. 2: this register is not available on 64-pin devices. table 34-4: device serial number summary virtual address (bfc5_#) register name bit range bits all resets (1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 4020 devsn0 31:16 device serial number <31:16> xxxx 15:0 device serial number <15:0> xxxx 4024 devsn1 31:16 device serial number <31:16> xxxx 15:0 device serial number <15:0> xxxx legend: x = unknown value on reset. note 1: reset values are dependent on the device variant.
? 2015-2016 microchip technology inc. ds60001320d-page 585 pic32mz embedded connectivity with floating point unit (ef) family table 34-5: device adc calibration summary virtual address (bfc5_#) register name bit range bits all resets (1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 4000 devadc0 31:16 adc calibration data <31:16> xxxx 15:0 adc calibration data <15:0> xxxx 4004 devadc1 31:16 adc calibration data <31:16> xxxx 15:0 adc calibration data <15:0> xxxx 4008 devadc2 31:16 adc calibration data <31:16> xxxx 15:0 adc calibration data <15:0> xxxx 400c devadc3 31:16 adc calibration data <31:16> xxxx 15:0 adc calibration data <15:0> xxxx 4010 devadc4 31:16 adc calibration data <31:16> xxxx 15:0 adc calibration data <15:0> xxxx 401c devadc7 31:16 adc calibration data <31:16> xxxx 15:0 adc calibration data <15:0> xxxx legend: x = unknown value on reset. note 1: reset values are dependent on the device variant.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 586 ? 2015-2016 microchip technology inc. register 34-1: devsign0/adevsign0: de vice signature word 0 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 23:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:8 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 7:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 reserved: write as 0 bit 30-0 reserved: write as 1 note: the devsign1 through devsign3 and adevsign1 through adevsign3 registers are used for quad word programming operation when programming the devsign0/adesign0 registers, and do not contain any valid information. register 34-2: devcp0/adevcp0: de vice code-protect 0 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 r-1 r-1 r/p r-1 r-1 r-1 r-1 cp 23:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:8 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 7:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-29 reserved: write as 1 bit 28 cp: code-protect bit prevents boot and program flash memory from being read or modified by an external programming device. 1 = protection is disabled 0 = protection is enabled bit 27-0 reserved: write as 1 note: the devcp1 through devcp3 and adevcp1 through adevcp3 registers are used for quad word programming operation when programming the devcp0/adevcp0 registers, and do not contain any valid information.
? 2015-2016 microchip technology inc. ds60001320d-page 587 pic32mz embedded connectivity with floating point unit (ef) family register 34-3: devcfg0/adevcfg0 : device configuration word 0 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-x r/p r-1 r-1 r-1 r-1 r-1 r-1 ejtagben 23:16 r-1 r-1 r/p r/p r/p r/p r/p r/p poscboost poscgain<1:0> soscboost soscgain<1:0> 15:8 r/p r/p r/p r/p r-y r/p r/p r/p smclr dbgper<2:0> fsleep fecccon<1:0> 7:0 r-1 r/p r/p r/p r/p r/p r/p r/p bootisa trcen icesel<1:0> jtagen (1) debug<1:0> legend: r = reserved bit y = value set from configuration bits on por r = readable bit p = programmable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 reserved: the reset value of this bit is the same as devsign0<31>. bit 30 ejtagben: ejtag boot enable bit 1 = normal ejtag functionality 0 = reduced ejtag functionality bit 29-22 reserved: write as 1 bit 21 poscboost: primary oscillator boost kick start enable bit 1 = boost the kick start of the oscillator 0 = normal start of the oscillator bit 20-19 poscgain<1:0>: primary oscillator gain control bits 11 = gain level 3 (highest) 10 = gain level 2 01 = gain level 1 00 = gain level 0 (lowest) bit 18 soscboost: secondary oscillator boost kick start enable bit 1 = boost the kick start of the oscillator 0 = normal start of the oscillator bit 17-16 soscgain<1:0>: secondary oscillator gain control bits 11 = gain level 3 (highest) 10 = gain level 2 01 = gain level 1 00 = gain level 0 (lowest) bit 15 smclr: soft master clear enable bit 1 = mclr pin generates a normal system reset 0 = mclr pin generates a por reset bit 14-12 dbgper<2:0>: debug mode cpu access permission bits 1xx = allow cpu access to permission group 2 permission regions x1x = allow cpu access to permission group 1 permission regions xx1 = allow cpu access to permission group 0 permission regions 0xx = deny cpu access to permission group 2 permission regions x0x = deny cpu access to permission group 1 permission regions xx0 = deny cpu access to permission group 0 permission regions when the cpu is in debug mode and the cpu1pg<1:0> bits (cfgpg<1:0>) are set to a denied permissi on group as defined by dbgper<2:0>, the transaction request is assigned group 3 permissions. bit 11 reserved: this bit is controlled by debugger/emulator development tools and should not be modified by the user. note 1: this bit sets the value of the jtagen bit in the cfgcon register.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 588 ? 2015-2016 microchip technology inc. bit 10 fsleep: flash sleep mode bit 1 = flash is powered down when the device is in sleep mode 0 = flash remains powered when the device is in sleep mode bit 9-8 fecccon<1:0>: dynamic flash ecc configuration bits upon a device reset, the value of these bits is copied to the ecccon<1:0> bi ts (cfgcon<5:4>). 11 = ecc and dynamic ecc are disabled (ecccon<1:0> bits are writable) 10 = ecc and dynamic ecc are disabled (ecccon<1:0> bits are locked) 01 = dynamic flash ecc is enabled (ecccon<1:0> bits are locked) 00 = flash ecc is enabled (ecccon<1:0> bits are locked; disables word flash writes ) bit 7 reserved: write as 1 bit 6 bootisa: boot isa selection bit 1 = boot code and exception code is mips32 ? ? (isaonexc bit is set to 0 and the isa<1:0> bits are set to 10 in the cp0 config3 register) 0 = boot code and exception code is micromips? ? (isaonexc bit is set to 1 and the isa<1:0> bits are set to 11 in the cp0 config3 register) bit 5 trcen: trace enable bit 1 = trace features in the cpu are enabled 0 = trace features in the cpu are disabled bit 4-3 icesel<1:0>: in-circuit emulator/debugger communication channel select bits 11 = pgec1/pged1 pair is used 10 = pgec2/pged2 pair is used 01 = reserved 00 = reserved bit 2 jtagen: jtag enable bit (1) 1 = jtag is enabled 0 = jtag is disabled bit 1-0 debug<1:0>: background debugger enable bits (forced to 11 if code-protect is enabled) 1x = debugger is disabled 0x = debugger is enabled register 34-3: devcfg0/adevcfg0: devi ce configuration word 0 (continued) note 1: this bit sets the value of the jtagen bit in the cfgcon register.
? 2015-2016 microchip technology inc. ds60001320d-page 589 pic32mz embedded connectivity with floating point unit (ef) family register 34-4: devcfg1/adevcfg1 : device configuration word 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/p r/p r/p r/p r/p r/p r/p r/p fdmten dmtcnt<4:0> fwdtwinsz<1:0> 23:16 r/p r/p r/p r/p r/p r/p r/p r/p fwdten windis wdtspgm wdtps<4:0> 15:8 r/p r/p r-1 r-1 r-1 r/p r/p r/p fcksm<1:0> osciofnc poscmod<1:0> 7:0 r/p r/p r/p r/p r/p r/p r/p r/p ieso fsoscen dmtintv<2:0> fnosc<2:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 fdmten: deadman timer enable bit 1 = deadman timer is enabled and cannot be disabled by software 0 = deadman timer is disabled and can be enabled by software bit 30-26 dmtcnt<4:0>: deadman timer count select bits 11111 = reserved 11000 = reserved 10111 = 2 31 (2147483648) 10110 = 2 30 (1073741824) 10101 = 2 29 (536870912) 10100 = 2 28 (268435456) 00001 = 2 9 (512) 00000 = 2 8 (256) bit 25-24 fwdtwinsz<1:0>: watchdog timer window size bits 11 = window size is 25% 10 = window size is 37.5% 01 = window size is 50% 00 = window size is 75% bit 23 fwdten: watchdog timer enable bit 1 = watchdog timer is enabled and cannot be disabled by software 0 = watchdog timer is not enabled; it can be enabled in software bit 22 windis: watchdog timer window enable bit 1 = watchdog timer is in non-window mode 0 = watchdog timer is in window mode bit 21 wdtspgm: watchdog timer stop during flash programming bit 1 = watchdog timer stops during flash programming 0 = watchdog timer runs during flash programming (for read/execute while programming flash applications)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 590 ? 2015-2016 microchip technology inc. bit 20-16 wdtps<4:0>: watchdog timer postscale select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 all other combinations not shown result in operation = 10100 bit 15-14 fcksm<1:0>: clock switching and monitoring selection configuration bits 11 = clock switching is enabled and clock monitoring is enabled 10 = clock switching is disabled and clock monitoring is enabled 01 = clock switching is enabled and clock monitoring is disabled 00 = clock switching is disabled and clock monitoring is disabled bit 13-11 reserved: write as 1 bit 10 osciofnc: clko enable configuration bit 1 = clko output disabled 0 = clko output signal active on the osc2 pin; primary oscillator must be disabled or configured for the external clock mode (ec) for the clko to be active (poscmod<1:0> = 11 or 00 ) bit 9-8 poscmod<1:0>: primary oscillator configuration bits 11 = p osc disabled 10 = hs oscillator mode selected 01 = reserved 00 = ec mode selected bit 7 ieso: internal external switchover bit 1 = internal external switchover mode is enabled (two-speed start-up is enabled) 0 = internal external switchover mode is disabled (two-speed start-up is disabled) bit 6 fsoscen: secondary oscillator enable bit 1 = enable s osc 0 = disable s osc bit 5-3 dmtintv<2:0>: deadman timer count window interval bits 111 = window/interval value is 127/128 counter value 110 = window/interval value is 63/64 counter value 101 = window/interval value is 31/32 counter value 100 = window/interval value is 15/16 counter value 011 = window/interval value is 7/8 counter value 010 = window/interval value is 3/4 counter value 001 = window/interval value is 1/2 counter value 000 = window/interval value is zero register 34-4: devcfg1/adevcfg1: devi ce configuration word 1 (continued)
? 2015-2016 microchip technology inc. ds60001320d-page 591 pic32mz embedded connectivity with floating point unit (ef) family bit 2-0 fnosc<2:0>: oscillator selection bits 111 = frc divided by frcdiv<2:0> bits (frcdiv) 110 = reserved 101 = lprc 100 = s osc 011 = reserved 010 = p osc (hs, ec) 001 = spll 000 = frc divided by frcdiv<2:0> bits (frcdiv) register 34-4: devcfg1/adevcfg1: devi ce configuration word 1 (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 592 ? 2015-2016 microchip technology inc. register 34-5: devcfg2/adevcfg2 : device configuration word 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 r/p r-1 r-1 r-1 r-1 r-1 r-1 upllfsel 23:16 r-1 r-1 r-1 r-1 r-1 r/p r/p r/p fpllodiv<2:0> 15:8 r-1 r/p r/p r/p r/p r/p r/p r/p fpllmult<6:0> 7:0 r/p r/p r/p r/p r-1 r/p r/p r/p fplliclk fpllrng<2:0> fpllidiv<2:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 reserved: write as 1 bit 30 upllfsel: usb pll input frequency select bit 1 = upll input clock is 24 mhz 0 = upll input clock is 12 mhz bit 29-19 reserved: write as 1 bit 18-16 fpllodiv<2:0>: default system pll output divisor bits 111 = pll output divided by 32 110 = pll output divided by 32 101 = pll output divided by 32 100 = pll output divided by 16 011 = pll output divided by 8 010 = pll output divided by 4 001 = pll output divided by 2 000 = pll output divided by 2 bit 15 reserved: write as 1 bit 14-8 fpllmult<6:0>: system pll feedback divider bits 1111111 = multiply by 128 1111110 = multiply by 127 1111101 = multiply by 126 1111100 = multiply by 125 0000000 = multiply by 1 bit 7 fplliclk: system pll input clock select bit 1 = frc is selected as input to the system pll 0 =p osc is selected as input to the system pll bit 6-4 fpllrng<2:0>: system pll divided input clock frequency range bits 111 = reserved 110 = reserved 101 = 34-64 mhz 100 = 21-42 mhz 011 = 13-26 mhz 010 = 8-16 mhz 001 = 5-10 mhz 000 = bypass
? 2015-2016 microchip technology inc. ds60001320d-page 593 pic32mz embedded connectivity with floating point unit (ef) family bit 3 reserved: write as 1 bit 2-0 fpllidiv<2:0>: pll input divider bits 111 = divide by 8 110 = divide by 7 101 = divide by 6 100 = divide by 5 011 = divide by 4 010 = divide by 3 001 = divide by 2 000 = divide by 1 register 34-5: devcfg2/adevcfg2: devi ce configuration word 2 (continued)
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 594 ? 2015-2016 microchip technology inc. register 34-6: devcfg3/adevcfg3 : device configuration word 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 r/p r/p r/p r/p r-1 r/p r/p fusbidio iol1way pmdl1way pgl1way fethio fmiien 23:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:8 r/p r/p r/p r/p r/p r/p r/p r/p userid<15:8> 7:0 r/p r/p r/p r/p r/p r/p r/p r/p userid<7:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 reserved: write as 1 bit 30 fusbidio: usb usbid selection bit 1 = usbid pin is controlled by the usb module 0 = usbid pin is controlled by the port function if usbmd is 1 , usbid reverts to port control. bit 29 iol1way: peripheral pin select configuration bit 1 = allow only one reconfiguration 0 = allow multiple reconfigurations bit 28 pmdl1way: peripheral module disable configuration bit 1 = allow only one reconfiguration 0 = allow multiple reconfigurations bit 27 pgl1way: permission group lock one way configuration bit 1 = allow only one reconfiguration 0 = allow multiple reconfigurations bit 26 reserved: write as 1 bit 25 fethio: ethernet i/o pin selection configuration bit 1 = default ethernet i/o pins 0 = alternate ethernet i/o pins this bit is ignored for devices that do not have an alternate ethernet pin selection. bit 24 fmiien: ethernet mii enable configuration bit 1 = mii is enabled 0 = rmii is enabled bit 23-16 reserved: write as 1 bit 15-0 userid<15:0>: this is a 16-bit value that is user-defined and is readable via icsp? and jtag
? 2015-2016 microchip technology inc. ds60001320d-page 595 pic32mz embedded connectivity with floating point unit (ef) family register 34-7: cfgcon: conf iguration control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 dmapri (1) cpupri (1) 23:16 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 icaclk (1) ocaclk (1) 15:8 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 iolock (1) pmdlock (1) pglock (1) usbssen (1) 7:0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 r/w-0 u-0 r/w-1 ioancpen ecccon<1:0> jtagen troen t d o e n legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-26 unimplemented: read as 0 bit 25 dmapri: dma read and dma write arbitration priority to sram bit (1) 1 = dma gets high priority access to sram 0 = dma uses least recently serviced arbitration (same as other initiators) bit 24 cpupri: cpu arbitration priority to sram when servicing an interrupt bit (1) 1 = cpu gets high priority access to sram 0 = cpu uses least recently serviced arbitration (same as other initiators) bit 23-18 unimplemented: read as 0 bit 17 icaclk: input capture alternate clock selection bit (1) 1 = input capture modules use an alternative timer pair as their timebase clock 0 = all input capture modules use timer2/3 as their timebase clock bit 16 ocaclk: output compare alternate clock selection bit (1) 1 = output compare modules use an alternative timer pair as their timebase cloc k 0 = all output compare modules use timer2/3 as their timebase clock bit 15-14 unimplemented: read as 0 bit 13 iolock: peripheral pin select lock bit (1) 1 = peripheral pin select is locked. writes to pps registers are not allowed 0 = peripheral pin select is not locked. writes to pps registers are allowed bit 12 pmdlock: peripheral module disable bit (1) 1 = peripheral module is locked. writes to pmd registers are not allowed 0 = peripheral module is not locked. writes to pmd registers are allowed bit 11 pglock: permission group lock bit (1) 1 = permission group registers are locked. writes to pg registers are not allowed 0 = permission group registers are not locked. writes to pg registers are allowed bit 10-9 unimplemented: read as 0 bit 8 usbssen: usb suspend sleep enable bit (1) enables features for usb phy clock shutdown in sleep mode. 1 = usb phy clock is shut down when sleep mode is active 0 = usb phy clock continues to run when sleep is active note 1: to change this bit, the unlock sequence must be performed. refer to section 42. oscillators with enhanced pll (ds60001250) in the ?pic32 family reference manual? for details.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 596 ? 2015-2016 microchip technology inc. bit 7 ioancpen: i/o analog charge pump enable bit the analog io charge pump improves analog performance when the device is operating at lower volt ages. however, the charge pumps consume additional current. 1 = charge pump is enabled 0 = charge pump is disabled bit 6 unimplemented: read as 0 bit 5-4 ecccon<1:0>: flash ecc configuration bits 11 = ecc and dynamic ecc are disabled (ecccon<1:0> bits are writable) 10 = ecc and dynamic ecc are disabled (ecccon<1:0> bits are locked) 01 = dynamic flash ecc is enabled (ecccon<1:0> bits are locked) 00 = flash ecc is enabled (ecccon<1:0> bits are locked; disables word flash writes ) bit 3 jtagen: jtag port enable bit 1 = enable the jtag port 0 = disable the jtag port bit 2 troen: trace output enable bit 1 = enable trace outputs and start trace clock (trace probe must be present) 0 = disable trace outputs and stop trace clock bit 1 unimplemented: read as 0 bit 0 tdoen: tdo enable for 2-wire jtag 1 = 2-wire jtag protocol uses tdo 0 = 2-wire jtag protocol does not use tdo register 34-7: cfgcon: configuration control register (continued) note 1: to change this bit, the unlock sequence must be performed. refer to section 42. oscillators with enhanced pll (ds60001250) in the ?pic32 family reference manual? for details.
? 2015-2016 microchip technology inc. ds60001320d-page 597 pic32mz embedded connectivity with floating point unit (ef) family register 34-8: cfgebia: external bus interface address pin configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ebipinen 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ebia23en ebia22en ebia21en ebia20en ebia19en ebia18en ebia17en ebia16en 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ebia15en ebia14en ebia13en ebia12e n ebia11en ebia10en ebia9en ebia8en 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ebia7en ebia6en ebia5en ebia4en ebi a3en ebia2en ebia1en ebia0en legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 ebipinen: ebi pin enable bit 1 = ebi controls access of pins shared with pmp 0 = pins shared with ebi are available for general use bit 30-24 unimplemented: read as 0 bit 23-0 ebia23en:ebia0en: ebi address pin enable bits 1 = ebiax pin is enabled for use by ebi 0 = ebiax pin has is available for general use note: when ebimd = 1 , the bits in this register are ignored and the pins are available for general use.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 598 ? 2015-2016 microchip technology inc. register 34-9: cfgebic: external bus interface control pin configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 ebi rdyinv3 ebi rdyinv2 ebi rdyin1 ebi rdyen3 ebi rdyen2 ebi rdyen1 23:16 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ebirdylvl ebirpen 15:8 u-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ebiween ebioeen ebibsen1 ebibsen0 7:0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ebicsen3 ebicsen2 ebicsen1 ebicsen0 ebiden1 ebiden0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31 ebirdyinv3: ebirdy3 inversion control bit 1 = invert ebirdy3 pin before use 0 = do not invert ebirdy3 pin before use bit 30 ebirdyinv2: ebirdy2 inversion control bit 1 = invert ebirdy2 pin before use 0 = do not invert ebirdy2 pin before use bit 29 ebirdyinv1: ebirdy1 inversion control bit 1 = invert ebirdy1 pin before use 0 = do not invert ebirdy1 pin before use bit 28 unimplemented: read as 0 bit 27 ebirdyen3: ebirdy3 pin enable bit 1 = ebirdy3 pin is enabled for use by the ebi module 0 = ebirdy3 pin is available for general use bit 26 ebirdyen2: ebirdy2 pin enable bit 1 = ebirdy2 pin is enabled for use by the ebi module 0 = ebirdy2 pin is available for general use bit 25 ebirdyen1: ebirdy1 pin enable bit 1 = ebirdy1 pin is enabled for use by the ebi module 0 = ebirdy1 pin is available for general use bit 24-18 unimplemented: read as 0 bit 17 ebirdylvl: ebirdyx pin sensitivity control bit 1 = use level detect for ebirdyx pins 0 = use edge detect for ebirdyx pins bit 16 ebirpen: ebirp pin sensitivity control bit 1 = ebirp pin is enabled for use by the ebi module 0 = ebirp pin is available for general use bit 15-14 unimplemented: read as 0 bit 13 ebiween: ebiwe pin enable bit 1 = ebiwe pin is enabled for use by the ebi module 0 = ebiwe pin is available for general use note: when ebimd = 1 , the bits in this register are ignored and the pins are available for general use.
? 2015-2016 microchip technology inc. ds60001320d-page 599 pic32mz embedded connectivity with floating point unit (ef) family bit 12 ebioeen: ebioe pin enable bit 1 = ebioe pin is enabled for use by the ebi module 0 = ebioe pin is available for general use bit 11-10 unimplemented: read as 0 bit 9 ebibsen1: ebibs1 pin enable bit 1 = ebibs1 pin is enabled for use by the ebi module 0 = ebibs1 pin is available for general use bit 8 ebibsen1: ebibs0 pin enable bit 1 = ebibs0 pin is enabled for use by the ebi module 0 = ebibs0 pin is available for general use bit 7 ebicsen3: ebics3 pin enable bit 1 = ebics3 pin is enabled for use by the ebi module 0 = ebics3 pin is available for general use bit 6 ebicsen2: ebics2 pin enable bit 1 = ebics2 pin is enabled for use by the ebi module 0 = ebics2 pin is available for general use bit 5 ebicsen1: ebics1 pin enable bit 1 = ebics1 pin is enabled for use by the ebi module 0 = ebics1 pin is available for general use bit 4 ebicsen0: ebics0 pin enable bit 1 = ebics0 pin is enabled for use by the ebi module 0 = ebics0 pin is available for general use bit 3-2 unimplemented: read as 0 bit 1 ebiden1: ebi data upper byte pin enable bit 1 = ebid<15:8> pins are enabled for use by the ebi module 0 = ebid<15:8> pins have reverted to general use bit 0 ebiden0: ebi data lower byte pin enable bit 1 = ebid<7:0> pins are enabled for use by the ebi module 0 = ebid<7:0> pins have reverted to general use register 34-9: cfgebic: external bus interface control pin configuration register (continued) note: when ebimd = 1 , the bits in this register are ignored and the pins are available for general use.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 600 ? 2015-2016 microchip technology inc. register 34-10: cfgpg: permission group configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 cryptpg<1:0> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 fcpg<1:0> sqi1pg<1:0> e t h p g < 1 : 0 > 15:8 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 can2pg<1:0> can1pg<1:0> usbpg<1:0> 7:0 u-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 dmapg<1:0> cpupg<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared bit 31-26 unimplemented: read as 0 bit 25-24 cryptpg<1:0>: crypto engine permission group bits 11 = initiator is assigned to permission group 3 10 = initiator is assigned to permission group 2 01 = initiator is assigned to permission group 1 00 = initiator is assigned to permission group 0 bit 23-22 fcpg<1:0>: flash control permission group bits same definition as bits 25-24. bit 21-20 sqi1pg<1:0>: sqi module permission group bits same definition as bits 25-24. bit 19-18 unimplemented: read as 0 bit 17-16 ethpg<1:0>: ethernet module permission group bits same definition as bits 25-24. bit 15-14 can2pg<1:0>: can2 module permission group bits same definition as bits 25-24. bit 13-12 can1pg<1:0>: can1 module permission group bits same definition as bits 25-24. bit 11-10 unimplemented: read as 0 bit 9-8 usbpg<1:0>: usb module permission group bits same definition as bits 25-24. bit 7-6 unimplemented: read as 0 bit 5-4 dmapg<1:0>: dma module permission group bits same definition as bits 25-24. bit 3-2 unimplemented: read as 0 bit 1-0 cpupg<1:0>: cpu permission group bits same definition as bits 25-24.
? 2015-2016 microchip technology inc. ds60001320d-page 601 pic32mz embedded connectivity with floating point unit (ef) family register 34-11: devid: device and revision id register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rrrrrrrr ver<3:0> (1) devid<27:24> (1) 23:16 rrrrrrrr devid<23:16> (1) 15:8 rrrrrrrr devid<15:8> (1) 7:0 rrrrrrrr devid<7:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-28 ver<3:0>: revision identifier bits (1) bit 27-0 devid<27:0>: device id (1) note 1: refer to ? pic32 embedded connectivity with floating point unit (ef) family silicon errata and data sheet clarification ? (ds80000663) for a list of revision and device id values. register 34-12: devsnx: device serial number register x (x = 0, 1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r r r r r r r r sn<31:24> 23:16 r r r r r r r r sn<23:16> 15:8 r r r r r r r r sn<15:8> 7:0 r r r r r r r r sn<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 sn<31:0>: device unique serial number bits
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 602 ? 2015-2016 microchip technology inc. register 34-13: devadcx: device adc calibration word x (x = 0-4, 7) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rr rrrrr r adcfg<31:24> 23:16 rr rrrrr r adcfg<23:16> 15:8 rr rrrrr r adcfg<15:8> 7:0 rr rrrrr r adcfg<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 31-0 adcfg<31:0>: calibration data for the adc module bits this data must be copied to the corresponding adcxcfg register. refer to 28.0 12-bit high-speed successive approximation register (sar ) analog-to-digital converter (adc) for more information.
? 2015-2016 microchip technology inc. ds60001320d-page 603 pic32mz embedded connectivity with floating point unit (ef) family 34.3 on-chip voltage regulator the core and digital logic for all pic32mz ef devices is designed to operate at a nominal 1.8v. to simplify system designs, devices in the pic32mz ef family incorporate an on-chip regulator providing the required core logic voltage from v dd . 34.3.1 on-chip regulator and por it takes a fixed delay for the on-chip regulator to generate an output. during this time, designated as t pu , code execution is disabled. t pu is applied every time the device resumes operation after any power-down, including sleep mode. 34.3.2 on-chip regulator and bor pic32mz ef devices also have a simple brown-out capability. if the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator reset circuitry will generate a brown-out reset. this event is captured by the bor flag bit (rcon<1>). the brown-out voltage levels are specific in section 37.1 dc characteristics . 34.4 on-chip temperature sensor pic32mz ef devices include a temperature sensor that provides accurate measurement of a devices junction temperature (see section 37.2 ac characteristics and timing parameters for more information). the temperature sensor is connected to the adc module and can be measured using the shared s&h circuit (see section 28.0 12-bit high-speed successive approximation register (sar) analog- to-digital converter (adc) for more information). 34.5 programming and diagnostics pic32mz ef devices provide a complete range of pro - gramming and diagnostic features that can increase the flexibility of any application using them. these features allow system designers to include: simplified field programmability using two-wire ? in-circuit serial programming? (icsp?) interfaces debugging using icsp programming and debugging capabilities using the ejtag extension of jtag jtag boundary scan testing for device and board diagnostics pic32 devices incorporate two programming and diag - nostic modules, and a trace controller, that provide a range of functions to the application developer. figure 34-1: block diagram of programming, debugging and trace ports tdi tdo tck tms jtag controller icsp? controller core jtagen debug<1:0> icesel pgec1 pged1 pgec2 pged2 instruction trace controller debug<1:0> trclk trd0 trd2 trd3 trd1
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 604 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 605 pic32mz embedded connectivity with floating point unit (ef) family 35.0 instruction set the pic32mz ef family instruction set complies with the mips32 ? release 5 instruction set architecture. the pic32mz ef device family does not support the following features: core extend instructions coprocessor 2 instructions note: refer to ?mips32 ? architecture for programmers volume ii: the mips32 ? instruction set? at www.imgtec.com for more information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 606 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 607 pic32mz embedded connectivity with floating point unit (ef) family 36.0 development support the pic ? microcontrollers (mcu) and dspic ? digital signal controllers (dsc) are supported with a full range of software and hardware development tools: integrated development environment - mplab ? x ide software compilers/assemblers/linkers - mplab xc compiler - mpasm tm assembler -mplink tm object linker/ ? mplib tm object librarian - mplab assembler/linker/librarian for ? various device families simulators - mplab x sim software simulator emulators - mplab real ice? in-circuit emulator in-circuit debuggers/programmers - mplab icd 3 - pickit? 3 device programmers - mplab pm3 device programmer low-cost demonstration/development boards, evaluation kits and starter kits third-party development tools 36.1 mplab x integrated development environment software the mplab x ide is a single, unified graphical user interface for microchip and third-party software, and hardware development tool that runs on windows ? , linux and mac os ? x. based on the netbeans ide, mplab x ide is an entirely new ide with a host of free software components and plug-ins for high- performance application development and debugging. moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. with complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, mplab x ide is flexible and friendly enough for new users. with the ability to support multiple tools on multiple projects with simultaneous debugging, mplab x ide is also suitable for the needs of experienced users. feature-rich editor: color syntax highlighting smart code completion makes suggestions and provides hints as you type automatic code formatting based on user-defined rules live parsing user-friendly, customizable interface: fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. call graph window project-based workspaces: multiple projects multiple tools multiple configurations simultaneous debugging sessions file history and bug tracking: local file history feature built-in support for bugzilla issue tracker
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 608 ? 2015-2016 microchip technology inc. 36.2 mplab xc compilers the mplab xc compilers are complete ansi c compilers for all of microchips 8, 16, and 32-bit mcu and dsc devices. these compilers provide powerful integration capabilities, superior code optimization and ease of use. mplab xc compilers run on windows, linux or mac os x. for easy source level debugging, the compilers provide debug information that is optimized to the mplab x ide. the free mplab xc compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. mplab xc compilers include an assembler, linker and utilities. the assembler generates relocatable object files that can then be archived or linked with other relo - catable object files and archives to create an execut - able file. mplab xc compiler uses the assembler to produce its object file. notable features of the assem - bler include: support for the entire device instruction set support for fixed-point and floating-point data command-line interface rich directive set flexible macro language mplab x ide compatibility 36.3 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code, and coff files for debugging. the mpasm assembler features include: integration into mplab x ide projects user-defined macros to streamline ? assembly code conditional assembly for multipurpose ? source files directives that allow complete control over the assembly process 36.4 mplink object linker/ ? mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 36.5 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic dsc devices. mplab xc compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire device instruction set support for fixed-point and floating-point data command-line interface rich directive set flexible macro language mplab x ide compatibility
? 2015-2016 microchip technology inc. ds60001320d-page 609 pic32mz embedded connectivity with floating point unit (ef) family 36.6 mplab x sim software simulator the mplab x sim software simulator allows code development in a pc-hosted environment by simulat - ing the pic mcus and dspic dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab x sim software simulator fully supports symbolic debugging using the mplab xc compilers, and the mpasm and mplab assemblers. the soft - ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi - ronment, making it an excellent, economical software development tool. 36.7 mplab real ice in-circuit emulator system the mplab real ice in-circuit emulator system is microchips next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs all 8, 16 and 32-bit mcu, and dsc devices with the easy-to-use, powerful graphical user interface of the mplab x ide. the emulator is connected to the design engineers pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (rj-11) or with the new high-speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab x ide. mplab real ice offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 36.8 mplab icd 3 in-circuit debugger system the mplab icd 3 in-circuit debugger system is microchips most cost-effective, high-speed hardware debugger/programmer for microchip flash dsc and mcu devices. it debugs and programs pic flash microcontrollers and dspic dscs with the powerful, yet easy-to-use graphical user interface of the mplab ide. the mplab icd 3 in-circuit debugger probe is connected to the design engineers pc using a high- speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 36.9 pickit 3 in-circuit debugger/ programmer the mplab pickit 3 allows debugging and program - ming of pic and dspic flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab ide. the mplab pickit 3 is connected to the design engineers pc using a full- speed usb interface and can be connected to the tar - get via a microchip debug (rj-11) connector (compati - ble with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to implement in-circuit debugging and in-circuit serial programming? (icsp?). 36.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages, and a mod - ular, detachable socket assembly to support various package types. the icsp cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an mmc card for file storage and data applications.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 610 ? 2015-2016 microchip technology inc. 36.11 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully functional systems. most boards include prototyping areas for adding custom circuitry and provide applica - tion firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demonstration/development board series of circuits, microchip has a line of evaluation kits and demonstra - tion software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. 36.12 third-party development tools microchip also offers a great collection of tools from third-party vendors. these tools are carefully selected to offer good value and unique functionality. device programmers and gang programmers from companies, such as softlog and ccs software tools from companies, such as gimpel and trace systems protocol analyzers from companies, such as saleae and total phase demonstration boards from companies, such as mikroelektronika, digilent ? and olimex embedded ethernet solutions from companies, such as ez web lynx, wiznet and iplogika ?
? 2015-2016 microchip technology inc. ds60001320d-page 611 pic32mz embedded connectivity with floating point unit (ef) family 37.0 electrical characteristics this section provides an overview of the pic32mz ef electrical characteristics. additional information will be provided in future revisions of this document as it becomes available. absolute maximum ratings for the pic32mz ef devices are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. specifications for extended temperature devices (-40oc to +125oc) that are different from the specification s in this section are provided in 38.0 extended temperature electrical characteristics . absolute maximum ratings (see note 1) ambient temperature under bias................................................................................................. ............. .-40c to +85c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant, with respect to v ss (note 3) ......................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd ? 2.1v (note 3) ........................................ -0.3v to +5.5v voltage on any 5v tolerant pin with respect to v ss when v dd < 2.1v (note 3) ........................................ -0.3v to +3.6v voltage on d+ or d- pin with respect to v usb 3 v 3 ..................................................................... -0.3v to (v usb 3 v 3 + 0.3v) voltage on v bus with respect to v ss ....................................................................................................... -0.3v to +5.5v maximum current out of v ss pin(s) .......................................................................................................................2 00 ma maximum current into v dd pin(s) (note 2) ............................................................................................................200 ma maximum current sunk/sourced by any 4x i/o pin (note 4) ....................................................................................15 ma maximum current sunk/sourced by any 8x i/o pin (note 4) ....................................................................................25 ma maximum current sunk/sourced by any 12x i/o pin (note 4) ..................................................................................33 ma maximum current sunk by all ports .............................................................................................. .........................150 ma maximum current sourced by all ports (note 2) ....................................................................................................150 ma note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see tab l e 37-2 ). 3: see the pin name tables ( tab l e 2 through tab l e 4 ) for the 5v tolerant pins. 4: characterized, but not tested. refer to parameters do10 , do20 , and do20a for the 4x, 8x, and 12x i/o pin lists.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 612 ? 2015-2016 microchip technology inc. 37.1 dc characteristics table 37-1: operating mips vs. voltage characteristic v dd range (in volts) (note 1) temp. range (in c) max. frequency comment pic32mz ef devices dc5 2.1v-3.6v -40c to +85c 200 mhz note 1: overall functional device operation at v bormin < v dd < v ddmin is guaranteed, but not characterized. all device analog modules, such as adc, etc., will function, but with degraded performance below v ddmin . refer to parameter bo10 in ta b l e 37-5 for bor values. table 37-2: thermal operating conditions rating symbol min. typical max. unit industrial temperature devices operating junction temperature range t j -40 +125 c operating ambient temperature range t a -40 +85 c extended temperature devices operating junction temperature range t j -40 +140 c operating ambient temperature range t a -40 +125 c power dissipation: internal chip power dissipation: p int = v dd x (i dd C s i oh ) p d p int + p i / o w i/o pin power dissipation: p i / o = s (({v dd C v oh } x i oh ) + s (v ol x i ol )) maximum allowed power dissipation p dmax (t j C t a )/ ? ja w table 37-3: thermal packaging characteristics characteristics symbol typical max. unit notes package thermal resistance, 64-pin qfn (9x9x0.9 mm) ? ja 28 c/w 1 package thermal resistance, 64-pin tqfp (10x10x1 mm) ? ja 49 c/w 1 package thermal resistance, 100-pin tqfp (12x12x1 mm) ? ja 43 c/w 1 package thermal resistance, 100-pin tqfp (14x14x1 mm) ? ja 40 c/w 1 package thermal resistance, 124-pin vtla (9x9x0.9 mm) ? ja 30 c/w 1 package thermal resistance, 144-pin tqfp (16x16x1 mm) ? ja 42 c/w 1 package thermal resistance, 144-pin lqfp (20x20x1.4 mm) ? ja 39 c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ? ja ) numbers are achieved by package simulations.
? 2015-2016 microchip technology inc. ds60001320d-page 613 pic32mz embedded connectivity with floating point unit (ef) family table 37-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. typical max. units conditions operating voltage dc10 v dd supply voltage (note 1) 2.1 3.6 v dc12 v dr ram data retention voltage (note 2) 2.0 v dc16 v por v dd start voltage ? to ensure internal ? power-on reset signal (note 3) 1.75 v dc17 sv dd v dd rise rate ? to ensure internal ? power-on reset signal 0.000011 1.1 v/s 300 ms to 3 s @ 3.3v note 1: overall functional device operation at v bormin < v dd < v ddmin is guaranteed, but not characterized. all device analog modules, such as adc, etc., will function, but with degraded performance below v ddmin . refer to parameter bo10 in table 37-5 for bor values. 2: this is the limit to which v dd can be lowered without losing ram data. 3: this is the limit to which v dd must be lowered to ensure power-on reset. table 37-5: electrical characteristics: bor dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. (1) typical max. units conditions bo10 v bor bor event on v dd transition high-to-low (note 2) 1.88 2.02 v note 1: parameters are for design guidance only and are not tested in manufacturing. 2: overall functional device operation at v bormin < v dd < v ddmin is tested, but not characterized. all device analog modules, such as adc, etc., will function, but with degraded performance below v ddmin .
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 614 ? 2015-2016 microchip technology inc. table 37-6: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial parameter no. typical (3) maximum (6) units conditions operating current (i dd ) (1) dc20 8 25 ma 4 mhz (note 4,5) dc21 10 30 ma 10 mhz (note 5) dc22 32 65 ma 60 mhz (note 2,4) dc23 40 75 ma 80 mhz (note 2,4) dc25 61 95 ma 130 mhz (note 2,4) dc26 72 110 ma 160 mhz (note 2,4) dc28 81 120 ma 180 mhz (note 2,4) dc27a 92 130 ma 200 mhz (note 2) dc27b 78 100 ma 200 mhz (note 4,5) note 1: a devices i dd supply current is mainly a function of the operating voltage and frequency. other factors, such as pbclk (peripheral bus clock) frequency, number of peripheral modules enabled, internal code execution pattern, i/o pin loading and switching rate, oscillator type, as well as temperature, can hav e an impact on the current consumption. 2: the test conditions for i dd measurements are as follows: oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail-to-rail, (osc1 input clock input over/undershoot < 100 mv required) osc2/clko is configured as an i/o input pin usb pll is disabled (usbmd = 1 ), v usb 3 v 3 is connected to v ss cpu, program flash, and sram data memory are operational, program flash memory wait states are equal to two l1 cache and prefetch modules are enabled no peripheral modules are operating, (on bit = 0 ), and the associated pmd bit is set. all clocks are disabled on bit (pbxdiv<15>) = 0 (x ?? 1,7) wdt, dmt, clock switching, fail-safe clock monitor, and secondary oscillator are disabled all i/o pins are configured as inputs and pulled to v ss mclr = v dd cpu executing while(1) statement from flash rtcc and jtag are disabled 3: data in typical column is at 3.3v, +25c at specified operating frequency unless otherwise stated. parameters are for design guidance only and are not tested. 4: this parameter is characterized, but not tested in manufacturing. 5: note 2 applies with the following exceptions: l1 cache and prefetch modules are disabled, program flash memory wait states are equal to seven. 6: data in the maximum column is at 3.3v, +85oc at specified operating frequency, unless otherwise stated. parameters are for design guidance only and are not tested.
? 2015-2016 microchip technology inc. ds60001320d-page 615 pic32mz embedded connectivity with floating point unit (ef) family table 37-7: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial parameter no. typical (2) maximum (4) units conditions idle current (i idle ): core off, clock on base current (note 1) dc30a 7 22 ma 4 mhz (note 3) dc31a 8 24 ma 10 mhz dc32a 13 32 ma 60 mhz (note 3) dc33a 21 42 ma 130 mhz (note 3) dc34 26 48 ma 180 mhz (note 3) dc35 28 52 ma 200 mhz note 1: the test conditions for i idle current measurements are as follows: oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail-to-rail, (osc1 input clock input over/undershoot < 100 mv required) osc2/clko is configured as an i/o input pin usb pll is disabled (usbpmd = 1 ), v usb 3 v 3 is connected to v ss , pbclkx divisor = 1:128 (x ? 7) cpu is in idle mode (cpu core halted) l1 cache and prefetch modules are disabled no peripheral modules are operating, (on bit = 0 ), but the associated pmd bit is cleared (except usbpmd) wdt, dmt, clock switching, fail-safe clock monitor, and secondary oscillator are disabled all i/o pins are configured as inputs and pulled to v ss mclr = v dd rtcc and jtag are disabled 2: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: this parameter is characterized, but not tested in manufacturing. 4: data in the maximum column is at 3.3v, +85oc at specified operating frequency, unless otherwise stated . parameters are for design guidance only and are not tested.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 616 ? 2015-2016 microchip technology inc. table 37-8: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param. no. typical (2) maximum (5) units conditions power-down current (i pd ) (note 1) dc40k 0.7 7 ma -40c base power-down current dc40l 1.5 7 ma +25c dc40n 7 20 ma +85c module differential current dc41e 15 50 a 3.6v watchdog timer current: ? i wdt (note 3) dc42e 25 50 a 3.6v rtcc + timer1 w/32 khz crystal: ? i rtcc (note 3) dc43d 3 3.8 ma 3.6v adc: ? i adc (notes 3, 4) dc44 15 50 a 3.6v deadman timer current: ? i dmt (note 3) note 1: the test conditions for i pd current measurements are as follows: oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail-to-rail, (osc1 input clock input over/undershoot < 100 mv required) osc2/clko is configured as an i/o input pin usb pll is disabled (usbmd = 1 ), v usb 3 v 3 is connected to v ss cpu is in sleep mode l1 cache and prefetch modules are disabled no peripheral modules are operating, (on bit = 0 ), and the associated pmd bit is set. all clocks are disabled on bit (pbxdiv<15>) = 0 (x ?? 1,7) wdt, dmt, clock switching, fail-safe clock monitor, and secondary oscillator are disabled all i/o pins are configured as inputs and pulled to v ss mclr = v dd rtcc and jtag are disabled voltage regulator is in stand-by mode (vregs = 0 ) 2: data in the typical column is at 3.3v, +25c unless otherwise stated. parameters are for design guid- ance only and are not tested. 3: the ? current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: voltage regulator is operational (vregs = 1 ). 5: data in the maximum column is at 3.3v, +85oc at specified operating frequency, unless otherwise stated. parameters are for design guidance only and are not tested.
? 2015-2016 microchip technology inc. ds60001320d-page 617 pic32mz embedded connectivity with floating point unit (ef) family table 37-9: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. typ. (1) max. units conditions v il input low voltage di10 i/o pins with pmp v ss 0.15 * v dd v i/o pins v ss 0.2 * v dd v di18 sdax, sclx v ss 0.3 * v dd v smbus disabled ? (note 4) di19 sdax, sclx v ss 0.8 v smbus enabled ? (note 4) v ih input high voltage di20 i/o pins not 5v-tolerant (5) 0.80 * v dd v dd v (note 4,6) i/o pins 5v-tolerant with pmp (5) 0.80 * v dd 5 . 5v (note 4,6) i/o pins 5v-tolerant (5) 0.80 * v dd 5 . 5v di28a sdax, sclx on non-5v tolerant pins (5) 0.80 * v dd v dd v smbus disabled ? (note 4,6) di29a sdax, sclx on non-5v tolerant pins (5) 2.1 v dd v smbus enabled, ? 2.1v ? v pin ? 5.5 ? (note 4,6) di28b sdax, sclx on 5v tolerant pins (5) 0.80 * v dd 5.5 v smbus disabled ? (note 4,6) di29b sdax, sclx on 5v tolerant pins (5) 2.1 5.5 v smbus enabled, ? 2.1v ? v pin ? 5.5 ? (note 4,6) di30 i cnpu change notification ? pull-up current - 4 0 a v dd = 3.3v, v pin = v ss (note 3,6) di31 i cnpd change notification ? pull-down current (4) 40 a v dd = 3.3v, v pin = v dd i il input leakage current (note 3) di50 i/o ports + 1 a v ss ? v pin ? v dd , ? pin at high-impedance di51 analog input pins + 1 a v ss ? v pin ? v dd , ? pin at high-impedance di55 mclr (2) + 1 a v ss ?? v pin ?? v dd di56 osc1 + 1 a v ss ?? v pin ?? v dd , ? hs mode note 1: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: this parameter is characterized, but not tested in manufacturing. 5: see the pin name tables ( tab l e 2 through tab l e 4 ) for the 5v-tolerant pins. 6: the v ih specifications are only in relation to externally applied inputs, and not with respect to the user- selectable internal pull-ups. external open drain input signals utilizing the internal pull-ups of the pic32 device are guaranteed to be recognized only as a logic high internally to the pic32 device, provided that the external load does not exceed the minimum value of i cnpu . for external input logic inputs that require a pull-up source, to guarantee the minimum v ih of those components, it is recommended to use an external pull-up resistor rather than the internal pull-ups of the pic32 device.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 618 ? 2015-2016 microchip technology inc. table 37-10: dc characteristics: i/o pin in put injection current specifications dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. typical (1) max. units conditions di60a i icl input low injection current 0 - 5 (2,5) ma this parameter applies to all pins, with the exception of rb10. maximum i ich current for this exception is 0 ma. di60b i ich input high injection current 0 + 5 (3,4,5) ma this parameter applies to all pins, with the exception of all 5v toler- ant pins, osci, osco, sosci, sosco, d+, d- and rb10. maximum i ich current for these exceptions is 0 ma. di60c ? i ict total input injection current (sum of all i/o and control pins) -20 (6) + 2 0 (6) ma absolute instantaneous sum of all input injection currents from all i/o pins ( | i icl + | i ich | ) ? ? i ict note 1: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: v il source < (v ss - 0.3). characterized but not tested. 3: v ih source > (v dd + 0.3) for non-5v tolerant pins only. 4: digital 5v tolerant pins do not have an internal high side diode to v dd , and therefore, cannot tolerate any positive input injection current. 5: injection currents > | 0 | can affect the adc results by approximately 4 to 6 counts (i.e., v ih source > (v dd + 0.3) or v il source < (v ss - 0.3)). 6: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the absolute instantaneous sum of the input injection currents from all pins do not exceed the spec- ified limit. if note 2 , i icl = (((vss - 0.3) - v il source) / rs). if note 3 , i ich = ((i ich source - (v dd + 0.3)) / rs). rs = resistance between input source voltage and device pin. if (v ss - 0.3) ? v source ? (v dd + 0.3), injection current = 0 .
? 2015-2016 microchip technology inc. ds60001320d-page 619 pic32mz embedded connectivity with floating point unit (ef) family table 37-11: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. sym. characteristic min. typ. max. units conditions (1) do10 v ol output low voltage i/o pins 4x sink driver pins - ra3, ra9, ra10, ra14, ra15 rb0-rb2, rb4, rb6, rb7, rb11, rb13 rc12-rc15 rd0, rd6-rd7, rd11, rd14 re8, re9 rf2, rf3, rf8 rg15 rh0, rh1, rh4-rh6, rh8-rh13 rj0-rj2, rj8, rj9, rj11 0 . 4v i ol ? 10 ma, v dd = 3.3v output low voltage i/o pins: 8x sink driver pins - ra0-ra2, ra4, ra5 rb3, rb5, rb8-rb10, rb12, rb14, rb15 rc1-rc4 rd1-rd5, rd9, rd10, rd12, rd13, rd15 re4-re7 rf0, rf4, rf5, rf12, rf13 rg0, rg1, rg6-rg9 rh2, rh3, rh7, rh14, rh15 rj3-rj7, rj10, rj12-rj15 rk0-rk7 0 . 4 vi ol ? 15 ma, v dd = 3.3v output low voltage i/o pins: 12x sink driver pins - ra6, ra7re0-re3 rf1 rg12-rg14 0 . 4 vi ol ? 20 ma, v dd = 3.3v note 1: parameters are characterized, but not tested.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 620 ? 2015-2016 microchip technology inc. do20 v oh output high voltage i/o pins: 4x source driver pins - ra3, ra9, ra10, ra14, ra15 rb0-rb2, rb4, rb6-rb7, rb11, rb13 rc12-rc15 rd0, rd6-rd7, rd11, rd14 re8, re9 rf2, rf3, rf8 rg15 rh0, rh1, rh4-rh6, rh8-rh13 rj0-rj2, rj8, rj9, rj11 2.4 v i oh ? -10 ma, v dd = 3.3v output high voltage i/o pins: 8x source driver pins - ra0-ra2, ra4, ra5 rb3, rb5, rb8-rb10, rb12, rb14, rb15 rc1-rc4 rd1-rd5, rd9, rd10, rd12, rd13, rd15 re4-re7 rf0, rf4, rf5, rf12, rf13 rg0, rg1, rg6-rg9 rh2, rh3, rh7, rh14, rh15 rj3-rj7, rj10, rj12-rj15 rk0-rk7 2.4 v i oh ? -15 ma, v dd = 3.3v output high voltage i/o pins: 12x source driver pins - ra6, ra7re0-re3 rf1 rg12-rg14 2.4 v i oh ? -20 ma, v dd = 3.3v table 37-11: dc characteristics: i/o pin output specifications (continued) dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. sym. characteristic min. typ. max. units conditions (1) note 1: parameters are characterized, but not tested.
? 2015-2016 microchip technology inc. ds60001320d-page 621 pic32mz embedded connectivity with floating point unit (ef) family do20a v oh 1 output high voltage i/o pins: 4x source driver pins - ra3, ra9, ra10, ra14, ra15 rb0-rb2, rb4, rb6-rb7, rb11, rb13 rc12-rc15 rd0, rd6-rd7, rd11, rd14 re8, re9 rf2, rf3, rf8 rg15 rh0, rh1, rh4-rh6, rh8-rh13 rj0-rj2, rj8, rj9, rj11 1.5 v i oh ? -14 ma, v dd = 3.3v 2.0 v i oh ? -12 ma, v dd = 3.3v 3.0 v i oh ? -7 ma, v dd = 3.3v output high voltage i/o pins: 8x source driver pins - ra0-ra2, ra4, ra5 rb3, rb5, rb8-rb10, rb12, rb14, rb15 rc1-rc4 rd1-rd5, rd9, rd10, rd12, rd13, rd15 re4-re7 rf0, rf4, rf5, rf12, rf13 rg0, rg1, rg6-rg9 rh2, rh3, rh7, rh14, rh15 rj3-rj7, rj10, rj12-rj15 rk0-rk7 1.5 v i oh ? -22 ma, v dd = 3.3v 2.0 v i oh ? -18 ma, v dd = 3.3v 3.0 v i oh ? -10 ma, v dd = 3.3v output high voltage i/o pins: 12x source driver pins - ra6, ra7re0-re3 rf1 rg12-rg14 1.5 v i oh ? -32 ma, v dd = 3.3v 2.0 v i oh ? -25 ma, v dd = 3.3v 3.0 v i oh ? -14 ma, v dd = 3.3v table 37-11: dc characteristics: i/o pin output specifications (continued) dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. sym. characteristic min. typ. max. units conditions (1) note 1: parameters are characterized, but not tested.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 622 ? 2015-2016 microchip technology inc. table 37-12: dc characteristics: program memory (3) dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. sym. characteristics min. typ. (1) max. units conditions d130a e p cell endurance 10,000 e/w without ecc d130b 20,000 e/w with ecc d131 v pr v dd for read v ddmin v ddmax v d132 v pew v dd for erase or write v ddmin v ddmax v d134a t retd characteristic retention 10 year without ecc d134b 20 year with ecc d135 i ddp supply current during programming 3 0 m a d136 t rw row write cycle time (notes 2, 4) 66813 frc cycles d137 t qww quad word write cycle time ? (note 4) 773 frc cycles d138 t ww word write cycle time (note 4) 383 frc cycles d139 t ce chip erase cycle time (note 4) 515373 frc cycles d140 t pfe all program flash (upper and lower regions) erase cycle time (note 4) 256909 frc cycles d141 t pbe program flash (upper or lower regions) erase cycle time (note 4) 128453 frc cycles d142 t pge page erase cycle time (note 4) 128453 frc cycles note 1: data in typical column is at 3.3v, +25c unless otherwise stated. 2: the minimum pbclk5 for row programming is 4 mhz. 3: refer to the ?pic32 flash programming specification? (ds60001145) for operating conditions during programming and erase cycles. 4: this parameter depends on frc accuracy (see table 37-20 ) and frc tuning values (see the osctun register: register 8-2 ). table 37-13: dc characteristics: program flash memory wait states dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended required flash wait states (1) sysclk units conditions with ecc: 0 wait states 1 wait state 2 wait states 0 < sysclk ? 60 60 < sysclk ? 120 120 < sysclk ? 200 mhz without ecc: 0 wait states 1 wait state 2 wait states 0 < sysclk ? 74 74 < sysclk ? 140 140 < sysclk ? 200 mhz note 1: to use wait states, the prefetch module must be enabled (prefen<1:0> ? 00 ) and the pfmws<2:0> bits must be written with the desired wait state value.
? 2015-2016 microchip technology inc. ds60001320d-page 623 pic32mz embedded connectivity with floating point unit (ef) family table 37-14: comparator specifications dc characteristics standard operating conditions (see note 3): 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. typical max. units comments d300 v ioff input offset voltage 10 mv av dd = v dd , av ss = v ss d301 v icm input common mode voltage 0 v dd va v dd = v dd , av ss = v ss ? (note 2) d302 cmrr common mode rejection ratio 55 db max v icm = (v dd C 1)v ? (note 2, 4) d303 t resp response time 150 ns av dd = v dd , av ss = v ss (notes 1, 2) d304 on2 ov comparator enabled to out- put valid 10 s comparator module is configured before setting the comparator on bit (note 2) d305 iv ref internal voltage reference 1.194 1.2 1.206 v note 1: response time measured with one comparator input at (v dd C 1.5)/2, while the other input transitions from v ss to v dd . 2: these parameters are characterized but not tested. 3: the comparator module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is guaranteed, but not characterized. 4: cmrr measurement characterized with a 1 m ? resistor in parallel with a 25 pf capacitor to v ss . table 37-15: comparator volt age reference specifications dc characteristics standard operating conditions (see note 3): 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. typ. max. units comments d312 t set internal 4-bit dac comparator reference settling time 10 s see note 1 d313 dac refh cv ref input voltage reference range av ss av dd v cv rsrc with cvrss = 0 v ref - v ref + v cv rsrc with cvrss = 1 d314 dv ref cv ref programmable output range 0 0.625 x dac refh v 0 to 0.625 dac refh with dac refh /24 step size 0.25 x dac refh 0.719 x dac refh v 0.25 x dac refh to 0.719 dac refh with dac refh /32 step size d315 dac res resolution dac refh /24 cvrcon = 1 dac refh /32 cvrcon = 0 d316 dac acc absolute accuracy (2) 1/4 lsb dac refh /24, cvrcon = 1 1/2 lsb dac refh /32, cvrcon = 0 note 1: settling time was measured while cvrr = 1 and cvr<3:0> transitions from 0000 to 1111 . this parameter is characterized, but is not tested in manufacturing. 2: these parameters are characterized but not tested.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 624 ? 2015-2016 microchip technology inc. 37.2 ac characteristics and timing parameters the information contained in this section defines pic32mz ef device ac characteristics and timing parameters. figure 37-1: load conditions fo r device timing specifications v dd /2 c l r l pin pin v ss v ss c l r l =464 ? load condition 1 C for all pins except osc2 load condition 2 C for osc2 (in ec mode) table 37-16: capacitiv e loading requirements on output pins ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. typical (1) max. units conditions do56 c l all i/o pins (except pins used as cxout) 50 pf ec mode for osc2 do58 c b sclx, sdax 400 pf in i 2 c mode do59 c sqi all sqi pins 10 pf note 1: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design gui dance only and are not tested.
? 2015-2016 microchip technology inc. ds60001320d-page 625 pic32mz embedded connectivity with floating point unit (ef) family figure 37-2: exter nal clock timing osc1 os20 os30 os30 os31 os31 table 37-17: external cl ock timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics minimum typical (1) maximum units conditions os10 f osc external clki frequency (external clocks allowed only ? in ec and ecpll modes) dc 64 mhz ec (note 2,3) os13 oscillator crystal frequency 4 32 mhz hs (note 2,3) os15 32 32.768 100 khz s osc (note 2) os20 t osc t osc = 1/f osc ? see parameter os10 for f osc value os30 t os l, t os h external clock in (osc1) ? high or low time 0.375 x t osc ns ec (note 2) os31 t os r, t os f external clock in (osc1) ? rise or fall time 7.5 ns ec (note 2) os40 t ost oscillator start-up timer period (only applies to hs, hspll, and s osc clock oscillator modes) 1024 t osc (note 2) os41 t fscm primary clock fail safe ? time-out period 2 ms (note 2) os42 g m external oscillator transconductance 400 a/v v dd = 3.3v, ? t a = +25c, hs ? (note 2) note 1: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are characterize d but are not tested. 2: this parameter is characterized, but not tested in manufacturing. 3: see parameter os50 for pll input frequency limitations.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 626 ? 2015-2016 microchip technology inc. table 37-18: system timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param. no. symbol characteristics minimum typical maximum units conditions os51 f sys system frequency dc 200 mhz usb module disabled 60 200 mhz usb module enabled os55a f pb peripheral bus frequency dc 100 mhz for pbclkx, x ? 4, 7 os55b dc 200 mhz for pbclk4, pbclk7 os56 f ref reference clock frequency 50 mhz for refclki1, 3, 4 and refclko1, 3, 4 pins table 37-19: pll clock timing specifications ac characteristics standard operating conditions: 2.1v to 3.6v ? (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typical max. units conditions os50 f in pll input frequency range 5 64 mhz ecpll, hspll, frcpll modes os52 t lock pll start-up time (lock time) 100 s os53 d clk clko stability (2) ? (period jitter or cumulative) -0.25 +0.25 % measured over 100 ms period os54 fv co pll v co frequency range 350 700 mhz os54a f pll pll output frequency range 10 200 mhz note 1: these parameters are characterized, but not tested in manufacturing. 2: this jitter specification is based on clock-cycle by clock-cycle measurements. to get the eff ective jitter for individual time-bases on communication clocks, use the following formula: for example, if pbclk2 = 100 mhz and spi bit rate = 50 mhz, the effective jitter is as follows: effectivejitter d clk pbclk 2 communicationclock --------------------------------------------------------- - -------------------------------------------------------------- = effectivejitter d clk 100 50 -------- - ------------- - d clk 1.41 ------------- - ==
? 2015-2016 microchip technology inc. ds60001320d-page 627 pic32mz embedded connectivity with floating point unit (ef) family table 37-20: internal frc accuracy ac characteristics standard operating conditions: 2.1v to 3.6v ? (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. characteristics min. typ. max. units conditions internal frc accuracy @ 8.00 mhz (1) f20 frc -5 +5 % 0c ? t a ? +85c -8 +8 % -40c ? t a ? +85c -10 +10 % -40c ? t a ? +125c note 1: frequency calibrated at +25c and 3.3v. the tun bits (osctun<5:0>) can be used to compensate for temperature drift. table 37-21: internal lprc accuracy ac characteristics standard operating conditions: 2.1v to 3.6v ? (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. characteristics min. typ. max. units conditions internal lprc @ 32.768 khz (1) f21 lprc -8 +8 % 0c ? t a ? +85c -25 +25 % -40c ? t a ? +125c note 1: change of lprc frequency as v dd changes. table 37-22: internal backup frc (bfrc) accuracy ac characteristics standard operating conditions: 2.1v to 3.6v ? (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. characteristics min. typ. max. units conditions internal bfrc accuracy @ 8 mhz f22 bfrc 30 %
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 628 ? 2015-2016 microchip technology inc. figure 37-3: i/o ti ming characteristics note: refer to figure 37-1 for load conditions. i/o pin (input) i/o pin (output) di35 di40 do31do32
? 2015-2016 microchip technology inc. ds60001320d-page 629 pic32mz embedded connectivity with floating point unit (ef) family table 37-23: i/o timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (2) min. typ. (1) max. units conditions do31 t io r port output rise time i/o pins: 4x source driver pins - ra3, ra9, ra10, ra14, ra15 rb0-rb2, rb4, rb6-rb7, rb11, rb13 rc12-rc15 rd0, rd6-rd7, rd11, rd14 re8, re9 rf2, rf3, rf8 rg15 rh0, rh1, rh4-rh6, rh8-rh13 rj0-rj2, rj8, rj9, rj11 9.5 ns c load = 50 pf 6 ns c load = 20 pf port output rise time i/o pins: 8x source driver pins - ra0-ra2, ra4, ra5 rb3, rb5, rb8-rb10, rb12, rb14, rb15 rc1-rc4 rd1-rd5, rd9, rd10, rd12, rd13, rd15 re4-re7 rf0, rf4, rf5, rf12, rf13 rg0, rg1, rg6-rg9 rh2, rh3, rh7, rh14, rh15 rj3-rj7, rj10, rj12-rj15 rk0-rk7 8 ns c load = 50 pf 6 ns c load = 20 pf port output rise time i/o pins: 12x source driver pins - ra6, ra7 re0-re3 rf1 rg12-rg14 3.5 ns c load = 50 pf 2 ns c load = 20 pf note 1: data in typical column is at 3.3v, +25c unless otherwise stated. 2: this parameter is characterized, but not tested in manufacturing.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 630 ? 2015-2016 microchip technology inc. do32 t io f port output fall time i/o pins: 4x source driver pins - ra3, ra9, ra10, ra14, ra15 rb0-rb2, rb4, rb6-rb7, rb11, rb13 rc12-rc15 rd0, rd6-rd7, rd11, rd14 re8, re9 rf2, rf3, rf8 rg15 rh0, rh1, rh4-rh6, rh8-rh13 rj0-rj2, rj8, rj9, rj11 9.5 ns c load = 50 pf 6 ns c load = 20 pf port output fall time i/o pins: 8x source driver pins - ra0-ra2, ra4, ra5 rb3, rb5, rb8-rb10, rb12, rb14, rb15 rc1-rc4 rd1-rd5, rd9, rd10, rd12, rd13, rd15 re4-re7 rf0, rf4, rf5, rf12, rf13 rg0, rg1, rg6-rg9 rh2, rh3, rh7, rh14, rh15 rj3-rj7, rj10, rj12-rj15 rk0-rk7 8 ns c load = 50 pf 6 ns c load = 20 pf port output fall time i/o pins: 12x source driver pins - ra6, ra7 re0-re3 rf1 rg12-rg14 3.5 ns c load = 50 pf 2 ns c load = 20 pf di35 t inp intx pin high or low time 5 ns di40 t rbp cnx high or low time (input) 5 ns table 37-23: i/o timing requirements (continued) ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (2) min. typ. (1) max. units conditions note 1: data in typical column is at 3.3v, +25c unless otherwise stated. 2: this parameter is characterized, but not tested in manufacturing.
? 2015-2016 microchip technology inc. ds60001320d-page 631 pic32mz embedded connectivity with floating point unit (ef) family figure 37-4: power-on reset timing characteristics v dd v por note 1: the power-up period will be extended if the power-up s equence completes before the device exits from bor (v dd < v ddmin ). 2: includes interval voltage regulator stabilization delay. sy00 power-up sequence (note 2) internal voltage regulator enabled (t pu ) sy10 cpu starts fetching code clock sources = (hs, hspll, and s osc ) v dd v por sy00 power-up sequence (note 2) internal voltage regulator enabled (t pu ) (t sysdly ) cpu starts fetching code (note 1) (note 1) clock sources = (frc, frcdiv, frcpll, ec, ecpll and lprc) (t ost ) sy02 (t sysdly ) sy02
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 632 ? 2015-2016 microchip technology inc. figure 37-5: external re set timing characteristics table 37-24: resets timing ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typical (2) max. units conditions sy00 t pu power-up period internal voltage regulator enabled 400 600 ? s sy02 t sysdly system delay period: ? time required to reload device configuration fuses plus sysclk delay before first instruction is fetched. 1 s + 8 sysclk cycles sy20 t mclr mclr pulse width (low) 2 ? s sy30 t bor bor pulse width (low) 1 ? s note 1: these parameters are characterized, but not tested in manufacturing. 2: data in typ column is at 3.3v, +25c unless otherwise stated. characterized by design but not tes ted. mclr (sy20) reset sequence (sy10) cpu starts fetching code bor (sy30) t ost t mclr t bor reset sequence cpu starts fetching code clock sources = (frc, frcdiv, frcpll, ec, ecpll and lprc) clock sources = (hs, hspll, and s osc ) (t sysdly ) sy02 (t sysdly ) sy02
? 2015-2016 microchip technology inc. ds60001320d-page 633 pic32mz embedded connectivity with floating point unit (ef) family figure 37-6: timer1-timer9 externa l clock timing characteristics note: refer to figure 37-1 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck table 37-25: timer1 external clock timing requirements (1) ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (2) min. typ. max. units conditions ta10 t tx h txck ? high time synchronous, ? with prescaler [(12.5 ns or 1 t pbclk 3 ) /n] + 20 ns ns must also meet parameter ta15 ( note 3 ) asynchronous, ? with prescaler 10 ns ta11 t tx l txck low time synchronous, ? with prescaler [(12.5 ns or 1 t pbclk 3 ) /n] + 20 ns ns must also meet parameter ta15 ( note 3 ) asynchronous, ? with prescaler 10 ns ta15 t tx p txck input period synchronous, ? with prescaler [(greater of 20 ns or 2 t pbclk 3 )/n] + 30 ns ns v dd > 2.7v ( note 3 ) [(greater of 20 ns or 2 t pbclk 3 )/n] + 50 ns ns v dd < 2.7v ( note 3 ) asynchronous, ? with prescaler 20 ns v dd > 2.7v 50 ns v dd < 2.7v os60 f t 1 sosc1/t1ck oscillator input frequency range (oscillator enabled by setting tcs bit (t1con<1>)) 32 50 khz ta20 t ckextmrl delay from external txck clock edge to timer ? increment 1 t pbclk 3 note 1: timer1 is a type a timer. 2: this parameter is characterized, but not tested in manufacturing. 3: n = prescale value (1, 8, 64, 256).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 634 ? 2015-2016 microchip technology inc. figure 37-7: input capture (c apx) timing characteristics table 37-26: timer2-timer9 exte rnal clock timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. max. units conditions tb10 t tx ht x c k high time synchronous, with prescaler [(12.5 ns or 1 t pbclk 3 ) /n] + 25 ns n sm u s t a l s o meet parameter tb15 n = prescale value ? (1, 2, 4, 8, 16, 32, 64, 256) tb11 t tx lt x c k low time synchronous, with prescaler [(12.5 ns or 1 t pbclk 3 ) /n] + 25 ns n sm u s t a l s o meet parameter tb15 tb15 t tx pt x c k input period synchronous, with prescaler [(greater of [(25 ns or 2 t pbclk 3 )/n] + 30 ns n sv dd > 2.7v [(greater of [(25 ns or 2 t pbclk 3 )/n] + 50 ns n sv dd < 2.7v tb20 t ckextmrl delay from external txck clock edge to timer increment 1 t pbclk 3 note 1: these parameters are characterized, but not tested in manufacturing. icx ic10 ic11 ic15 note: refer to figure 37-1 for load conditions. table 37-27: input capture module timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. max. units conditions ic10 t cc l icx input low time [(12.5 ns or 1 t pbclk 3 ) /n] + 25 ns ns must also meet parameter ic15. n = prescale value (1, 4, 16) ic11 t cc h icx input high time [(12.5 ns or 1 t pbclk 3 ) /n] + 25 ns ns must also meet parameter ic15. ic15 t cc p icx input period [(25 ns or 2 t pbclk 3 ) /n] + 50 ns ns note 1: these parameters are characterized, but not tested in manufacturing.
? 2015-2016 microchip technology inc. ds60001320d-page 635 pic32mz embedded connectivity with floating point unit (ef) family figure 37-8: output compare mo dule (ocx) timing characteristics table 37-28: output compare module timing requirements figure 37-9: ocx/pwm modul e timing characteristics ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typical (2) max. units conditions oc10 t cc f ocx output fall time ns see parameter do32 oc11 t cc r ocx output rise time ns see parameter do31 note 1: these parameters are characterized, but not tested in manufacturing. 2: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. ocx oc11 oc10 (output compare note: refer to figure 37-1 for load conditions. or pwm mode) ocfa/ocfb ocx oc20 oc15 note: refer to figure 37-1 for load conditions. ocx is tri-stated table 37-29: simple ocx/pwm mode timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param no. symbol characteristics (1) min typical (2) max units conditions oc15 t fd fault input to pwm i/o change 50 ns oc20 t flt fault input pulse width 50 ns note 1: these parameters are characterized, but not tested in manufacturing. 2: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design gui dance only and are not tested.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 636 ? 2015-2016 microchip technology inc. figure 37-10: spix module master mode (cke = 0 ) timing characteristics sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp11 sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30 sp31 note: refer to figure 37-1 for load conditions.
? 2015-2016 microchip technology inc. ds60001320d-page 637 pic32mz embedded connectivity with floating point unit (ef) family table 37-30: spix master mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typ. (2) max. units conditions sp10 t sc l sckx output low time ? (note 3) t sck /2 ns sp11 t sc h sckx output high time ? (note 3) t sck /2 n s sp15 t sc k spi clock speed (note 5) 2550 25 50 25 mhz mhz mhz mhz mhz spi1, spi4 through spi6 spi2 on rpb3, rpb5 spi2 on other i/o spi3 on rpb10, rpb9, rpf0 spi3 on other i/o sp20 t sc f sckx output fall time ? (note 4) n s see parameter do32 sp21 t sc r sckx output rise time ? (note 4) ns see parameter do31 sp30 t do f sdox data output fall time ? (note 4) ns see parameter do32 sp31 t do r sdox data output rise time ? (note 4) ns see parameter do31 sp35 t sc h2 do v, ? t sc l2 do v sdox data output valid after sckx edge 7 ns v dd > 2.7v 10 ns v dd < 2.7v sp40 t di v2 sc h, ? t di v2 sc l setup time of sdix data input ? to sckx edge 5 n s sp41 t sc h2 di l, ? t sc l2 di l hold time of sdix data input ? to sckx edge 5 n s note 1: these parameters are characterized, but not tested in manufacturing. 2: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 20 ns. therefore, the clock generated in master mode must not violate this specification. 4: assumes 30 pf load on all spix pins. 5: to achieve maximum data rate, v dd must be ? 3.3v, the smp bit (spixcon<9>) must be equal to 1 , and the operating temperature must be within the range of -40c to +105c.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 638 ? 2015-2016 microchip technology inc. figure 37-11: spix module master mode (cke = 1 ) timing characteristics sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi x sp36 sp30,sp31 sp35 msb bit 14 - - - - - -1 lsb in bit 14 - - - -1 lsb note: refer to figure 37-1 for load conditions. sp11 sp10 sp21 sp20 sp40 sp41 sp20 sp21 msb in
? 2015-2016 microchip technology inc. ds60001320d-page 639 pic32mz embedded connectivity with floating point unit (ef) family table 37-31: spix module master mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typ. (2) max. units conditions sp10 t sc l sckx output low time (note 3) t sck /2 ns sp11 t sc h sckx output high time (note 3) t sck /2 ns sp15 t sc k spi clock speed (note 5) 2550 25 50 25 mhzmhz mhz mhz mhz spi1, spi4 through spi6 spi2 on rpb3, rpb5 spi2 on other i/o spi3 on rpb10, rpb9, rpf0 spi3 on other i/o sp20 t sc f sckx output fall time ? (note 4) ns see parameter do32 sp21 t sc r sckx output rise time ? (note 4) ns see parameter do31 sp30 t do f sdox data output fall time ? (note 4) ns see parameter do32 sp31 t do r sdox data output rise time ? (note 4) ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after ? sckx edge 7n s v dd > 2.7v 1 0n s v dd < 2.7v sp36 t do v2 sc , t do v2 sc l sdox data output setup to ? first sckx edge 7n s sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 7n s v dd > 2.7v 10 ns v dd < 2.7v sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input ? to sckx edge 7n s v dd > 2.7v 10 ns v dd < 2.7v note 1: these parameters are characterized, but not tested in manufacturing. 2: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design gui dance only and are not tested. 3: the minimum clock period for sckx is 20 ns. therefore, the clock generated in master mode must not violate this specification. 4: assumes 30 pf load on all spix pins. 5: to achieve maximum data rate, v dd must be ? 3.3v, the smp bit (spixcon<9>) must be equal to 1 , and the operating temperature must be within the range of -40c to +105c.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 640 ? 2015-2016 microchip technology inc. figure 37-12: spix modul e slave mode (cke = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp70 note: refer to figure 37-1 for load conditions. sdi x msb in table 37-32: spix modul e slave mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typ. (2) max. units conditions sp70 t sc l sckx input low time (note 3) t sck /2 ns sp71 t sc h sckx input high time (note 3) t sck /2 ns sp72 t sc f sckx input fall time ns see parameter do32 sp73 t sc r sckx input rise time ns see parameter do31 sp30 t do f sdox data output fall time (note 4) ns see parameter do32 sp31 t do r sdox data output rise time (note 4) ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after ? sckx edge 7 ns v dd > 2.7v 10 ns v dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input ? to sckx edge 5 ns sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input ? to sckx edge 5 ns sp50 t ss l2 sc h, t ss l2 sc l ssx ? to sckx ? or sckx input 88 ns sp51 t ss h2 do z ssx ? to sdox output ? high-impedance (note 3) 2.5 12 ns sp52 t sc h2 ss h t sc l2 ss h ssx after sckx edge 10 ns note 1: these parameters are characterized, but not tested in manufacturing. 2: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design gui dance only and are not tested. 3: the minimum clock period for sckx is 20 ns. 4: assumes 30 pf load on all spix pins.
? 2015-2016 microchip technology inc. ds60001320d-page 641 pic32mz embedded connectivity with floating point unit (ef) family figure 37-13: spix modul e slave mode (cke = 1 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp40 sp41 note: refer to figure 37-1 for load conditions. sp50 sp70 sp35 table 37-33: spix modul e slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typical (2) max. units conditions sp70 t sc l sckx input low time (note 3) t sck /2 ns sp71 t sc h sckx input high time (note 3) t sck /2 ns sp72 t sc f sckx input fall time 10 ns sp73 t sc r sckx input rise time 10 ns sp30 t do f sdox data output fall time ? (note 4) ns see parameter do32 sp31 t do r sdox data output rise time ? (note 4) ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after ? sckx edge 10 ns v dd > 2.7v 15 ns v dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input ? to sckx edge 0 ns sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input ? to sckx edge 7 ns note 1: these parameters are characterized, but not tested in manufacturing. 2: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design gui dance only and are not tested. 3: the minimum clock period for sckx is 20 ns. 4: assumes 30 pf load on all spix pins.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 642 ? 2015-2016 microchip technology inc. sp50 t ss l2 sc h, t ss l2 sc l ssx ? to sckx ? or sckx ? input 88 ns sp51 t ss h2 do z ssx ? to sdo x output ? high-impedance ? (note 4) 2.5 12 ns sp52 t sc h2 ss h t sc l2 ss h ssx ? after sckx edge 10 ns sp60 t ss l2 do v sdox data output valid after ? ssx edge 12.5 ns table 37-33: spix modul e slave mode (cke = 1 ) timing requirements (continued) ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typical (2) max. units conditions note 1: these parameters are characterized, but not tested in manufacturing. 2: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design gui dance only and are not tested. 3: the minimum clock period for sckx is 20 ns. 4: assumes 30 pf load on all spix pins.
? 2015-2016 microchip technology inc. ds60001320d-page 643 pic32mz embedded connectivity with floating point unit (ef) family figure 37-14: sqi serial input timing characteristics figure 37-15: sqi serial output timing characteristics msb lsb t dih t dis t clk t sckl t sckh sqics1 sqiclk sqidx msb lsb t doh t dov t chs t clk t ceh t sckl t sckh t ces t chh t cc sqics1 sqics2 sqiclk sqidx
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 644 ? 2015-2016 microchip technology inc. table 37-34: sqi timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristic (1,3) min. typ. (2) max. units conditions sq10 f clk serial clock frequency (1/t sqi ) 66 mhz dma mode read, spi mode 0 33 mhz dma mode read, spi mode 3 100 mhz pio mode write sq11 t sckh serial clock high time 5 ns sq12 t sckl serial clock low time 5 ns sq13 t sckr serial clock rise time ns see parameter do31 sq14 t sckf serial clock fall time ns see parameter do32 sq15 t css (t ces )cs active setup time 5 ns sq16 t csh (t ceh )cs active hold time 5 ns sq17 t chs cs not active setup time 3 ns sq18 t chh cs not active hold time 3 ns sq22 t dis data in setup time 6 ns sq23 t dih data in hold time 3 ns sq24 t doh data out hold 0 ns sq25 t dov data out valid 6 ns note 1: these parameters are characterized, but not tested in manufacturing. 2: data in the typical column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: assumes 10 pf load on all sqix pins
? 2015-2016 microchip technology inc. ds60001320d-page 645 pic32mz embedded connectivity with floating point unit (ef) family figure 37-16: i2cx bus start/stop bits timing characteristics (master mode) figure 37-17: i2cx bus data timing characteristics (master mode) sclx sdax start condition stop condition note: refer to figure 37-1 for load conditions. im30 im31 im34 im33 im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 37-1 for load conditions. table 37-35: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. (1) max. units conditions im10 t lo : scl clock low time 100 khz mode t pbclk 2 * (brg + 2) s 400 khz mode t pbclk 2 * (brg + 2) s 1 mhz mode ? (note 2) t pbclk 2 * (brg + 2) s im11 t hi : scl clock high time 100 khz mode t pbclk 2 * (brg + 2) s 400 khz mode t pbclk 2 * (brg + 2) s 1 mhz mode ? (note 2) t pbclk 2 * (brg + 2) s im20 t f : scl sdax and sclx ? fall time 100 khz mode 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ? (note 2) 100 ns note 1: brg is the value of the i 2 c baud rate generator. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 3: the typical value for this parameter is 104 ns.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 646 ? 2015-2016 microchip technology inc. im21 t r : scl sdax and sclx ? rise time 100 khz mode 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ? (note 2) 300 ns im25 t su : dat data input ? setup time 100 khz mode 250 ns 400 khz mode 100 ns 1 mhz mode ? (note 2) 100 ns im26 t hd : dat data input ? hold time 100 khz mode 0 s 400 khz mode 0 0.9 s 1 mhz mode ? (note 2) 0 0.3 s im30 t su : sta start condition ? setup time 100 khz mode t pbclk 2 * (brg + 2) s only relevant for repeated start ? condition 400 khz mode t pbclk 2 * (brg + 2) s 1 mhz mode ? (note 2) t pbclk 2 * (brg + 2) s im31 t hd : sta start condition hold time 100 khz mode t pbclk 2 * (brg + 2) s after this period, the ? first clock pulse is ? generated 400 khz mode t pbclk 2 * (brg + 2) s 1 mhz mode ? (note 2) t pbclk 2 * (brg + 2) s im33 t su : sto stop condition setup time 100 khz mode t pbclk 2 * (brg + 2) s 400 khz mode t pbclk 2 * (brg + 2) s 1 mhz mode ? (note 2) t pbclk 2 * (brg + 2) s im34 t hd : sto stop condition 100 khz mode t pbclk 2 * (brg + 2) ns hold time 400 khz mode t pbclk 2 * (brg + 2) ns 1 mhz mode ? (note 2) t pbclk 2 * (brg + 2) ns im40 t aa : scl output valid from clock 100 khz mode 3500 ns 400 khz mode 1000 ns 1 mhz mode ? (note 2) 350 ns im45 t bf : sda bus free time 100 khz mode 4.7 s the amount of time the bus must be free before a new ? transmission can start 400 khz mode 1.3 s 1 mhz mode ? (note 2) 0.5 s im50 c b bus capacitive loading pf see parameter do58 im51 t pgd pulse gobbler delay 52 312 ns see note 3 table 37-35: i2cx bus data timing requirements (master mode) (continued) ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. (1) max. units conditions note 1: brg is the value of the i 2 c baud rate generator. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 3: the typical value for this parameter is 104 ns.
? 2015-2016 microchip technology inc. ds60001320d-page 647 pic32mz embedded connectivity with floating point unit (ef) family figure 37-18: i2cx bus start/stop bits timing characteristics (slave mode) figure 37-19: i2cx bus data timi ng characteristics (slave mode) is34 sclx sdax start condition stop condition is33 note: refer to figure 37-1 for load conditions. is31 is30 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 sclx sdax in sdax out note: refer to figure 37-1 for load conditions. table 37-36: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. max. units conditions is10 t lo : scl clock low time 100 khz mode 4.7 s pbclk must operate at a minimum of 800 khz 400 khz mode 1.3 s pbclk must operate at a minimum of 3.2 mhz 1 mhz mode ? (note 1) 0.5 s is11 t hi : scl clock high time 100 khz mode 4.0 s pbclk must operate at a minimum of 800 khz 400 khz mode 0.6 s pbclk must operate at a minimum of 3.2 mhz 1 mhz mode ? (note 1) 0.5 s note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 648 ? 2015-2016 microchip technology inc. is20 t f : scl sdax and sclx ? fall time 100 khz mode 300 ns c b is specified to be from ? 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ? (note 1) 100 ns is21 t r : scl sdax and sclx ? rise time 100 khz mode 1000 ns c b is specified to be from ? 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ? (note 1) 300 ns is25 t su : dat data input ? setup time 100 khz mode 250 ns 400 khz mode 100 ns 1 mhz mode ? (note 1) 100 ns is26 t hd : dat data input ? hold time 100 khz mode 0 ns 400 khz mode 0 0.9 s 1 mhz mode ? (note 1) 0 0.3 s is30 t su : sta start condition ? setup time 100 khz mode 4700 ns only relevant for repeated start condition 400 khz mode 600 ns 1 mhz mode ? (note 1) 250 ns is31 t hd : sta start condition hold time 100 khz mode 4000 ns after this period, the first clock pulse is generated 400 khz mode 600 ns 1 mhz mode ? (note 1) 250 ns is33 t su : sto stop condition setup time 100 khz mode 4000 ns 400 khz mode 600 ns 1 mhz mode ? (note 1) 600 ns is34 t hd : sto stop condition hold time 100 khz mode 4000 ns 400 khz mode 600 ns 1 mhz mode ? (note 1) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns 400 khz mode 0 1000 ns 1 mhz mode ? (note 1) 0 350 ns is45 t bf : sda bus free time 100 khz mode 4.7 s the amount of time the bus must be free before a new transmission can start 400 khz mode 1.3 s 1 mhz mode ? (note 1) 0.5 s is50 c b bus capacitive loading pf see parameter do58 table 37-36: i2cx bus data timing requirements (slave mode) (continued) ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. max. units conditions note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only).
? 2015-2016 microchip technology inc. ds60001320d-page 649 pic32mz embedded connectivity with floating point unit (ef) family figure 37-20: canx module i/o timing characteristics table 37-37: canx module i/o timing requirements citx pin (output) ca10 ca11 old value new value ca20 cirx pin (input) ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions ca10 tiof port output fall time ns see parameter do32 ca11 tior port output rise time ns see parameter do31 ca20 tc w f pulse width to trigger can wake-up filter 700 ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 650 ? 2015-2016 microchip technology inc. table 37-38: adc modul e specifications ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. typ. max. units conditions device supply ad01 av dd module v dd supply greater of v dd C 0.3 or 2.1 lesser of v dd + 0.3 or 3.6 v ad02 av ss module v ss supply v ss v ss + 0.3 v reference inputs ad05 v refh reference voltage high v refl + 1.8 av dd v (note 1) ad06 v refl reference voltage low av ss v refh C 1.8 v (note 1) ad07 v ref absolute reference voltage (v refh C v refl ) 1.8 av dd v (note 2) ad08 i ref current drain 102 a per adcx (x = 0-4, 7) analog input ad12 v inh -v inl full-scale input span v refl v refh v ad13 v inl absolute v inl input voltage av ss v refl v ad14 v inh absolute v inh input voltage av ss v refh v adc accuracy C measurements with external v ref +/v ref - ad20c nr resolution 6 ? 12 bits selectable 6, 8, 10, 12 resolution ranges ad21c inl integral nonlinearity 3 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad22c dnl differential nonlinearity 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad23c g err gain error 8 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad24c e off offset error 2 lsb v inl = av ss = 0v, ? av dd = 3.3v dynamic performance ad31b sinad signal to noise and ? distortion 67 db single-ended (notes 2,3) ad34b enob effective number of bits 10.5 bits (notes 2,3) note 1: these parameters are not characterized or tested in manufacturing. 2: these parameters are characterized, but not tested in manufacturing. 3: characterized with a 1 khz sine wave. 4: the adc module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is guaranteed, but not characterized.
? 2015-2016 microchip technology inc. ds60001320d-page 651 pic32mz embedded connectivity with floating point unit (ef) family table 37-39: analog-to-dig ital conversion timing requirements ac characteristics (2) standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. typ. (1) max. units conditions clock parameters ad50 t ad adc clock period 20 6250 ns throughput rate ad51 f tp sample rate for adc0-adc4 (class 1 inputs) 3.125 3.574.16 5 msps msps msps msps 12-bit resolution source impedance ? 200 ? 10-bit resolution source impedance ? 200 ? 8-bit resolution source impedance ? 200 ? 6-bit resolution source impedance ? 200 ? sample rate for adc7 (class 2 and class 3 inputs) 2.943.33 3.84 4.55 msps msps msps msps 12-bit resolution source impedance ? 200 ? 10-bit resolution source impedance ? 200 ? 8-bit resolution source impedance ? 200 ? 6-bit resolution source impedance ? 200 ? timing parameters ad60 t samp sample time for adc0-adc4 (class 1 inputs) 34 5 13 t ad source impedance ? 200 ? , max adc clock source impedance ? 500 ? , max adc clock source impedance ? 1 k ? , max adc clock source impedance ? 5 k ? , max adc clock sample time for adc7 (class 2 and 3 inputs) 45 6 14 t ad source impedance ? 200 ? , max adc clock source impedance ? 500 ? , max adc clock source impedance ? 1 k ? , max adc clock source impedance ? 5 k ? , max adc clock sample time for adc7 (class 2 and 3 inputs) see table 37-40 t ad cvden (adccon1<11>) = 1 ad62 t conv conversion time (after sample time is complete) 13 11 97 t ad 12-bit resolution 10-bit resolution 8-bit resolution 6-bit resolution ad65 t wake wake-up time from low- power mode 5 0 0 t ad lesser of 500 t ad or 20 s. 2 0 s note 1: these parameters are characterized, but not tested in manufacturing. 2: the adc module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is guaranteed, but not characterized.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 652 ? 2015-2016 microchip technology inc. table 37-40: adc sample times with cvd enabled ac characteristics (2) standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. typ. (1) max. units conditions ad60a t samp sample time for ? adc7 (class 2 and class 3 inputs) with the cvden bit (adccon1<11>) = 1 89 11 1214 16 17 t ad source impedance ? 200 ?? cvdcpl<2:0> (adccon2<28:26>) = 001 ? cvdcpl<2:0> (adccon2<28:26>) = 010 ? cvdcpl<2:0> (adccon2<28:26>) = 011 ? cvdcpl<2:0> (adccon2<28:26>) = 100 ? cvdcpl<2:0> (adccon2<28:26>) = 101 ? cvdcpl<2:0> (adccon2<28:26>) = 110 ? cvdcpl<2:0> (adccon2<28:26>) = 111 1012 14 16 18 19 21 t ad source impedance ? 500 ?? cvdcpl<2:0> (adccon2<28:26>) = 001 ? cvdcpl<2:0> (adccon2<28:26>) = 010 ? cvdcpl<2:0> (adccon2<28:26>) = 011 ? cvdcpl<2:0> (adccon2<28:26>) = 100 ? cvdcpl<2:0> (adccon2<28:26>) = 101 ? cvdcpl<2:0> (adccon2<28:26>) = 110 ? cvdcpl<2:0> (adccon2<28:26>) = 111 1316 18 21 23 26 28 t ad source impedance ? 1 k ?? cvdcpl<2:0> (adccon2<28:26>) = 001 ? cvdcpl<2:0> (adccon2<28:26>) = 010 ? cvdcpl<2:0> (adccon2<28:26>) = 011 ? cvdcpl<2:0> (adccon2<28:26>) = 100 ? cvdcpl<2:0> (adccon2<28:26>) = 101 ? cvdcpl<2:0> (adccon2<28:26>) = 110 ? cvdcpl<2:0> (adccon2<28:26>) = 111 4148 56 63 70 78 85 t ad source impedance ? 5 k ?? cvdcpl<2:0> (adccon2<28:26>) = 001 ? cvdcpl<2:0> (adccon2<28:26>) = 010 ? cvdcpl<2:0> (adccon2<28:26>) = 011 ? cvdcpl<2:0> (adccon2<28:26>) = 100 ? cvdcpl<2:0> (adccon2<28:26>) = 101 ? cvdcpl<2:0> (adccon2<28:26>) = 110 ? cvdcpl<2:0> (adccon2<28:26>) = 111 note 1: these parameters are characterized, but not tested in manufacturing. 2: the adc module is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is guaranteed, but not characterized.
? 2015-2016 microchip technology inc. ds60001320d-page 653 pic32mz embedded connectivity with floating point unit (ef) family table 37-41: temperature sensor specifications ac characteristics standard operating conditions (see note 1): 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics min. typical max. units conditions ts10 v ts rate of change +5 mv/oc ts11 t r resolution 5 oc ts12 iv temp voltage range 0.5 1.5 v ts13 t min minimum temperature -40 oc iv temp = 0.5v ts14 t max maximum temperature 160 oc iv temp = 1.5v note 1: the temperature sensor is functional at v bormin < v dd < v ddmin , but with degraded performance. unless otherwise stated, module functionality is tested, but not characterized.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 654 ? 2015-2016 microchip technology inc. figure 37-21: parallel slave port timing pmcsx pmrd pmwr pmd ps1 ps2 ps3 ps4 ps5 ps6 ps7 table 37-42: parallel slave port requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typ. max. units conditions ps1 tdtv2wrh data in valid before pm wr or pmcsx inactive (setup time) 20 ns ps2 twrh2dti pmwr or pmcsx inactive to ? data-in invalid (hold time) 40 ns ps3 trdl2dtv pmrd and pmcs x active to ? data-out valid 60 ns ps4 trdh2dti pmrd active ? or pmcsx inactive to data-out invalid 0 10 ns ps5 tc s pmcsx active time t pbclk 2 + 40 ns ps6 t wr pmwr active time t pbclk 2 + 25 ns ps7 t rd pmrd active time t pbclk 2 + 25 ns note 1: these parameters are characterized, but not tested in manufacturing.
? 2015-2016 microchip technology inc. ds60001320d-page 655 pic32mz embedded connectivity with floating point unit (ef) family figure 37-22: parallel master port read timing diagram t pbclk 2 t pbclk 2 t pbclk 2 t pbclk 2 t pbclk 2 t pbclk 2 t pbclk 2 t pbclk 2 pbclk2 pmall/pmalh pmd pma pmrd pmcsx pmwr pm5 data address<7:0> pm1 pm3 pm6 data pm7 address<7:0> address pm4 pm2 table 37-43: parallel master po rt read timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typ. max. units conditions pm1 t lat pmall/pmalh pulse width 1 t pbclk 2 pm2 t adsu address out valid to pmall/ pmalh invalid (address setup time) 2 t pbclk 2 pm3 t adhold pmall/pmalh invalid to address out invalid (address hold time) 1 t pbclk 2 pm4 t ahold pmrd inactive to address out invalid (address hold time) 5 ns pm5 t rd pmrd pulse width 1 t pbclk 2 pm6 t dsu pmrd or pmenb active to data in valid (data setup time) 15 ns pm7 t dhold pmrd or pmenb inactive to data in invalid (data hold time) 80 ns note 1: these parameters are characterized, but not tested in manufacturing.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 656 ? 2015-2016 microchip technology inc. figure 37-23: parallel master port write timing diagram t pbclk 2 t pbclk 2 t pbclk 2 t pbclk 2 t pbclk 2 t pbclk 2 t pbclk 2 t pbclk 2 pbclk2 pmall/pmalh pmd pma pmwr pmcsx pmrd pm12 pm13 pm11 address address<7:0> data pm2 + pm3 pm1 table 37-44: parallel master port write timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typ. max. units conditions pm11 t wr pmwr pulse width 1 t pbclk 2 pm12 t dvsu data out valid before pmwr or pmenb goes inactive (data setup time) 2 t pbclk 2 pm13 t dvhold pmwr or pmemb invalid to data out invalid (data hold time) 1 t pbclk 2 note 1: these parameters are characterized, but not tested in manufacturing.
? 2015-2016 microchip technology inc. ds60001320d-page 657 pic32mz embedded connectivity with floating point unit (ef) family table 37-45: usb otg electrical specifications ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typ. max. units conditions usb313 v usb 3 v 3 usb voltage 3.0 3.6 v voltage on v usb 3 v 3 must be in this range for proper usb operation low-speed and full-speed modes usb315 v ilusb input low voltage for usb buffer 0.8 v usb316 v ihusb input high voltage for usb buffer 2.0 v usb318 v difs differential input sensitivity 0.2 v the difference between d+ and d- must exceed this value while vcm is met usb319 vcm differential common mode range 0.8 2.5 v usb321 v ol voltage output low 0.0 0.3 v 1.425 k ? load connected to v usb 3 v 3 usb322 v oh voltage output high 2.8 3.6 v 14.25 k ? load connected to ground hi-speed mode usb323 v hsdi differential input signal level 150 mv usb324 v hssq sq detection threshold 100 150 mv usb325 v hscm common mode voltage range -50 500 mv usb326 v hsoh data signaling high 360 440 mv usb327 v hsol data signaling low -10 10 mv usb328 v chirpj chirp j level 700 1100 mv usb329 v chirpk chirp k level -900 -500 mv usb330 z hsdrv driver output resistance 45 ? note 1: these parameters are characterized, but not tested in manufacturing.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 658 ? 2015-2016 microchip technology inc. table 37-46: ethernet module specifications figure 37-24: mdio sourced by the pic32 device figure 37-25: mdio sourced by the phy ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. characteristic min. typical max. units conditions miim timing requirements et1 mdc duty cycle 40 60 % et2 mdc period 400 ns et3 mdio output setup and hold 10 10 ns see figure 37-24 et4 mdio input setup and hold 0 300 ns see figure 37-25 mii timing requirements et5 tx clock frequency 25 mhz et6 tx clock duty cycle 35 65 % et7 etxdx, eten, etxerr output delay 0 25 ns see figure 37-26 et8 rx clock frequency 25 mhz et9 rx clock duty cycle 35 65 % et10 erxdx, erxdv, erxerr setup and hold 10 30 ns see figure 37-27 rmii timing requirements et11 reference clock frequency 50 mhz et12 reference clock duty cycle 35 65 % et13 etxdx, eten, setup and hold 2 4 ns et14 erxdx, erxdv, erxerr setup and hold 2 4 ns et3 (hold) (setup) et3 mdc mdio v ihmin v ilmax v ihmin v ilmax v ihmin v ilmax v ihmin v ilmax et4 mdc mdio
? 2015-2016 microchip technology inc. ds60001320d-page 659 pic32mz embedded connectivity with floating point unit (ef) family figure 37-26: transmit signal ti ming relationships at the mii figure 37-27: receive signal ti ming relationships at the mii et7 tx clock etxd<3:0>, v ihmin v ilmax v ihmin v ilmax eten, etxerr et10 (hold) rx clock erxd<3:0>, v ihmin v ilmax v ihmin v ilmax (setup) et10 erxdv, erxerr
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 660 ? 2015-2016 microchip technology inc. figure 37-28: ebi page read timing figure 37-29: ebi write timing address 00 01 10 11 00 read data read data read data read data tebico tebico tebico tebico tebico tebico tebico tebico tebico tebico tebico tebico tebico tebidh tebidh tebids tebidh tebids tebidh tebids tebids tebi-prc tebi-prc tebi-prc tebi-prc tebi-prc tebi-rc tebi-prc tebi-rc pbclk8 ebia ebia<1:0> ebicsx ebibsx ebioe ebid<15:0> address byte selects write data tebido tebido tebico tebico tebico tebico tebico tebico tebico tebico tebi-wr tebi-wr tebi-wp tebi-wp tebi-as tebi-as pbclk8 ebia ebicsx ebibsx ebioe ebiwe ebid<15:0>
? 2015-2016 microchip technology inc. ds60001320d-page 661 pic32mz embedded connectivity with floating point unit (ef) family table 37-47: ebi timing requirements table 37-48: ebi thro ughput requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol characteristic min. typ. max. units conditions eb10 t ebiclk internal ebi clock period ? (pbclk8) 10 ns eb11 t ebirc ebi read cycle time ? (trc<5:0>) 20 ns eb12 t ebiprc ebi page read cycle time (tprc<3:0>) 20 ns eb13 t ebias ebi write address setup (tas<1:0>) 10 ns eb14 t ebiwp ebi write pulse width ? (twp<5:0>) 10 ns eb15 t ebiwr ebi write recovery time (twr<1:0>) 10 ns eb16 t ebico ebi output control signal delay 5 ns see note 1 eb17 t ebido ebi output data signal delay 5 ns see note 1 eb18 t ebids ebi input data setup 5 ns see note 1 eb19 t ebidh ebi input data hold 3 ns see note 1, 2 note 1: maximum pin capacitance = 10 pf. 2: hold time from ebi address change is 0 ns. ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. characteristic min. typ. max. units conditions eb20 asynchronous sram read 100 mbps eb21 asynchronous sram write 533 mbps note 1: maximum pin capacitance = 10 pf. 2: hold time from ebi address change is 0 ns.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 662 ? 2015-2016 microchip technology inc. figure 37-30: ejtag timing characteristics t tckcyc t tckhigh t tcklow t rf t rf t rf t rf t tse t up t thold t tdoout t tdozstate defined undefined t trst*low t rf tck tdo trst* tdi tms table 37-49: ejtag timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +125c for extended param. no. symbol description (1) min. max. units conditions ej1 t tckcyc tck cycle time 25 ns ej2 t tckhigh tck high time 10 ns ej3 t tcklow tck low time 10 ns ej4 t tsetup tap signals setup time before rising tck 5 ns ej5 t thold tap signals hold time after rising tck 3 ns ej6 t tdoout tdo output delay time from falling tck 5 ns ej7 t tdozstate tdo 3-state delay time from falling tck 5 ns ej8 t trstlow trst low time 25 ns ej9 t rf tap signals rise/fall time, all input and output ns note 1: these parameters are characterized, but not tested in manufacturing.
? 2015-2016 microchip technology inc. ds60001320d-page 663 pic32mz embedded connectivity with floating point unit (ef) family 38.0 extended temperature electrical characteristics this section provides an overview of the pic32mz ef electrical characteristics for devices running up to 125oc. additional information will be provided in future revisions of this document as it becomes available. the specifications for extended temperature are identical to those shown in 37.0 electrical characteristics , with the exception of the parameters listed in this chapter. parameters in this chapter begin with the letter e, which denotes extended temperature operation. for example, parameter dc28 in 37.0 electrical characteristics , is the extended temperature operation equivalent for edc28. absolute maximum ratings for the pic32mz ef devices are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. absolute maximum ratings (see note 1) ambient temperature under bias................................................................................................. ........... .-40c to +125c note 1: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 664 ? 2015-2016 microchip technology inc. 38.1 dc characteristics table 38-2: dc characteristics: operating current (i dd ) table 38-1: operating mips vs. voltage characteristic v dd range (in volts) (note 1) temp. range (in c) max. frequency comment pic32mz ef devices edc5 2.1v-3.6v -40c to +125c 180 mhz note 1: overall functional device operation at v bormin < v dd < v ddmin is guaranteed, but not characterized. all device analog modules, such as adc, etc., will function, but with degraded performance below v ddmin . refer to parameter bo10 in ta b l e 37-5 for bor values. dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +125c for extended parameter no. typical (3) maximum (6) units conditions operating current (i dd ) (1) edc20 8 54 ma 4 mhz (note 4,5) edc21 10 60 ma 10 mhz (note 5) edc22 32 95 ma 60 mhz (note 2,4) edc23 40 105 ma 80 mhz (note 2,4) edc25 61 125 ma 130 mhz (note 2,4) edc26 72 140 ma 160 mhz (note 2,4) edc28 81 150 ma 180 mhz (note 2,4) note 1: a devices i dd supply current is mainly a function of the operating voltage and frequency. other factors, such as pbclk (peripheral bus clock) frequency, number of peripheral modules enabled, internal code execution pattern, i/o pin loading and switching rate, oscillator type, as well as temperature, can hav e an impact on the current consumption. 2: the test conditions for i dd measurements are as follows: oscillator mode is ec+pll with osc1 driven by external square wave from rail-to-rail, (osc1 input clock input over/undershoot < 100 mv required) osc2/clko is configured as an i/o input pin usb pll is disabled (usbmd = 1 ), v usb 3 v 3 is connected to v ss cpu, program flash, and sram data memory are operational, program flash memory wait states are equal to four l1 cache and prefetch modules are enabled no peripheral modules are operating, (on bit = 0 ), and the associated pmd bit is set. all clocks are disabled on bit (pbxdiv<15>) = 0 (x ?? 1,7) wdt, dmt, clock switching, fail-safe clock monitor, and secondary oscillator are disabled all i/o pins are configured as inputs and pulled to v ss mclr = v dd cpu executing while(1) statement from flash rtcc and jtag are disabled 3: data in typical column is at 3.3v, +25c at specified operating frequency unless otherwise stated. parameters are for design guidance only and are not tested. 4: this parameter is characterized, but not tested in manufacturing. 5: note 2 applies with the following exceptions: l1 cache and prefetch modules are disabled, program flash memory wait states are equal to seven. 6: data in the maximum column is at 3.3v, +125oc at specified operating frequency. parameters are for design guidance only and are not tested.
? 2015-2016 microchip technology inc. ds60001320d-page 665 pic32mz embedded connectivity with floating point unit (ef) family table 38-3: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +125c for extended parameter no. typical (2) maximum (4) units conditions idle current (i idle ): core off, clock on base current (note 1) edc30a 7 52 ma 4 mhz (note 3) edc31a 8 56 ma 10 mhz edc32a 13 66 ma 60 mhz (note 3) edc33a 21 86 ma 130 mhz (note 3) edc34 26 96 ma 180 mhz (note 3) note 1: the test conditions for i idle current measurements are as follows: oscillator mode is ec+pll with osc1 driven by external square wave from rail-to-rail, (osc1 input clock input over/undershoot < 100 mv required) osc2/clko is configured as an i/o input pin usb pll is disabled (usbpmd = 1 ), v usb 3 v 3 is connected to v ss , pbclkx divisor = 1:128 (x ? 7) cpu is in idle mode (cpu core halted) l1 cache and prefetch modules are disabled no peripheral modules are operating, (on bit = 0 ), but the associated pmd bit is cleared (except usbpmd) wdt, dmt, clock switching, fail-safe clock monitor, and secondary oscillator are disabled all i/o pins are configured as inputs and pulled to v ss mclr = v dd rtcc and jtag are disabled 2: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: this parameter is characterized, but not tested in manufacturing. 4: data in the maximum column is at 3.3v, +125oc at specified operating frequency. parameters are for design guidance only and are not tested.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 666 ? 2015-2016 microchip technology inc. table 38-4: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +125c for extended param. no. typical (2) maximum (5) units conditions power-down current (i pd ) (note 1) edc40m 20 46 ma +125oc base power-down current module differential current edc41e 15 50 a 3.6v watchdog timer current: ? i wdt (note 3) edc42e 25 50 a 3.6v rtcc + timer1 w/32 khz crystal: ? i rtcc (note 3) edc43d 3 3.8 ma 3.6v adc: ? i adc (notes 3, 4) edc44 15 50 a 3.6v deadman timer current: ? i dmt (note 3) note 1: the test conditions for i pd current measurements are as follows: oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail-to-rail, (osc1 input clock input over/undershoot < 100 mv required) osc2/clko is configured as an i/o input pin usb pll is disabled (usbmd = 1 ), v usb 3 v 3 is connected to v ss cpu is in sleep mode l1 cache and prefetch modules are disabled no peripheral modules are operating, (on bit = 0 ), and the associated pmd bit is set. all clocks are disabled on bit (pbxdiv<15>) = 0 (x ?? 1,7) wdt, dmt, clock switching, fail-safe clock monitor, and secondary oscillator are disabled all i/o pins are configured as inputs and pulled to v ss mclr = v dd rtcc and jtag are disabled voltage regulator is in stand-by mode (vregs = 0 ) 2: data in the typical column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the ? current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: voltage regulator is operational (vregs = 1 ). 5: data in the maximum column is at 3.3v, +125oc at specified operating frequency, unless otherwise stated. parameters are for design guidance only and are not tested.
? 2015-2016 microchip technology inc. ds60001320d-page 667 pic32mz embedded connectivity with floating point unit (ef) family 38.2 ac characteristics and timing parameters the information contained in this section defines pic32mz ef device ac characteristics and timing parameters. table 38-5: system timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +125c for extended param. no. symbol characteristics min. typ. max. units conditions eos51 f sys system frequency dc 180 mhz usb module disabled 30 180 mhz usb module enabled eos55a f pb peripheral bus frequency dc 90 mhz for pbclkx, x ? 4, 7 eos55b dc 180 mhz for pbclk4, pbclk7 eos56 f ref reference clock frequency 45 mhz for refclki1, 3, 4 and refclko1, 3, 4 pins table 38-6: pll clock timing specifications ac characteristics standard operating conditions: 2.1v to 3.6v ? (unless otherwise stated) operating temperature -40c ? t a ? +125c for extended param. no. symbol characteristics (1) min. typical max. units conditions eos54a f pll pll output frequency range 10 180 mhz note 1: these parameters are characterized, but not tested in manufacturing. 2: this jitter specification is based on clock-cycle by clock-cycle measurements. to get the eff ective jitter for individual time-bases on communication clocks, use the following formula: for example, if pbclk2 = 100 mhz and spi bit rate = 50 mhz, the effective jitter is as follows: effectivejitter d clk pbclk 2 communicationclock --------------------------------------------------------- - -------------------------------------------------------------- = effectivejitter d clk 100 50 -------- - ------------- - d clk 1.41 ------------- - ==
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 668 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 669 pic32mz embedded connectivity with floating point unit (ef) family 39.0 252 mhz electrical characteristics this section provides an overview of the pic32mz ef electrical characteristics for devices run ning at 252 mhz. additional information will be provided in future revisions of this document as it becomes available. the specifications for 252 mhz are identical to those shown in 37.0 electrical characteristics including absolute maximum ratings, with the exception of the parameters listed in this chapter. parameters in this chapter begin with the letter m, which denotes 252 mhz operation. for example, parameter dc27a in 37.0 electrical characteristics , is the up to 200 mhz operation equivalent for mdc27a.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 670 ? 2015-2016 microchip technology inc. 39.1 dc characteristics table 39-2: dc characteristics: operating current (i dd ) table 39-1: operating mips vs. voltage characteristic v dd range (in volts) (note 1) temp. range (in c) max. frequency comment pic32mz ef devices mdc5 2.1v-3.6v -40c to +85c 252 mhz note 1: overall functional device operation at v bormin < v dd < v ddmin is guaranteed, but not characterized. all device analog modules, such as adc, etc., will function, but with degraded performance below v ddmin . refer to parameter bo10 in ta b l e 37-5 for bor values. dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial parameter no. typical (3) maximum (6) units conditions operating current (i dd ) (1) mdc27a 156 170 ma 252 mhz (note 2) mdc27b 115 135 ma 252 mhz (note 4,5) note 1: a devices i dd supply current is mainly a function of the operating voltage and frequency. other factors, such as pbclk (peripheral bus clock) frequency, number of peripheral modules enabled, internal code execution pattern, i/o pin loading and switching rate, oscillator type, as well as temperature, can hav e an impact on the current consumption. 2: the test conditions for i dd measurements are as follows: oscillator mode is ec+pll with osc1 driven by external square wave from rail-to-rail, (osc1 input clock input over/undershoot < 100 mv required) osc2/clko is configured as an i/o input pin usb pll is disabled (usbmd = 1 ), v usb 3 v 3 is connected to v ss cpu, program flash, and sram data memory are operational, program flash memory wait states are equal to four l1 cache and prefetch modules are enabled no peripheral modules are operating, (on bit = 0 ), and the associated pmd bit is set. all clocks are disabled on bit (pbxdiv<15>) = 0 (x ?? 1,7) wdt, dmt, clock switching, fail-safe clock monitor, and secondary oscillator are disabled all i/o pins are configured as inputs and pulled to v ss mclr = v dd cpu executing while(1) statement from flash rtcc and jtag are disabled 3: data in typical column is at 3.3v, +25c at specified operating frequency unless otherwise stated. parameters are for design guidance only and are not tested. 4: this parameter is characterized, but not tested in manufacturing. 5: note 2 applies with the following exceptions: l1 cache and prefetch modules are disabled, program flash memory wait states are equal to seven. 6: data in the maximum column is at 3.3v, +85oc at specified operating frequency, unless otherwise stated. parameters are for design guidance only and are not tested.
? 2015-2016 microchip technology inc. ds60001320d-page 671 pic32mz embedded connectivity with floating point unit (ef) family table 39-3: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial parameter no. typical (2) maximum (4) units conditions idle current (i idle ): core off, clock on base current (note 1) mdc35 41 60 ma 252 mhz note 1: the test conditions for i idle current measurements are as follows: oscillator mode is ec+pll with osc1 driven by external square wave from rail-to-rail, (osc1 input clock input over/undershoot < 100 mv required) osc2/clko is configured as an i/o input pin usb pll is disabled (usbpmd = 1 ), v usb 3 v 3 is connected to v ss , pbclkx divisor = 1:128 (x ? 7) cpu is in idle mode (cpu core halted) l1 cache and prefetch modules are disabled no peripheral modules are operating, (on bit = 0 ), but the associated pmd bit is cleared (except usbpmd) wdt, dmt, clock switching, fail-safe clock monitor, and secondary oscillator are disabled all i/o pins are configured as inputs and pulled to v ss mclr = v dd rtcc and jtag are disabled 2: data in typical column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: this parameter is characterized, but not tested in manufacturing. 4: data in the maximum column is at 3.3v, +85oc at specified operating frequency, unless otherwise stated. parameters are for design guidance only and are not tested.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 672 ? 2015-2016 microchip technology inc. table 39-4: dc characteristics: program flash memory wait states dc characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial required flash wait states (1) sysclk units conditions with ecc: 0 wait states 1 wait state 2 wait states 4 wait states 0 < sysclk ? 60 60 < sysclk ? 120 120 < sysclk ? 200 200 < sysclk ? 252 mhz without ecc: 0 wait states 1 wait state 2 wait states 4 wait states 0 < sysclk ? 74 74 < sysclk ? 140 140 < sysclk ? 200 200 < sysclk ? 252 mhz note 1: to use wait states, the prefetch module must be enabled (prefen<1:0> ? 00 ) and the pfmws<2:0> bits must be written with the desired wait state value.
? 2015-2016 microchip technology inc. ds60001320d-page 673 pic32mz embedded connectivity with floating point unit (ef) family 39.2 ac characteristics and timing parameters the information contained in this section defines pic32mz ef device ac characteristics and timing parameters. table 39-5: system timing requirements ac characteristics standard operating conditions: 2.1v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param. no. symbol characteristics minimum typical maximum units conditions mos51 f sys system frequency dc 252 mhz usb module disabled 60 252 mhz usb module enabled mos55a f pb peripheral bus frequency dc 100 mhz for pbclkx, x ? 4, 7 (see note 1 ) mos55b dc 200 mhz for pbclk4 mos55c dc 252 mhz for pbclk7 mos56 f ref reference clock frequency 50 mhz for refclki1, 3, 4 and refclko1, 3, 4 pins note 1: if the devcfg registers are confi gured for a sysclk speed greater than 200 mhz, these pbclks will be running faster than the maximum rating when the device comes out of reset. to ensure proper operation, firmware must start the device at a speed less than or equal to 200 mhz, adjust the speed of the pbclks, and then raise the sysclk speed to the desired speed. table 39-6: pll clock timing specifications ac characteristics standard operating conditions: 2.1v to 3.6v ? (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param. no. symbol characteristics (1) min. typical max. units conditions mos54a f pll pll output frequency range 10 252 mhz note 1: these parameters are characterized, but not tested in manufacturing. 2: this jitter specification is based on clock-cycle by clock-cycle measurements. to get the eff ective jitter for individual time-bases on communication clocks, use the following formula: for example, if pbclk2 = 100 mhz and spi bit rate = 50 mhz, the effective jitter is as follows: effectivejitter d clk pbclk 2 communicationclock --------------------------------------------------------- - -------------------------------------------------------------- = effectivejitter d clk 100 50 -------- - ------------- - d clk 1.41 ------------- - ==
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 674 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 675 pic32mz embedded connectivity with floating point unit (ef) family 40.0 ac and dc characteristics graphs figure 40-1: v oh C 4x driver pins figure 40-2: v ol C 4x driver pins figure 40-3: v oh C 8x driver pins figure 40-4: v ol C 8x driver pins note: the graphs provided are a statistical summary based on a limited number of samples and are pr ovided for design guidance purpose s only. the performance characteristics listed herein are not tested or guaranteed. in some graphs, the data presented may be outside the specified operating range (e.g., outsid e specified power s upply range) and therefore, outside the warranted range. r 0.050 r 0.045 r 0.040 r 0.035 r 0.030 r 0.025 0020 ioh (a) voh (v) r 0 . 020 r 0.015 r 0.010 r 0.005 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 absolute maimum 0 020 0.025 0.030 0.035 0.040 0.045 0.050 iol (a) vol (v) 0.000 0.005 0.010 0.015 0 . 020 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 absolute maimum r 0.090 r 0.080 r 0.070 r 0.060 r 0.050 r 0.040 ioh (a) voh (v) r 0.030 r 0.020 r 0.010 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 absolute maimum 0.040 0.050 0.060 0.070 0.080 0.090 iol (a) vol (v) 0.000 0.010 0.020 0.030 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 absolute maimum
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 676 ? 2015-2016 microchip technology inc. figure 40-5: v oh C 12x driver pins figure 40-6: v ol C 12x driver pins figure 40-7: typical temperature sensor voltage r 0.140 r 0.120 r 0.100 r 0.080 r 0.060 ioh (a) voh (v) r 0.040 r 0.020 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 absolute maimum 0.060 0.080 0.100 0.120 0.140 iol (a) vol (v) 0.000 0.020 0.040 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 absolute maimum 0.450 0.550 0.650 0.750 0.850 0.950 1.050 1.150 1.250 1.350 1.450 -40-30-20-10 0 102030405060708090100110120130 voltage (v) temperature (celsius)
? 2015-2016 microchip technology inc. ds60001320d-page 677 pic32mz embedded connectivity with floating point unit (ef) family 41.0 packaging information 41.1 package marking information mz2048efh 064-i/pt 0510017 3 e legend: xx...x customer-specific information ? y year code (last digit of calendar year) ? yy year code (last 2 digits of calendar year) ? ww week code (week of january 1 is week 01) ? nnn alphanumeric traceability code ? pb-free jedec designator for matte tin (sn) ? * this package is pb-free. the pb-free jedec designator ( ) ? can be found on the outer packaging for this package. note: in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 64-lead tqfp (10x10x1 mm) xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example 100-lead tqfp (14x14x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example mz2048efh 100-i/pf 0510017 3 e xxxxxxxxxx 64-lead qfn (9x9x0.9 mm) xxxxxxxxxx xxxxxxxxxx yywwnnn mz2048efh example 064-i/mr 0510017 3 e xxxxxxxxxxxx
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 678 ? 2015-2016 microchip technology inc. 41.1 package marking information (continued) xxxxxxxxxx 124-lead vtla (9x9x0.9 mm) xxxxxxxxxx xxxxxxxxxx yywwnnn mz2048efh example 124-i/tl 0510017 3 e 144-lead tqfp (16x16x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example mz2048efh 144-i/ph 0510017 3 e legend: xx...x customer-specific information ? y year code (last digit of calendar year) ? yy year code (last 2 digits of calendar year) ? ww week code (week of january 1 is week 01) ? nnn alphanumeric traceability code ? pb-free jedec designator for matte tin (sn) ? * this package is pb-free. the pb-free jedec designator ( ) ? can be found on the outer packaging for this package. note: in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 100-lead tqfp (12x12x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example mz2048efh 100-i/pt 0510017 3 e 144-lead lqfp (20x20x1.40 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example mz2048efh 144-i/pl 0510017 3 e xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx
? 2015-2016 microchip technology inc. ds60001320d-page 679 pic32mz embedded connectivity with floating point unit (ef) family 41.2 package details microchip technology drawing no. c04-2213b 64-lead plastic quad flat, no lead package (mr) ? 9x9x0.9 mm body [qfn] with 0.40 mm contact length and 7.70x7.70mm exposed pad silk screen 12 64 c2 c1 w2 ev ?v y1 x1 e t2 recommended land pattern dimension limits units c2 optional center pad width contact pad spacing optional center pad length contact pitch t2 w2 7.50 7.50 millimeters 0.50 bsc min e max 8.90 contact pad length (x20) contact pad width (x20) y1 x1 0.90 0.30 nom c1 contact pad spacing 8.90 contact pad to center pad (x20) g 0.20 thermal via diameter v thermal via pitch ev 0.301.00 bsc: basic dimension. theoretically exact value shown without tolerances. notes: dimensioning and tolerancing per asme y14.5m for best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process 1.2. g ev for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note:
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 680 ? 2015-2016 microchip technology inc. b a 0.25 c 0.25 c 0.10 c a b 0.05 c (datum b) (datum a) c seating plane note 1 1 2 n 2x top view side view bottom view note 1 1 2 n 0.10 c a b 0.10 c a b 0.10 c 0.08 c microchip technology drawing c04-213b sheet 1 of 2 64-lead plastic quad flat, no lead package (mr) ? 9x9x0.9 mm body [qfn] 2x 64x for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: with 7.70 x 7.70 exposed pad [qfn] a3 a a1 d e e 64x b d2 e2 k l e 2
? 2015-2016 microchip technology inc. ds60001320d-page 681 pic32mz embedded connectivity with floating point unit (ef) family microchip technology drawing c04-213b sheet 2 of 2 64-lead plastic quad flat, no lead package (mr) ? 9x9x0.9 mm body [qfn] for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: with 7.70 x 7.70 exposed pad [qfn] 0.50 0.30 0.40 contact length l contact-to-exposed pad ref: reference dimension, usually without tolerance, for information purposes only. 3. bsc: basic dimension. theoretically exact value shown without tolerances. 1. notes:2. k- 0.20 - overall height overall length exposed pad width contact thickness number of pins contact width exposed pad length overall width standoff pitch e2 d2 b d a3 e a1 7.80 7.60 7.70 9.00 bsc 0.25 7.70 7.600.20 7.800.30 0.02 9.00 bsc 0.20 ref 0.00 0.05 dimension limits e a n units max min nom 0.50 bsc 0.85 64 0.80 0.90 millimeters dimensioning and tolerancing per asme y14.5m. pin 1 visual index feature may vary, but must be located within the hatched area. package is saw singulated.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 682 ? 2015-2016 microchip technology inc. 0.20 c a-b d 64 x b 0.08 c a-b d c seating plane 4x n/4 tips top view side view for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing c04-085c sheet 1 of 2 64-lead plastic thin quad flatpack (pt)-10x10x1 mm body, 2.00 mm footprint [tqfp] d e e1 d1 d a b 0.20 h a-b d 4x d1/2 e a 0.08 c a1 a2 see detail 1 a a e1/2 note 1 note 2 1 2 3 n 0.05
? 2015-2016 microchip technology inc. ds60001320d-page 683 pic32mz embedded connectivity with floating point unit (ef) family for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 64-lead plastic thin quad flatpack (pt)-10x10x1 mm body, 2.00 mm footprint [tqfp] 13 12 11 e mold draft angle bottom 13 12 11 d mold draft angle top 0.27 0.22 0.17 b lead width 0.20 - 0.09 c lead thickness 10.00 bsc d1 molded package length 10.00 bsc e1 molded package width 12.00 bsc d overall length 12.00 bsc e overall width 7 3.5 0 i foot angle 0.75 0.60 0.45 l foot length 0.15 - 0.05 a1 standoff 1.05 1.00 0.95 a2 molded package thickness 1.20 - - a overall height 0.50 bsc e lead pitch 64 n number of leads max nom min dimension limits millimeters units footprint l1 1.00 ref 2. chamfers at corners are optional; size may vary. 1. pin 1 visual index feature may vary, but must be located within the hatched area. 4. dimensioning and tolerancing per asme y14.5m bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. 3. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25mm per side. noes: microchip technology drawing c04-085c sheet 2 of 2 l (l1) e c h x x=a?b or d e/2 detail 1 section a-a t
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 684 ? 2015-2016 microchip technology inc. recommended land pattern for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: dimension limits units c1 contact pad spacing contact pad spacing contact pitch c2 millimeters 0.50 bsc min e max 11.4011.40 contact pad length (x28) contact pad width (x28) y1 x1 1.50 0.30 bsc: basic dimension. theoretically exact value shown without tolerances. notes: 1. dimensioning and tolerancing per asme y14.5m microchip technology drawing c04-2085b sheet 1 of 1 g distance between pads 0.20 nom 64-lead plastic thin quad flatpack (pt)-10x10x1 mm body, 2.00 mm footprint [tqfp] c2 c1 e g y1 x1
? 2015-2016 microchip technology inc. ds60001320d-page 685 pic32mz embedded connectivity with floating point unit (ef) family d d1 e b e1 e n note 1 note 2 123 c l a1 l1 a2 a
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 686 ? 2015-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2015-2016 microchip technology inc. ds60001320d-page 687 pic32mz embedded connectivity with floating point unit (ef) family d d1 e e1 e b n 123 note 1 note 2 c l a1 l1 a a2
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 688 ? 2015-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2015-2016 microchip technology inc. ds60001320d-page 689 pic32mz embedded connectivity with floating point unit (ef) family
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 690 ? 2015-2016 microchip technology inc.
? 2015-2016 microchip technology inc. ds60001320d-page 691 pic32mz embedded connectivity with floating point unit (ef) family for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: recommended land pattern silk screen dimension limits units c1 optional center pad length contact pad spacing contact pad spacing optional center pad chamfer (x4) c2 w3 w2 0.10 6.60 millimeters min max 8.508.50 contact pad length (x124) contact pad width (x124) x2 x1 0.30 0.30 bsc: basic dimension. theoretically exact value shown without tolerances. notes: 1. dimensioning and tolerancing per asme y14.5m microchip technology drawing no. c04-2193a nom optional center pad width t2 contact to center pad clearance (x4) g5 pad clearance g4 pad clearance g3 pad clearance g2 contact pitch 0.50 bsc e pad clearance g1 6.60 0.30 0.20 0.20 0.20 0.20 e e/2 w2 w3 g2 g4 x1 g5 x4 c2 c1 g3 g1 x2 e t2 124-very thin leadless array package (tl) ? 9x9x0.9 mm body [vtla]
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 692 ? 2015-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2015-2016 microchip technology inc. ds60001320d-page 693 pic32mz embedded connectivity with floating point unit (ef) family note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 694 ? 2015-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2015-2016 microchip technology inc. ds60001320d-page 695 pic32mz embedded connectivity with floating point unit (ef) family 144-lead plastic low profile quad flatpack (pl) C 20x20x1.40 mm body, with 2.00 mm footprint [lqfp] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 696 ? 2015-2016 microchip technology inc. 144-lead plastic low profile quad flatpack (pl) C 20x20x1.40 mm body, with 2.00 mm footprint [lqfp] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2015-2016 microchip technology inc. ds60001320d-page 697 pic32mz embedded connectivity with floating point unit (ef) family note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 698 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 699 pic32mz embedded connectivity with floating point unit (ef) family appendix a: migrating from pic32mx5xx/6xx/7xx to pic32mz ef this appendix provides an overview of considerations for migrating from pic32mx5xx/6xx/7xx devices to the pic32mz ef family of devices. the code devel - oped for pic32mx5xx/6xx/7xx devices can be ported to pic32mz ef devices after making the appropriate changes outlined in the following sections. the pic32mz ef devices are based on a new architecture, and feature many improvements and new capabilities over pic32mx5xx/6xx/7xx devices. a.1 oscillator and pll configuration because the maximum speed of the pic32mz ef family is greater, the configuration of the oscillator is different from prior pic32mx5xx/6xx/7xx devices. table a-1 summarizes the differences (indicated by bold type) between the family devices for the oscillator. table a-1: oscillator co nfiguration differences pic32mx5xx/6xx/7xx feature pic32mz ef feature primary oscillator configuration on pic32mx devices, xt mode had to be selected if the input fre - quency was in the 3 mhz to 10 mhz range (4-10 for pll), and hs mode had to be selected if the input frequency was in the 10 mhz to 20 mhz range. on pic32mz ef devices, hs mode has a wider input frequency range (4 mhz to 12 mhz). the bit setting of 01 is reserved. poscmod<1:0> (devcfg1<9:8>) 11 = primary oscillator disabled 10 = hs oscillator mode selected 01 = xt oscillator mode selected 00 = external clock mode selected poscmod<1:0> (devcfg1<9:8>) 11 = primary oscillator disabled 10 = hs oscillator mode selected 01 = reserved 00 = external clock mode selected on pic32mx devices, crystal mode could be selected with the hs or xt posc setting, but an ex ternal oscillator could be fed into the osc1/clki pin and the part would operate normally. on pic32mz devices, this option is not available. external oscil - lator signals should only be fed into the osc1/clki pin with the posc set to ec mode. oscillator selection on pic32mx devices, clock sele ction choices are as follows: on pic32mz ef devices, clock se lection choices are as follows: fnosc<2:0> (devcfg1<2:0>) nosc<2:0> (osccon<10:8>) 111 = frcdiv 110 = frcdiv16 101 = lprc 100 = sosc 011 = posc with pll module 010 = posc (xt, hs, ec) 001 = frcdiv+pll 000 = frc fnosc<2:0> (devcfg1<2:0>) nosc<2:0> (osccon<10:8>) 111 = frcdiv 110 = reserved 101 = lprc 100 = sosc 011 = reserved 010 = posc (hs or ec) 001 = system pll (spll) 000 = frcdiv cosc<2:0> (osccon<14:12>) 111 = frc divided by frcdiv 110 = frc divided by 16 101 = lprc 100 = sosc 011 = posc + pll module 010 = posc 001 = frcpll 000 = frc cosc<2:0> (osccon<14:12>) 111 = frc divided by frcdiv 110 = bfrc 101 = lprc 100 = sosc 011 = reserved 010 = posc 001 = system pll 000 = frc divided by frcdiv
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 700 ? 2015-2016 microchip technology inc. secondary oscillator enable the location of the soscen bit in the flash configuration words has moved. fsoscen (devcfg1< 5 >) fsoscen (devcfg1< 6 >) pll configuration the fnosc<2:0> and nosc<2:0> bits select between posc and frc. selection of which input clock (posc or frc) is now done through the fplliclk/plliclk bits. fnosc<2:0> (devcfg1<2:0>) nosc<2:0> (osccon<10:8>) fplliclk (devcfg2<7>) plliclk (spllcon<7>) on pic32mx devices, the input frequency to the pll had to be between 4 mhz and 5 mhz. fpllidiv selected how to divide the input frequency to give it the appropriate range. on pic32mz ef devices, the input range for the pll is wider (5 mhz to 64 mhz). the input divider values have changed, and new fpllrng/pllrng bits have been added to indicate under what range the input frequency falls. fpllidiv<2:0> (devcfg2<2:0>) 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider fpllidiv<2:0> (devcfg2<2:0>) pllidiv<2:0> (spllcon<2:0>) 111 = divide by 8 110 = divide by 7 101 = divide by 6 100 = divide by 5 011 = divide by 4 010 = divide by 3 001 = divide by 2 000 = divide by 1 fpllrng<2:0> (devcfg2<6:4>) pllrng<2:0> (spllcon<2:0>) 111 = reserved 110 = reserved 101 = 34-64 mhz 100 = 21-42 mhz 011 = 13-26 mhz 010 = 8-16 mhz 001 = 5-10 mhz 000 = bypass on pic32mx devices, the output frequency of pll is between 60 mhz and 120 mhz. the pll multiplier and divider bits configure the pll for this range. the pll multiplier and divider on pic32mz ef devices have a wider range to accommodate the wider pll specification range. fpllmul< 2 :0> (devcfg2< 6:4 >) pllmult< 2 :0> (osccon<18:16>) 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier fpllmul t < 6 :0> (devcfg2< 14:8 >) pllmult< 6 :0> ( spllcon<22:16> ) 1111111 = multiply by 128 1111110 = multiply by 127 1111101 = multiply by 126 1111100 = multiply by 125 0000000 = multiply by 1 fpllodiv<2:0> (devcfg2<18:16>) pllodiv<2:0> (osccon<29:27>) 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier fpllodiv<2:0> (devcfg2<18:16>) pllodiv<2:0> ( spllcon<26:24> ) 111 = pll divide by 32 110 = pll divide by 32 101 = pll divide by 32 100 = pll divide by 16 011 = pll divide by 8 010 = pll divide by 4 001 = pll divide by 2 000 = pll divide by 2 table a-1: oscillator configur ation differences (continued) pic32mx5xx/6xx/7xx feature pic32mz ef feature
? 2015-2016 microchip technology inc. ds60001320d-page 701 pic32mz embedded connectivity with floating point unit (ef) family crystal/oscillator selection for usb any frequency that can be divided down to 4 mhz using upllidiv, including 4, 8, 12, 16, 20, 40, and 48 mhz. if the usb module is used, the pr imary oscillator is limited to either 12 mhz or 24 mhz. which frequency is used is selected using the upllfsel (devcfg2<30>) bit. usb pll configuration on pic32mx devices, the pll for the usb requires an input fre - quency of 4 mhz. on pic32mz ef devices, the hs usb phy requires an input frequency of 12 mhz or 24 mhz. upllidiv has been replaced with upllfsel. upllidiv<2:0> (devcfg2<10:8>) 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider upllfsel (devcfg2<30>) 1 = upll input clock is 24 mhz 0 = upll input clock is 12 mhz peripheral bus clock configuration on pic32mx devices, there is one peripheral bus, and the clock for that bus is divided from the sysclk using fpbdiv/pbdiv. in addition, the maximum pbclk frequency is the same as sysclk. on pic32mz ef devices, there ar e eight peripheral buses with their own clocks. fpbdiv is removed, and each pbdiv is in its own register for each pbclk. the initial pbclk speed is fixed at reset, and the maximum pbclk speed is limited to100 mhz for all buses, with the exception of pbclk7, which is 200 mhz. fpbdiv<1:0> (devcfg1<5:4>) pbdiv< 1 :0> ( osccon<20:19> ) 11 = pbclk is sysclk divided by 8 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 pbdiv< 6 :0> ( pbxdiv < 6 :0>) 1111111 = pbclkx is sysclk divided by 128 1111110 = pbclkx is sysclk divided by 127 0000011 = pbclkx is sysclk divided by 4 0000010 = pbclkx is sysclk divided by 3 0000001 = pbclkx is sysclk divided by 2 ? (default value for x < 7) 0000000 = pbclkx is sysclk divided by 1 ? (default value for x ? 7) cpu clock configuration on pic32mx devices, the cpu clock is derived from sysclk. on pic32mz ef devices, the cpu clock is derived from pbclk7. frcdiv default on pic32mx devices, the default value for frcdiv was to divide the frc clock by two. on pic32mz ef devices, the default has been changed to divide by one. frcdiv<2:0> (osccon<26:24>) 111 = frc divided by 256 110 = frc divided by 64 101 = frc divided by 32 100 = frc divided by 16 011 = frc divided by 8 010 = frc divided by 4 001 = frc divided by 2 (default) 000 = frc divided by 1 frcdiv<2:0> (osccon<26:24>) 111 = frc divided by 256 110 = frc divided by 64 101 = frc divided by 32 100 = frc divided by 16 011 = frc divided by 8 010 = frc divided by 4 001 = frc divided by 2 000 = frc divided by 1 (default) table a-1: oscillator configur ation differences (continued) pic32mx5xx/6xx/7xx feature pic32mz ef feature
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 702 ? 2015-2016 microchip technology inc. table a-2 illustrates the difference in code setup of the respective parts for maximum speed using an external 24 mhz crystal. table a-2: code differences for maximum speed using an external 24 mhz crystal fail-safe clock monitor (fscm) on pic32mx devices, the internal frc became the clock source on a failure of the clock source. on pic32mz ef devices, a separate internal backup frc (bfrc) becomes the clock source upon a failure at the clock source. on pic32mx devices, a clock failure resulted in the triggering of a specific interrupt when the switchover was complete. on pic32mz ef devices, a nmi is triggered instead, and must be handled by the nmi routine. fscm generates an interrupt. fscm generates a nmi. the definitions of the fcksm<1:0> bits has changed on pic32mz ef devices. fcksm<1:0> (devcfg1<15:14>) 1x = clock switching is disabled, fscm is disabled 01 = clock switching is enabled, fscm is disabled 00 = clock switching is enabled, fscm is enabled fcksm<1:0> (devcfg1<15:14>) 11 = clock switching is enabled and clock monitoring ? is enabled 10 = clock switching is disabled and clock monitoring ? is enabled 01 = clock switching is enabled and clock monitoring is disabled 00 = clock switching is disabled and clock monitoring ? is disabled on pic32mx devices, the cf (osccon<3>) bit indicates a clock failure. writing to this bit initiates a fscm event. on pic32mz ef devices, the cf (osccon<3>) bit has the same functionality as that of pic32mx device; however, an addi - tional cf(rnmicon<1>) bit is available to indicate a nmi event. writing to this bit causes a nmi event, but not a fscm event. on pic32mx devices, the clklock (osccon<7>) bit is controlled by the fscm. on pic32mz ef devices, the clklock (osccon<7>) bit is not impacted by the fscm. clklock (osccon<7>) if clock switching and monitoring is disabled (fcksm<1:0> = 1x ): 1 = clock and pll selections are locked 0 = clock and pll selections are not locked and may be modified if clock switching and monitoring is enabled (fcksm<1:0> = 0x ): clock and pll selections are never locked and may be modified. clklock (osccon<7>) 1 = clock and pll selections are locked 0 = clock and pll selections are not locked and may be modified table a-1: oscillator configur ation differences (continued) pic32mx5xx/6xx/7xx feature pic32mz ef feature pic32mx5xx/6xx/7xx @ 80 hz pic32mz ef @ 200 mhz #include #pragma config poscmod = hs #pragma config fnosc = pripll #pragma config fpllidiv = div_6 #pragma config fpllmul = mul_20 #pragma config fpllodiv = div_1 #define sysfreq (80000000l) #include #pragma config poscmod = hs #pragma config fnosc = spll #pragma config fplliclk = pll_posc #pragma config fpllidiv = div_3 #pragma config fpllrng = range_5_10_mhz #pragma config fpllmult = mul_50 #pragma config fpllodiv = div_2 #define sysfreq (200000000l)
? 2015-2016 microchip technology inc. ds60001320d-page 703 pic32mz embedded connectivity with floating point unit (ef) family a.2 analog-to-digital converter (adc) the pic32mz ef family of devices has a new 12-bit high-speed successive approximation register (sar) adc module that replaces the 10-bit adc module in pic32mx5xx/6xx/7xx devices; therefore, the use of bold type to show differences is not used in the follow - ing table. note that not all register differences are described in this section; however, the key feature differences are listed in tab l e a-3 . table a-3: adc differences pic32mx5xx/6xx/7xx feature pic32mz ef feature clock selection and operating frequency (t ad ) on pic32mx devices, the adc cloc k was derived from either the frc or from the pbclk. on pic32mz ef devices, the three possible sources of the adc clock are frc, refclko3, and sysclk. adrc (ad1con3<15>) 1 = frc clock 0 = clock derived from peripheral bus clock (pbclk) adcsel<1:0> (adccon3<31:30>) 11 = frc 10 = refclko3 01 = sysclk 00 = reserved on pic32mx devices, if the adc clock was derived from the pbclk, that frequency was divided further down, with a maxi- mum divisor of 512, and a minimum divisor of two. on pic32mz ef devices, any adc clock source can be divided down separately for each dedicated adc and the shared adc, with a maximum divisor of 254. the input clock can also be fed directly to the adc. adcs<7:0> (ad1con3<7:0>) 11111111 = 512 * t pb = t ad 00000001 = 4 * t pb = t ad 00000000 = 2 * t pb = t ad adcdiv<6:0> (adctimex<22:16>) adcdiv<6:0> (adccon2<6:0>) 1111111 = 254 * t q = t ad 0000011 = 6 * t q = t ad 0000010 = 4 * t q = t ad 0000001 = 2 * t q = t ad 0000000 = t q = t ad
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 704 ? 2015-2016 microchip technology inc. scan trigger source on pic32mx devices, there are four sources that can trigger a scan conversion in the adc module: auto, timer3, int0, and clearing the samp bit. on pic32mz ef devices, the list of sources for triggering a scan conversion has been expanded to include the comparators, output compare, and two additional timers. in addition, trigger sources can be simulated by setting the rqcnvrt (adccon3<8>) bit. ssrc<2:0> (ad1con1<7:5>) 111 = auto convert 110 = reserved 101 = reserved 100 = reserved 011 = reserved 010 = timer3 period match 001 = active transition on int0 pin 000 = clearing samp bit strgsrc<4:0> (adccon1<20:16>) 11111 = reserved 01101 = reserved 01100 = comparator 2 cout 01011 = comparator 1 cout 01010 = ocmp5 01001 = ocmp3 01000 = ocmp1 00111 = tmr5 match 00110 = tmr3 match 00101 = tmr1 match 00100 = int0 00011 = reserved 00010 = global level software trigger (glswtrg) 00001 = global software trigger (gswtrg) 00000 = no trigger output format on pic32mx devices, the output format was decided for all adc channels based on the setting of the form<2:0> bits. on pic32mz ef devices, the fract bit determines whether fractional or integer format is used. then, each input can have its own setting for input (differential or single-ended) and sign (signed or unsigned) using the diffx and signx bits in the adcimodx registers. form<2:0> (ad1con1<10:8>) 011 = signed fractional 16-bit 010 = fractional 16-bit 001 = signed integer 16-bit 000 = integer 16-bit 111 = signed fractional 32-bit 110 = fractional 32-bit 101 = signed integer 32-bit 100 = integer 32-bit fract (adccon1<23>) 1 = fractional 0 = integer diffx (adcimody) 1 = channel x is using differential mode 0 = channel x is using single-ended mode signx (adcmody) 1 = channel x is using signed data mode 0 = channel x is using unsigned data mode interrupts on pic32mx devices, an interrupt is triggered from the adc module when a certain number of conversions have taken place, irrespective of which channel was converted. on pic32mz ef devices, the adc module can trigger an inter- rupt for each channel when it is c onverted. use the interrupt con- troller bits, iec1<31:27>, iec2<31:0>, and iec3<7:0>, to enable/ disable them. in addition, the adc support one global interrupt to indicate conversion on any number of channels. smpi<3:0> (ad1con2<5:2>) 1111 = interrupt for each 16th sample/convert sequence 1110 = interrupt for each 15th sample/convert sequence 0001 = interrupt for each 2nd sample/convert sequence 0000 = interrupt for each sample/convert sequence agienxx (adcgirqenx) 1 = data ready event will generate a global adc interrupt 0 = no global interrupt in addition, interrupts can be generated for filter and comparator events. table a-3: adc differences (continued) pic32mx5xx/6xx/7xx feature pic32mz ef feature
? 2015-2016 microchip technology inc. ds60001320d-page 705 pic32mz embedded connectivity with floating point unit (ef) family adc calibration on pic32mx devices, the adc m odule can be used immediately, once it is enabled. pic32mz devices require a calibration step prior to operation. this is done by copying the calibration data from devadcx to the corresponding adcxcfg register. i/o pin analog function selection on pic32mx devices, the analog function of an i/o pin was deter- mined by the pcfgx bit in the ad1pcfg register. on pic32mz ef devices, the analog selection function has been moved into a separate register on each i/o port. note that the sense of the bit is different. pcfgx (ad1pcfg) 1 = analog input pin in digital mode 0 = analog input pin in analog mode ansxy (anselx) 1 = analog input pin in analog mode 0 = analog input pin in digital mode electrical specifications and timing requirements refer to section 31. electrical characteristics in the pic32mx5xx/6xx/7xx data sheet for adc module specifications and timing requirements. on pic32mz ef devices, the adc module sampling and conver- sion time and other specifications have changed. refer to 37.0 electrical characteristics for more information. table a-3: adc differences (continued) pic32mx5xx/6xx/7xx feature pic32mz ef feature
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 706 ? 2015-2016 microchip technology inc. a.3 cpu the cpu in the pic32mz ef family of devices has been changed to the mips32 m-class mpu architec - ture. this cpu includes dsp ase, internal data and instruction l1 caches, and a tlb-based mmu. table a-4 summarizes some of the key differences (indicated by bold type) in the internal cpu registers. table a-4: cpu differences pic32mx5xx/6xx/7xx feature pic32mz ef feature l1 data and instruction cache and prefetch wait states on pic32mx devices, the cache was included in the prefetch module outside the cpu. on pic32mz ef devices, the cpu has a separate l1 instruction and data cache in the core. the prefen<1:0> bits still enable the prefetch module; however, the k0<2:0> bits in the cp0 regis- ters controls the internal l1 cache for the designated regions. prefen<1:0> ( checon <5:4>) 11 = enable predictive prefetch for both cacheable and ? non-cacheable regions 10 = enable predictive prefetch for non-cacheable regions only 01 = enable predictive prefetch for cacheable regions only 00 = disable predictive prefetch dcsz<1:0> (checon<9:8>) changing these bits causes all lines to be reinitialized to the invalid state. 11 = enable data caching with a size of 4 lines 10 = enable data caching with a size of 2 lines 01 = enable data caching with a size of 1 line 00 = disable data caching checoh (checon<16>) 1 = invalidate all data and instruction lines 0 = invalidate all data and instruction lines that are not locked prefen<1:0> ( precon <5:4>) 11 = enable predictive prefetch for any address 10 = enable predictive prefetch for cpu instructions and cpu data 01 = enable predictive prefetch for cpu instructions only 00 = disable predictive prefetch k0<2:0> (cp0 reg 16, select 0) 011 = cacheable, non-coherent, write-back, write allocate 010 = uncached 001 = cacheable, non-coherent, write-through, write allocate 000 = cacheable, non-coherent, write-through, no write allocate the program flash memory read wait state frequency points have changed in pic32mz ef devices. the register for accessing the pfmws field has changed from checon to precon. pfmws<2:0> ( checon <2:0>) 111 = seven wait states 110 = six wait states 101 = five wait states 100 = four wait states 011 = three wait states 010 = two wait states (61-80 mhz) 001 = one wait state (31-60 mhz) 000 = zero wait state (0-30 mhz) pfmws<2:0> ( precon <2:0>) 111 = seven wait states 100 = four wait states (200-252 mhz) 011 = reserved 010 = two wait states (133-200 mhz) 001 = one wait state (66-133 mhz) 000 = zero wait states (0-66 mhz) note: wait states listed are for ecc enabled. core instruction execution on pic32mx devices, the cpu can execute mips16e instructions and uses a 16-bit instruction set, which reduces memory size. on pic32mz ef devices, the cpu can operate a mode called micromips. micromips mode is an enhanced mips32? instruction set that uses both 16-bit and 32-bit opcodes. this mode of operation reduces memory size with minimum performance impact. mips16e ? micromips? the bootisa (devcfg0<6>) configuration bit controls the mips32 and micromips modes for boot and exception code. 1 = boot code and exception code is mips32 ? (isaonexc bit is set to 0 and the isa<1:0> bits are set to 10 in the cp0 config3 register) 0 = boot code and exception code is micromips? (isaonexc bit is set to 1 and the isa<1:0> bits are set to 11 in the cp0 config3 register)
? 2015-2016 microchip technology inc. ds60001320d-page 707 pic32mz embedded connectivity with floating point unit (ef) family a.4 resets the pic32mz ef family of devices has updated the resets modules to incorporate the new handling of nmi resets from the wdt, dmt, and the fscm. in addition, some bits have been moved, as summarized in table a-5 . a.5 usb the pic32mz ef family of devices has a new hi- speed usb module, which requires the updated usb stack from microchip. in addition, the usb pll was also updated. see a.1 oscillator and pll configuration for more information and ta bl e a-6 for a list of additional differences. table a-5: reset differences pic32mx5xx/6xx/7xx feature pic32mz ef feature power reset the vregs bit, which controls whether the internal regulator is enabled in sleep mode, has been moved from rcon in pic32mx5xx/6xx/7xx devices to a new pwrcon register in pic32mz ef devices. vregs ( rcon<8> ) 1 = regulator is enabled and is on during sleep mode 0 = regulator is disabled and is off during sleep mode vregs ( pwrcon<0> ) 1 = voltage regulator will remain active during sleep 0 = voltage regulator will go to stand-by mode during sleep watchdog timer reset on pic32mx devices, a wdt expiration immediately triggers a device reset. on pic32mz ef devices, the wdt expiration now causes a nmi. the wdto bit in rnmicon indicates that the wdt caused the nmi. a new timer, nmicnt, runs when the wdt nmi is triggered, and if it expires, the device is reset. wdt expiration immediately causes a device reset. wdt expiration causes a nmi, which can then tri gger the device reset. wdto (rnmicon<24>) 1 = wdt time-out has occurred and caused a nmi 0 = wdt time-out has not occurred nmicnt<7:0> (rnmicon<7:0>) table a-6: usb differences pic32mx5xx/6xx/7xx feature pic32mz ef feature debug mode on pic32mx devices, when st opping on a breakpoint during debugging, the usb module can be configured to stop or continue execution from the freeze peripherals dialog in mplab x ide. on pic32mz ef devices, the usb module continues operating when stopping on a breakpoint during debugging. v buson pin pic32mx devices feature a v buson pin for controlling the external transceiv er power supply. on pic32mz ef devices, the v buson pin is not available. a port pin can be used to achieve the same functionality.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 708 ? 2015-2016 microchip technology inc. a.6 dma the dma controller in pic32mz ef devices is similar to the dma controller in pic32mx5xx/6xx/7xx devices. new features include the extension of pattern matching to two by bytes and the addition of the optional pattern ignore mode. table a-7 lists differ - ences (indicated by bold type) that will affect software migration. table a-7: dma differences pic32mx5xx/6xx/7xx feature pic32mz ef feature read/write status on error the rdwr bit has moved from dmastat<3> in pic32mx5xx/ 6xx/7xx devices to dmastat<31> in pic32mz ef devices. rdwr (dmastat< 3 >) 1 = last dma bus access when an error was detected was a read 0 = last dma bus access when an error was detected was a write rdwr (dmastat< 31 >) 1 = last dma bus access when an error was detected was a read 0 = last dma bus access when an error was detected was a write source-to-destination transfer on pic32mx devices, a dma channel performs a read of the source data and completes the transfer of this data into the desti - nation address before it is ready to read the next data from the source. on pic32mz ef devices, the dma implements a 4-deep queue for data transfers. a dma channel reads the source data and places it into the queue, regardles s of whether previous data in the queue has been delivered to the destination address.
? 2015-2016 microchip technology inc. ds60001320d-page 709 pic32mz embedded connectivity with floating point unit (ef) family a.7 interrupts and exceptions the key difference between interrupt controllers in pic32mx5xx/6xx/7xx devices and pic32mz ef devices concerns vector spacing. previous pic32mx devices had fixed vector spacing, which is adjustable in set increments, and every interrupt had the same amount of space. pic32mz ef devices replace this with a variable offset spacing, where each interrupt has an offset register to determine where to begin execution. in addition, the ifsx, iecx, and ipcx registers for old peripherals have shifted to different registers due to new peripherals. please refer to 7.0 cpu exceptions and interrupt controller to determine where the interrupts are now located. table a-8 lists differences (indicated by bold type) in the registers that will affect software migration. table a-8: interrupt differences pic32mx5xx/6xx/7xx feature pic32mz ef feature vector spacing on pic32mx devices, the vector spacing was determined by the vs field in the cpu core. on pic32mz ef devices, the vector spacing is variable and determined by the interrupt controller. the voffx<17:1> bits in the offx register are set to the offset from ebase where the interrupt service routine is located. vs<4:0> (intctl<9:5>: cp0 register 12, select 1) 10000 = 512-byte vector spacing 01000 = 256-byte vector spacing 00100 = 128-byte vector spacing 00010 = 64-byte vector spacing 00001 = 32-byte vector spacing 00000 = 0-byte vector spacing voffx<17:1> (offx<17:1>) interrupt vector x address offset bits shadow register sets on pic32mx devices, there was one shadow register set which could be used during interrupt proces sing. which interrupt priority could use the shadow register set was determined by the fsrs- sel field in devcfg3 and ss0 on intcon. on pic32mz ef devices, there are seven shadow register sets, and each priority level can be as signed a shadow register set to use via the prixss<3:0> bits in the priss register. the ss0 bit is also moved to priss<0>. fsrssel<2:0> (devcfg3<18:16>) 111 = assign interrupt priority 7 to a shadow register set 110 = assign interrupt priority 6 to a shadow register set 001 = assign interrupt priority 1 to a shadow register set 000 = all interrupt priorities are assigned to a shadow ? register set prixss<3:0> priss 1xxx = reserved (by default, an interrupt with a priority level of x uses shadow set 0) 0111 = interrupt with a priority level of x uses shadow set 7 0110 = interrupt with a priority level of x uses shadow set 6 0001 = interrupt with a priority level of x uses shadow set 1 0000 = interrupt with a priority level of x uses shadow set 0 ss0 ( intcon<16> ) 1 = single vector is presented with a shadow register set 0 = single vector is not present ed with a shadow register set ss0 ( priss<0> ) 1 = single vector is presented with a shadow register set 0 = single vector is not presented with a shadow register set status pic32mx devices, the vec<5:0> bits show which interrupt is being serviced. on pic32mz ef devices, the sirq<7:0> bits show the irq number of the interrupt last serviced. vec<5:0> (intstat<5:0>) 11111-00000 = the interrupt vector that is presented to the cpu sirq<7:0> (intstat<7:0>) 11111111 - 00000000 = the last interrupt request number serviced by the cpu
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 710 ? 2015-2016 microchip technology inc. a.8 flash programming the pic32mz ef family of devices incorporates a new flash memory technology. applications ported from pic32mx5xx/6xx/7xx devices that take advantage of run-time self programming will need to adjust the flash programming steps to incorporate these changes. table a-9 lists the differences (indicated by bold type) that will affect software migration. table a-9: flash programming differences pic32mx5xx/6xx/7xx feature pic32mz ef feature program flash write protection on pic32mx devices, the program flash write-protect bits are part of the flash configuration words (devcfg0). on pic32mz ef devices, the writ e-protect register is contained separately as the nvmpwp register. it has been expanded to 24 bits, and now represents the address below, which all flash mem- ory is protected. note that the lower 14 bits are forced to zero, so that all memory locations in the page are protected. pwp< 7 :0> ( devcfg0<19:12> ) 11111111 = disabled 11111110 = 0xbd000fff 11111101 = 0xbd001fff 11111100 = 0xbd002fff 11111011 = 0xbd003fff 11111010 = 0xbd004fff 11111001 = 0xbd005fff 11111000 = 0xbd006fff 11110111 = 0xbd007fff 11110110 = 0xbd008fff 11110101 = 0xbd009fff 11110100 = 0xbd00afff 11110011 = 0xbd00bfff 11110010 = 0xbd00cfff 11110001 = 0xbd00dfff 11110000 = 0xbd00efff 11101111 = 0xbd00ffff 01111111 = 0xbd07ffff pwp< 23 :0> ( nvmpwp<23:0> ) physical memory below address 0x1dxxxxxx is write protected, where xxxxxx is specified by pwp<23:0>. when pwp<23:0> has a value of 0 , write protection is disabled for the entire pro- gram flash. if the specified address falls within the page, the entire page and all pages below the current page will be pro- tected. code protection on pic32mx devices, code protec tion is enabled by the cp ( devcfg <28>) bit. on pic32mz ef devices, code protection is enabled by the cp ( devcp0 <28>) bit. boot flash write protection on pic32mx devices, boot flash write protection is enable by the bwp (devcfg<24>) bit and protects the entire boot flash memory. on pic32mz ef devices, boot flash write protection is divided into pages and is enable by the lbwpx and ubwpx bits in the nvmbwp register. low-voltage detect status lvdstat (nvmcon<11>) 1 = low-voltage event is active 0 = low-voltage event is not active the lvdstat bit is not available in pic32mz ef devices.
? 2015-2016 microchip technology inc. ds60001320d-page 711 pic32mz embedded connectivity with floating point unit (ef) family flash programming the op codes for programming the flash memory have been changed to accommodate the new quad-word programming and dual-panel features. the row size has changed to 2 kb (512 iw) from 128 iw. the page size has changed to 16 kb (4k iw) from 4 kb (1k iw). note that the nvmop register is now protected, and requires the wren bit be set to enable modification. nvmop<3:0> (nvmcon<3:0>) 1111 = reserved 0111 = reserved 0110 = no operation 0101 = program flash (pfm) erase operation 0100 = page erase operation 0011 = row program operation 0010 = no operation 0001 = word program operation 0000 = no operation nvmop<3:0> (nvmcon<3:0>) 1111 = reserved 1000 = reserved 0111 = program erase operation 0110 = upper program flash memory erase operation 0101 = lower program flash memory erase operation 0100 = page erase operation 0011 = row program operation 0010 = quad word (128-bit) program operation 0001 = word program operation 0000 = no operation pic32mx devices feature a single nvmdata register for word programming. on pic32mz ef devices, to support quad word programming, the nvmdata register has been expanded to four words. nvmdata nvmdata x , where x = 0 through 3 flash endurance and retention pic32mx devices support flash endurance and retention of up to 20k e/w cycles and 20 years. on pic32mz ef devices, ecc must be enabled to support the same endurance and retention as pic32mx devices. configuration words on pic32mx devices, configur ation words can be programmed with word or row program operation. on pic32mz ef devices, all configuration words must be programmed with quad word or row program operations. configuration words reserved bit on pic32mx devices, the devcfg0<15> bit is reserved and must be programmed to 0 . on pic32mz ef devices, this bit is devsign0<31> . table a-9: flash programming differences (continued) pic32mx5xx/6xx/7xx feature pic32mz ef feature
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 712 ? 2015-2016 microchip technology inc. a.9 other peripherals and features most of the remaining peripherals on pic32mz ef devices act identical to their counterparts on pic32mx - 5xx/6xx/7xx devices. the main differences have to do with handling the increased peripheral bus clock speed and additional clock sources. table a-10 lists the differences (indicated by bold type) that will affect software and hardware migration. table a-10: peripheral differences pic32mx5xx/6xx/7xx feature pic32mz ef feature i 2 c on pic32mx devices, all pins are 5v-tolerant. on pic 32mz ef devices, the i2c4 port uses non-5v tolerant pins, and will have different v ol /v oh specifications. the baud rate generator register has been expanded from 12 bits to 16 bits. i2cxbrg< 11 :0> i2cxbrg< 15 :0> watchdog timer clearing the watchdog timer on pic32mx5xx/6xx/7xx devices required writing a 1 to the wdtclr bit. on pic32mz ef devices, the wdtclr bit has been replaced with the 16-bit wdtclrkey, which must be written with a spe- cific value (0x5743) to clear the watchdog timer. in addition, the wdtspgm (devcfg1<21>) bit is used to control operation of the watchdog timer during flash programming. wdtclr (wdtcon< 0 >) wdtclrkey<15:0> (wdtcon< 31:16 >) rtcc on pic32mx devices, the output of the rtcc pin was selected between the seconds clock or the alarm pulse. on pic32mz ef devices, the rtcc clock is added as an option. rtcsecsel has been renamed rtcoutsel and expanded to two bits. rtcsecsel (rtccon<7>) 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin rtcoutsel<1:0> (rtccon< 8: 7>) 11 = reserved 10 = rtcc clock is presented on the rtcc pin 01 = seconds clock is presented on the rtcc pin 00 = alarm pulse is presented on the rtcc pin when the alarm ? interrupt is triggered on pic32mx devices, the secondary oscillator (s osc ) serves as the input clock for the rtcc module. on pic32mz ef devices, an additional clock source, lprc, is available as a choice for the input clock. rtcclksel<1:0> (rtccon<10:9>) 11 = reserved 10 = reserved 01 = rtcc uses the external 32.768 khz s osc 00 = rtcc uses the internal 32 khz oscillator (lprc)
? 2015-2016 microchip technology inc. ds60001320d-page 713 pic32mz embedded connectivity with floating point unit (ef) family ethernet on pic32mz ef devices, the input clock divider for the ethernet module has expanded options to accommodate the faster peripheral bus clock. clksel<3:0> (emac1mcfg<5:2>) 1000 = sysclk divided by 40 0111 = sysclk divided by 28 0110 = sysclk divided by 20 0101 = sysclk divided by 14 0100 = sysclk divided by 10 0011 = sysclk divided by 8 0010 = sysclk divided by 6 000x = sysclk divided by 4 clksel<3:0> (emac1mcfg<5:2>) 1010 = pbclk5 divided by 50 1001 = pbclk5 divided by 48 1000 = pbclk5 divided by 40 0111 = pbclk5 divided by 28 0110 = pbclk5 divided by 20 0101 = pbclk5 divided by 14 0100 = pbclk5 divided by 10 0011 = pbclk5 divided by 8 0010 = pbclk5 divided by 6 000x = pbclk5 divided by 4 comparator/comparator voltage reference on pic32mx devices, it was possible to select the v ref + pin as the output to the cv refout pin. on pic32mz ef devices, the cv refout pin must come from the resistor network. vrefsel (cvrcon<10>) 1 = cv ref = v ref + 0 = cv ref is generated by the resistor network this bit is not available. on pic32mx devices, the internal voltage reference (iv ref ) could be chosen by the bgsel<1:0> bits. on pic32mz ef devices, iv ref is fixed and cannot be changed. bgsel<1:0> (cvrcon<9:8>) 11 = iv ref = v ref + 10 = reserved 01 = iv ref = 0.6v (nominal, default) 00 = iv ref = 1.2v (nominal) these bits are not available. change notification on pic32mx devices, change notification is controlled by the cncon, cnen, and cnpue registers. on pic32mz ef devices, change notification functionality has been relocated into each i/o port and is controlled by the cnpux, cnpdx, cnconx, cnenx, and cnstatx registers. system bus on pic32mx devices, the system bus registers can be used to configure ram memory for data and program memory partitions, cacheability of flash memory, and ram wait states. these reg- isters are: bmxcon, bmxdkpba, bmxdudba, bmxdupba, bmxpupba, bmxdrmsz, bmxpfmsz, and bmxbootsz. on pic32mz ef devices, a new system bus is utilized that sup- ports using ram memory for program or data without the need for special configuration. theref ore, no special registers are associated with the system bus to configure these features. on pic32mx devices, various arbi tration modes are used as ini- tiators on the system bus. these modes can be selected by the bmxarb<2:0> (bmxcon<2:0>) bits. on pic32mz ef devices, a new arbitration scheme has been implemented on the system bus. all initiators use the least recently serviced (lrs) scheme, with the exception of the dma, cpu, and the flash controller. the flash controller always has high priority over lrs initiators. the dma and cpu (when servicing an interrupt) can be selected to have lrs or high priority using the dmapri (cfgcon<25>) and cpupri (cfgcon<24>) bits. table a-10: peripheral differences (continued) pic32mx5xx/6xx/7xx feature pic32mz ef feature
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 714 ? 2015-2016 microchip technology inc. a.10 package differences in general, pic32mz ef devices are mostly pin com - patible with pic32mx5xx/6xx/7xx devices; how - ever, some pins are not. in particular, the v dd and v ss pins have been added and moved to different pins. in addition, i/o functions that were on fixed pins now will largely be on remappable pins. table a-11: package differences pic32mx5xx/6xx/7xx feature pic32mz ef feature v cap pin on pic32mx devices, an external capacitor is required between a v cap pin and gnd, which provides a filtering capacitor for the internal voltage regulator. on pic32mz ef devices, this requirement has been removed. a low-esr capacitor (typically 10 f) is required on the v cap pin. no v cap pin. v dd and v ss pins there are more v dd pins on pic32mz ef devices, and many are located on different pins. v dd on 64-pin packages: 10, 26, 38, 57 v dd on 100-pin packages: 2, 16, 37, 46, 62, 86 v dd on 64-pin packages: 8, 26, 39, 54, 60 v dd on 100-pin packages: 14, 37, 46, 62, 74, 83, 93 there are more v ss pins on pic32mz ef devices, and many are located on different pins. v ss on 64-pin packages: 9, 25, 41 v ss on 100-pin packages: 15, 36, 45, 65, 75 v ss on 64-pin packages: 7, 25, 35, 40, 55, 59 v ss on 100-pin packages: 13, 36, 45, 53, 63, 75, 84, 92 pps i/o pins peripheral functions on pic32mz ef devices are now routed through a pps module, which routes the signals to the desired pins. when migrating software, it is necessary to initialize the pps i/o functions in order to get the signal to and from the cor- rect pin. all peripheral functions are fixed as to what pin upon which they operate. pps functionality for the following peripherals: can uart spi (except sck) input capture output compare external interrupt (except int0) timer clocks (except timer1) reference clocks (except refclk2)
? 2015-2016 microchip technology inc. ds60001320d-page 715 pic32mz embedded connectivity with floating point unit (ef) family appendix b: migrating from pic32mz ec to pic32mz ef this appendix provides an overview of considerations for migrating from pic32mz ec devices to the pic32mz ef family of devices. the code developed for pic32mz ec devices can be ported to pic32mz ef devices after making the appropriate changes outlined in the following sections. the pic32mz ef devices are similar to pic32mz ec devices, with many feature improvements and new capabilities. b.1 oscillator and pll configuration a number of new features have been added to the oscillator and pll to enhance their ability to work with crystals and to change frequencies. table b-1 summarizes the differences (indicated by bold type) between the family differences for the oscillator. table b-1: oscillator differences pic32mz ec feature pic32mz ef feature primary oscillator crystal power on pic32mz ec devices, the crystal hs p osc mode is only functional with crystals that have certain characteristics, such as very low esr. on pic32mz ef devices, some devcfg0 bits have been added to allow control over the strength of the oscillator and to add a kick start boost. poscboost (devcfg0<21>) 1 = boost the kick start of the oscillator 0 = normal start of the oscillator poscgain<1:0> (devcfg0<20:19>) 11 = 2x gain setting 10 = 1.5x gain setting 01 = 0.5x gain setting 00 = 1x gain setting note that the default for poscgain (2x gain setting) may over- drive crystals and shorten their life. it is the responsibility of the designer to ensure crystals are operated properly. secondary oscillator crystal power on pic32mz ec devices, the secondary oscillator (s osc ) is not functional. on pic32mz ef devices, the secondary oscillator is now functional, and provides similar strength and kick start boost features as the p osc . soscboost (devcfg0<18>) 1 = boost the kick start of the oscillator 0 = normal start of the oscillator soscgain<1:0> (devcfg0<17:16>) 11 = 2x gain setting 10 = 1.5x gain setting 01 = 0.5x gain setting 00 = 1x gain setting note that the default for soscgain (2x gain setting) may over- drive crystals and shorten their life. it is the responsibility of the designer to ensure crystals are operated properly. clock status bits on pic32mz ec devices, the soscrdy bit (osccon<22>) indicates when the secondary oscillator is ready. there are no indications of other oscillator status. a new register, clkstat, has been added, which includes the soscrdy bit (clkstat<4>). in addition, new status bits are available: lprcrdy (clkstat<5>) poscrdy (clkstat<2>) divspllrdy (clkstat<1>) frcrdy (clkstat<0>) clock switching on pic32mz ec devices, clock switches occur as soon as the switch command is issued. also, the only clock sources that can be divided are the output of the pll, and the frc. to reduce power spikes during clock switches, pic32mz ef devices add a clock slewing feature, so that clock switches can be controlled in their rate and size. the slewcon register controls this feature. the slewcon register also features a sysclk divider, so that all of the possible clock sources may be divided further as needed.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 716 ? 2015-2016 microchip technology inc. b.2 analog-to-digital converter (adc) the pic32mz ec family features a pipelined adc module, while the pic32mz ef family of devices has an entirely new 12-bit high-speed sar adc module. nearly all registers in this new adc module differ from the registers in pic32mz ec devices. due to this differ - ence, code will not port from pic32mz ec devices to pic32mz ef devices. table b-2 lists some of the differ - ences in registers to note to adapt code as quickly as possible. table b-2: adc differences pic32mz ec feature pic32mz ef feature clock selection and operating frequency (t ad ) on pic32mz ec devices, there ar e three possible sources of the adc clock: frc, refclko3, and sysclk. on pic32mz ef devices, there are four sources for the adc clock. in addition to the ones for pic32mz ec, pbclk4 is added as a source. also, the clock source selection is in a different register. adcsel<1:0> (ad1con1<9:8>) 11 = frc 10 = refclko3 01 = sysclk 00 = reserved adcsel<1:0> (adccon3<31:30>) 11 = frc 10 = refclko3 01 = sysclk 00 = pbclk4 scan trigger sources on pic32mz ec devices, there ar e 10 available trigger sources for starting adc sampling and conversion. on pic32mz ef devices, two new sources have been added. one is a shared trigger source (strig). the other is a global level software trigger (glswtrg). with the glswtrg, the conversions continue until the bit is cleared in software. strgsrc<4:0> (ad1con1<26:22>) 11111 = reserved 01101 = reserved 01100 = comparator 2 cout 01011 = comparator 1 cout 01010 = ocmp5 01001 = ocmp3 01000 = ocmp1 00111 = tmr5 match 00110 = tmr3 match 00101 = tmr1 match 00100 = int0 00011 = reserved 00010 = reserved 00001 = global software trigger (gswtrg) 00000 = no trigger trgsrc<4:0> (adctrgx) 11111 = reserved 01101 = reserved 01100 = comparator 2 cout 01011 = comparator 1 cout 01010 = ocmp5 01001 = ocmp3 01000 = ocmp1 00111 = tmr5 match 00110 = tmr3 match 00101 = tmr1 match 00100 = int0 00011 = strig 00010 = global level software trigger (glswtrg) 00001 = global software trigger (gswtrg) 00000 = no trigger debug mode on pic32mz ec devices, the adc module continues operating when stopping on a breakpoint during debugging. on pic32mz ef devices, the adc module will stop during debugging when stopping on a breakpoint. electrical specifications and timing requirements refer to the electrical characteristics chapter in the pic32mz ec data sheet for a dc module specifications and timing requirements. on pic32mz ef devices, the adc module sampling and conversion time and other specif ications have changed. refer to 37.0 electrical characteristics for more information. adc calibration pic32mz ec devices require calibration values be copied into the ad1calx registers before turning on the adc. these values come from the devadcx registers. pic32mz ef devices also require adc calibration values, but the destination registers are named adcxcal.
? 2015-2016 microchip technology inc. ds60001320d-page 717 pic32mz embedded connectivity with floating point unit (ef) family b.3 cpu the cpu in pic32mz ec devices is the microaptiv? mpu architecture. the cpu in the pic32mz ef devices is the series 5 warrior m-class m5150 mpu architecture. most pic32mz ef m-class core features are identical to the microaptiv? core in pic32mz ec devices. the main differences are that in pic32mz ef devices, a floating-point unit (fpu) is included for improved math performance, and pc sampling for performance measurement. b.4 system bus the system bus on pic32mz ef devices is similar to the system bus on pic32mz ec devices. there are two key differences listed in tab le b-3 . b.5 flash controller the flash controller on pic32mz ef devices adds the ability both to control boot flash aliasing, and for lock - ing the current swap settings. tab le b-4 lists theses differences. table b-3: system bus differences pic32mz ec feature pic32mz ef feature permission groups during nmi on pic32mz ec devices, the permission group in which the cpu is part of is lost during nmi handling, and must be manually restored. on pic32mz ef devices, the prior permission group is preserved, and is restored when the cpu returns from the nmi handler. dma access the dma can access the peripheral registers on peripheral bus 1. on pic32mz ef devices, the dma no longer has access to registers on peripheral bus 1. refer to table 4-4 for details on which peripherals are now excluded. table b-4: flash controller differences pic32mz ec feature pic32mz ef feature boot flash aliasing on pic32mz ec devices, boot flash aliasing is done through the devseq0 register, but no further changes are possible without rebooting the processor. on pic32mz ef devices, the initial boot flash aliasing is determined by the devseq3 register, but the bfswap bit (nvmcon<6>) reflects the state of the aliasing, and can be modified to change it during run-time. bfswap (nvmcon<6>) 1 = boot flash bank 2 is mapped to the lower boot alias, and boot flash bank 1 is mapped to the upper boot alias 0 = boot flash bank 1 is mapped to the lower boot alias, and boot flash bank 2 is mapped to the upper boot alias pfm and bfm swap locking on pic32mz ec devices, the swapping of pfm is always available. on pic32mz ef devices, a new control, swaplock<1:0> (nvmcon2<7:6>) allows the locking of pfswap and bfswap bits, and can restrict any further changes. swaplock<1:0> (nvmcon2<7:6>) 11 = pfswap and bfswap are not writable and swaplock is not writable 10 = pfswap and bfswap are not writable and swaplock is writable 01 = pfswap and bfswap are not writable and swaplock is writable 00 = pfswap and bfswap are writable and swaplock is ? writable
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 718 ? 2015-2016 microchip technology inc. b.6 resets on pic32mz ef devices, the reset module adds eight bits to the nmicnt field to make the time-out period before device reset longer, as described in table b-5 . table b-5: resets differences b.7 usb on pic32mz ef devices, a new usbcrcon register has been added to assist in controlling the reset of the usb module, and triggering interrupts based on vbus voltage levels. this register also overcomes an errata on pic32mz ec devices that requires a three second start-up on the usb module. b.8 i/o ports on pic32mz ef devices, many of the i/o pins now feature slew rate control bits to control how fast the pin makes a low-to-high or high-to-low transition. the change notification feature has also been enhanced to allow detection of level events in addition to edge detection. however, the sidl bit is not present in the cnconx registers on pic32mz ef devices, as it is on pic32mz ec devices. b.9 watchdog timer pic32mz ef devices use a new watchdog timer, although the overall control through the devcfgx words remains identical to that of pic32mz ec devices. tab l e b-6 lists two more changes, as well. table b-6: watchdog timer differences pic32mz ec feature pic32mz ef feature countdown to reset during nmis on pic32mz ec devices, the nmicnt<7:0> field is eight bits long, giving a maximum of 256 instructions before the device reset. on pic32mz ef devices, the nmicnt<15:0> field is now 16 bits long, giving a longer period of time (up to 65,536 instructions) prior to a device reset. pic32mz ec feature pic32mz ef feature watchdog timer postscaler on pic32mz ec devices, the swdtps<4:0> bits (wdtcon<6:2>) reflect the postscaler setting for the watchdog timer. on pic32mz ef devices, the field has been changed to the rundiv<4:0> bits (wdtcon<12:8>). watchdog windowed mode on pic32mz ec devices, wdtwinen is at bit position 1 (wdtcon<1>). on pic32mz ef devices, wdtwinen is now at bit position 0 (wdtcon<0>).
? 2015-2016 microchip technology inc. ds60001320d-page 719 pic32mz embedded connectivity with floating point unit (ef) family b.10 serial quad interface (sqi) on pic32mz ef devices, the sqi module has been updated with the following features: fifos can be reset through the confiforst (sqi1cfg<19>), rxfiforst (sqi1cfg<18>), and txfiforst (sqi1cfg<17>) bits in register 20-3 a new flash status check is available, which will allow the sqi to automatically query the status of the external device during write/erase operations without software intervention. see the scheck bit (sqi1con<24>) and the sqi1memstat register ( register 20-4 and register 20-24 , respectively). the sqi clock divider bits have been expanded, and can use an undivided clock. see the clkdiv<10:0> bits (sqi1clkcon<18:8>) in register 20-5 . a new dma bus error interrupt is available through the dmaeie (sqi1inten<11>), dmaeif (sqi1intstat<11>), and dmaeise (sqi1intsigen<11>) bits in register 20-8 , register 20-9 , and register 20-22 , respectively the sqi1stat2 register (see register 20-13 ) has two new fields: - cmdstat<1:0> (sqi1stat2<17:16>) indicates the current command status - conavail<4:0> (sqi1stat<11:8>) indicates how many spaces are available in the control fifo. the tap controller within the sqi can be configured for various timing requirements via the sqi1tapcon register ( register 20-23 ) two new xip mode registers (sqi1xcon3 and sqi1xcon4) have been added for additional command sequencing (see register 20-25 and register 20-26 , respectively) refer to 20.0 serial quad interface (sqi) and section 46. serial quad interface (sqi) (ds60001128) for more information. b.11 pmp on pic32mz ef devices, the pmp features the ability to buffer reads and writes in both directions, and can read and write from different addresses. refer to 23.0 parallel master port (pmp) and section 43. parallel master port (ds60001346) for information.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 720 ? 2015-2016 microchip technology inc. b.12 crypto engine table b-7 lists the changes available for the crypto engine. table b-7: crypto differences b.13 device configuration and control a number of enhancements have been added to the pic32mz ef devices that allow greater control and flexibility on the device. some bit fields have also changed location. ta b l e b-8 lists these changes. table b-8: device configurat ion and control differences pic32mz ec feature pic32mz ef feature output data format on pic32mz ec devices, the output of the crypto engine is always in big-endian format, usually requiring a software (or dma) solution to put the data into little-endian format, which the core handles natively. on pic32mz ef devices, the swapoen bit (cecon<7>) has been added to control output byte swapping. this bit, when enabled, will byte-swap the output. pic32mz ec feature pic32mz ef feature mclr pin configuration on pic32mz ec devices, the mclr pin always generate a system reset. on pic32mz ef devices, the mclr pin can now be configured to generate either a system reset or an emulated por reset. smclr (devcfg0<15>) 1 = mclr pin generates a normal system reset 0 = mclr pin generates an emulated por reset i/o analog charge pump low v dd environments cause attenuation of analog inputs. a new bit enables an i/o charge pump, which improves analog performance when operating at lower v dd . ioancpen (cfgcon<7>) 1 = charge pump is enabled 0 = charge pump is disabled ebi ready pin control the ebirdy control bits have been moved. ebirdyinv<3:1> (cfgebic<30:28>) ebirdyen<3:1> (cfgebic<26:24>) ebirdyinv<3:1> (cfgebic<31:29>) ebirdyen<3:1> (cfgebic<27:25>) boot flash sequence control on pic32mz ec devices, the boot flash sequence (specifying which boot memory was mapped to the lower boot alias) was determined with the bfxseq0 registers. on pic32mz ef devices, the boot flash sequence has been moved to the bfxseq3 register.
? 2015-2016 microchip technology inc. ds60001320d-page 721 pic32mz embedded connectivity with floating point unit (ef) family appendix c: revision history revision a (january 2015) this is the initial released version of the document. revision b (july 2015) the document status was updated from advance information to preliminary. the revision includes the following major changes, which are referenced by their respective chapter in table c-1 . in addition, minor updates to text and formatting were incorporated throughout the document. table c-1: major section updates section name update description 32-bit mcus (up to 2 mb live- update flash and 512 kb sram) with fpu, audio and graphics interfaces, hs usb, ethernet, and advanced analog the operating conditions were updated to: 2.1v to 3.6v. 4.0 memory organization legal information on the system bus was added (see 4.2 system bus arbitration ). 5.0 flash program memory the bootswap bit in the nvmcon register was changed to: bfswap (see register 5-1). 6.0 resets the nvmlta bit was removed from the rcon register (see register 6-1). the gnmi bit was added to the rnmicon register (see register 6-3). 7.0 cpu exceptions and interrupt controller the adc fifo data ready interrupt, irq 45, was added (see table 7-2). adc fifo bits were added, and note 7 regarding devices without a crypto module was added to the interrupt register map (see table 7-3). the nmikey<7:0> bits were added to the intcon register (see register 7-1). 8.0 oscillator configuration the spllrdy bit was removed and the splldivrdy bit was added to the clkstat register (see register 8-8 11.0 hi-speed usb with on-the- go (otg) the vbusie and vbusif bits were changed to: vbuserrie and vbuserrif, respectively in the usbcsr2 register (see register 11-3). 15.0 deadman timer (dmt) the por values were updated for the pscnt<4:0> bits in the post status configure dmt count status register (see register 15-6). the por values were updated for the psintv<2:0> bits in the post status configure dmt interval status register (see register 15-7). 16.0 watchdog timer (wdt) the wdtcon register was updated (see register 16-1). 23.0 parallel master port (pmp) the pmdout, pmdin, and pmrdin registers were added (see register 23-4, register 23-4, and register 23-10). the pmaddr, pmwaddr, and pmraddr registers were updated (see register 23-3, register 23-8, and register 23-9). the pmrdata register was removed. 24.0 external bus interface (ebi) reset values for the ebimsk2, ebimsk3, ebismt0-ebismt2, and ebiftrpd registers were updated in the ebi register map (see table 24-2). por value changes were implemented to the ebi static memory timing register (see register 24-3).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 722 ? 2015-2016 microchip technology inc. 27.0 random number generator (rng) the trngmode bit was added to the rngcon register (see register 27-2). 28.0 12-bit high-speed successive approximation register (sar) analog-to-digital converter (adc) the s&h block diagram was updated (see figure 28-2). the registers, adctrg4 through adctrg8, were removed. the bit value definitions for the adcsel<1:0> and conclkdiv<5:0> bits in the adccon3 register were updated (see register 28-3). the bit names in the adc status registers (register 28-12 and register 28-13) were updated to match the names in the sfr summary table. the adctrgsns register was updated (see register 28-26). the por values were changed in the adc system configuration registers (see register 28-34 and register 28-35). 34.0 special features the fdbgwp bit was removed from the devcfg0/adevcfg0 registers (se e register 34-3). 37.0 electrical characteristics v-temp (-40c ? t a ? +105c) information was removed from all tables. the operating conditions voltage range was updated in the absolute maximum ratings and in all tables to: 2.1v to 3.6v. notes on maximum value operating conditions were added to the operating, idle, and power-down current tables (see table 37-6, table 37-7, and table 37-8, respectively). the conditions for system timing requirement parameters os55a and os55b were updated (see table 37-18). the internal frc accuracy specifications were updated (see table 37-20) . the internal lprc accuracy specifications were updated (see table 37-21 ). the adc module specifications were updated (see table 37-38). the analog-to-digital conversion timing requirements were updated (see table 37-39). appendix b: migrating from pic32mz ec to pic32mz ef this appendix was added, which provides an overview of considerations for migrating from pic32mz ec devices to the pic32mz ef family of devices. product identification system v-temp (-40c ? t a ? +105c) information was removed. table c-1: major section updates (continued) section name update description
? 2015-2016 microchip technology inc. ds60001320d-page 723 pic32mz embedded connectivity with floating point unit (ef) family revision c (march 2016) in this revision, the preliminary status was removed from the document footer. the revision also includes the following major changes, which are referenced by their respective chapter in table c-2 . in addition, minor updates to text and formatting were incorporated throughout the document. table c-2: major section updates section name update description 2.0 guidelines for getting started with 32-bit microcontrollers 2.9.1.3 emi/emc/eft (iec 61000-4-4 and iec 61000-4-2) suppression considerations and figure 2-5 were updated. 4.0 memory organization the names of the boot flash words were updated from bfxseq0 to bfxseq3 (see 4.1.1 boot flash sequence and configuration spaces ). the abfxseqx registers were removed from the boot flash sequence and configuration tables (see table 4-2 and table 4-3). 7.0 cpu exceptions and interrupt controller the cache error exception type was removed from the mips32 m-class microprocessor core exception types (see table 7-1). 8.0 oscillator configuration the pllodiv<2:0> bit value settings were updated in the spllcon register (see register 8-3). 12.0 i/o ports the sidl bit was removed from the cnconx registers (see table 12-4 through tab l e 12-21 and register 12-3). 20.0 serial quad interface (sqi) the following bits were removed from the sqi1xcon1 register (see table 20-1 and register 20-1): ddrdata, ddrdummy, ddrmode, ddraddr, and ddrcmd. the ddrmode bit was removed from the sqi1con register (see table 20-1 and register 20-4). 28.0 12-bit high-speed successive approximation register (sar) analog-to-digital converter (adc) a note was added to the selres<1:0> bits in the adccon1 and adcxtime registers (see register 28-1 and register 28-27). the adcid<2:0 bit values were updated in the adcfstat register (see register 28-22). 34.0 special features the bit value definitions for the poscgain<1:0> and soscgain<1:0> bits were updated (see register 34-3). the device adc calibration word (devadcx) register was added (see tab l e 34-5 and register 34-13).
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 724 ? 2015-2016 microchip technology inc. 37.0 electrical characteristics the dc characteristics: operating current (i dd ) and note 6 were updated (see tab l e 37-6). the dc characteristics: idle current (i idle ) and note 4 were updated (see tab l e 37-7). parameter dc40m and note 5 in the dc characteristics: power-down current (i pd ) were updated (see table 37-8). parameter do50 (cosco) was removed from the capacitive loading requirements on output pins (see table 37-16). the internal frc accuracy and internal lprc conditions were updated for 125oc (see table 37-20 and table 37-21). parameter sp15 and note 5 of the spix module master mode timing requirements were updated (see table 37-30 and table 37-31). the temperature sensor specifications were updated (see table 37-41). 38.0 extended temperature electrical characteristics new chapter for extended temperature devices was added. 39.0 ac and dc characteristics graphs the typical temperature sensor voltage graph was updated (see figure 39-7). 40.0 packaging information the package drawings and land pattern for the 64-lead plastic quad flat, no lead package (mr) were updated. appendix a: migrating from pic32mx5xx/6xx/7xx to pic32mz ef the primary oscillator configuration section in the oscillator configuration differences was updated (see table a-1). appendix b: migrating from pic32mz ec to pic32mz ef boot flashing aliasing was updated for pic32mz ef devices (see table b-4). table c-2: major section updates (continued) section name update description
? 2015-2016 microchip technology inc. ds60001320d-page 725 pic32mz embedded connectivity with floating point unit (ef) family revision d (july 2016) this revision includes the following major changes, which are referenced by their respective chapter in table c-3 . in addition, minor updates to text and formatting were incorporated throughout the document. table c-3: major section updates section name update description 32-bit mcus (up to 2 mb live- update flash and 512 kb sram) with fpu, audio and graphics interfaces, hs usb, ethernet, and advanced analog updated the operating conditions and core mhz values. the xfbga package was renamed to tfbga. 20.0 serial quad interface (sqi) the clkdiv<9:0> bits in the sqi1clkcon register were updated (see register 20-5 ). the thres<4:0> bits in the sqi1thr register were updated (see register 20-21 ). 37.0 electrical characteristics the program flash memory wait states were updated (see table 37-13 ). the minimum value for system time requirements parameter os51 (when the usb module is enabled) was updated (see table 37-18 ). 39.0 252 mhz electrical characteristics this chapter was added. appendix a: migrating from pic32mx5xx/6xx/7xx to pic32mz ef the new adc module reference was updated (see a.2 analog-to-digital converter (adc) ). adc calibration was added to b.2 analog-to-digital converter (adc) appendix b: migrating from pic32mz ec to pic32mz ef the device configuration and control differences ( tab l e b - 8 ) were updated to include the boot flash sequence. b.10 serial quad interface (sqi) was updated. product identification system the speed category was added.
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 726 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds60001320d-page 727 pic32mz embedded connectivity with floating point unit (ef) family index a ac characteristics ............................................ 624, 667, 673 adc specifications ................................................... 650 analog-to-digital conversion requirements............. 651 ejtag timing requirements ................................... 662 ethernet .................................................................... 658 internal bfrc accuracy ........................................... 627 internal frc accuracy.............................................. 627 internal lprc accuracy............................................ 627 parallel master port read requirements ................. 655 parallel master port write ......................................... 656 parallel master port write requirements.................. 656 parallel slave port requirements ............................. 654 pll clock timing...................................... 626, 667, 673 usb otg electrical specifications ........................... 657 assembler mpasm assembler................................................... 608 b block diagrams comparator i/o operating modes............................. 567 comparator voltage reference ................................ 571 cpu ............................................................................ 44 crypto engine ........................................................... 401 dma .......................................................................... 173 ebi system ............................................................... 383 ethernet controller.................................................... 5 23 i2c ............................................................................ 354 input capture .............................................. .............. 305 interrupt controller .................................................... 1 15 jtag programming, debugging and trace ports .... 603 output compare module........................................... 309 pic32 can module.............................................. ..... 485 pmp pinout and connections to external devices ... 369 prefetch module............................................... ......... 169 random number generator (rng) .......................... 421 rtcc ........................................................................ 391 serial quad interface (sqi) ...................................... 325 spi/i2s module ........................................... .............. 315 system reset............................................................ 109 timer1....................................................................... 283 timer2-timer9 (16-bit).............................................. 287 typical multiplexed port structure ............................ 247 uart ........................................................................ 361 wdt.......................................................................... 301 brown-out reset (bor) and on-chip voltage regulator................................ 603 c c compilers mplab...................................................................... 608 comparator specifications............................................................ 623 comparator module ............................................ .............. 567 comparator voltage reference (cvref ............................. 571 configuration bits.............................................................. 58 1 configuring analog port pins ............................................ 248 controller area network (can)......................................... 485 cpu architecture overview................................................. 45 coprocessor 0 registers ............................................ 46 core exception types............................................... 116 ejtag debug support............................................ ... 50 power management .............................................. ..... 49 cpu module ............................................... ........................ 43 crypto buffer descriptors..................................................... 412 format of bd_ctrl................................................. 413 format of bd_dstaddr......................................... 414 format of bd_enc_off ......................................... 415 format of bd_msg_len ......................................... 415 format of bd_nxtaddr......................................... 414 format of bd_saddr.............................................. 413 format of bd_srcaddr ........................................ 414 format of bd_updptr ........................................... 415 format of sa_ctrl ................................................. 419 security association structure.................................. 416 crypto engine ................................................................... 401 customer change notification service............................. 733 customer notification service .......................................... 733 customer support............................................... .............. 733 d dc characteristics............................................ 612, 664, 670 i/o pin input specifications .............................. 617, 618 i/o pin output specifications.................................... 619 idle current (i idle ) .................................... 615, 665, 671 power-down current (i pd )................................ 616, 666 program flash memory wait states................. 622, 672 program memory...................................................... 622 temperature and voltage specifications.................. 613 development support....................................................... 607 direct memory access (dma) controller.......................... 173 e electrical characteristics .................................. 611, 663, 669 errata .................................................................................. 12 ethernet controller...................................................... ...... 523 external bus interface (ebi) ............................................. 383 external clock timer1 timing requirements ................................... 633 timer2-timer9 timing requirements....................... 634 timing requirements ............................................... 625 f flash program memory ...................................................... 99 g getting started ................................................................... 37 h hi-speed usb on-the-go (otg).................................... 197 i i/o ports ........................................................................... 247 parallel i/o (pio) ...................................................... 248 write/read timing.......................................... .......... 248 input change notification ...................................... ........... 248 instruction set................................................................... 605 inter-integrated circuit (i2c) ............................................. 353 internet address ............................................................... 733 interrupt controller irg, vector and bit location .................................... 118
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 728 ? 2015-2016 microchip technology inc. m memory maps devices with 1024 kb program memory and 256 kb ram .................................................................... 63 devices with 1024 kb program memory and 512 kb ram .................................................................... 64 devices with 2048 kb program memory .................... 65 devices with 512 kb program memory ...................... 62 memory organization............................................ .............. 61 layout ......................................................................... 61 microchip internet web site .............................................. 733 mplab assembler, linker, librarian ................................ 608 mplab icd 3 in-circuit debugger system....................... 609 mplab pm3 device programmer..................................... 609 mplab real ice in-circuit emulator system................. 609 mplab x integrated development environment software..... 607 mplink object linker/mplib object librarian ................ 608 o oscillator configuration..................................................... 153 output compare................................................................ 309 p packaging ......................................................................... 677 details ....................................................................... 679 marking ..................................................................... 677 parallel master port (pmp) ............................................... 369 pickit 3 in-circuit debugger/programmer ........................ 609 pinout i/o descriptions adc ............................................................................ 16 alternate ethernet mii ................................................. 33 alternate ethernet rmii .............................................. 33 can ............................................................................ 31 comparators and cvref ........................................... 27 ebi .............................................................................. 29 ethernet mii ................................................................ 32 ethernet rmii .............................................................. 32 external interrupts....................................................... 19 i2c .............................................................................. 27 input capture .............................................. ................ 18 jtag, trace, and programming/debugging............... 35 oscillator ..................................................................... 18 output compare ......................................................... 19 pmp ............................................................................ 28 ports............................................................................ 20 power, ground, and voltage reference ..................... 34 spi .............................................................................. 26 sqi .............................................................................. 34 timers ......................................................................... 24 uart .......................................................................... 25 usb............................................................................. 31 power-on reset (por) and on-chip voltage regulator ................................ 603 power-saving features..................................................... 575 with cpu running................................................. .... 575 prefetch module ............................................... ................. 169 r random number generator (rng) .................................. 421 real-time clock and calendar (rtcc)............................ 391 register map adevcfg (alternate device configuration word sum- mary)................................................................. 583 can1 register summary.......................................... 486 can2 register summary ......................................... 488 comparator............................................................... 568 comparator voltage reference ................................ 572 deadman timer ............................................... ......... 294 devcfg (device configuration word summary) .... 582 device adc calibration summary............................ 585 device id, revision, and configuration summary.... 584 device serial number summary .............................. 584 dma channel 0-7 ................................................ ..... 175 dma crc ................................................................. 174 dma global ............................................... ............... 174 ebi............................................................................ 384 ethernet controller register summary..................... 525 flash controller ........................................................ 100 i2c1 through i2c5 ......................................... .......... 355 input capture 1-9...................................................... 307 interrupt .................................................................... 126 oscillator configuration .......... .................................. 156 output compare1-9 .................................................. 311 parallel master port .................................................. 370 peripheral pin select input ....................................... 274 peripheral pin select output .................................... 278 porta ..................................................................... 256 portb ..................................................................... 257 portc ................................................ ............. 258, 259 portd ................................................ ..... 260, 261, 262 porte ................................................ ............. 263, 264 portf ................................................ ............. 265, 266 portg ..................................................................... 268 porth ................................................ ............. 269, 270 portj ................................................ .............. 271, 272 portk ..................................................................... 273 prefetch .................................................................... 170 resets ...................................................................... 110 rtcc........................................................................ 392 spi1 through spi6 ........................................ ............ 316 system bus ................................................................ 76 system bus target 0 .................................................. 76 system bus target 1 .................................................. 77 system bus target 10 ................................................ 87 system bus target 11 ................................................ 88 system bus target 12 ................................................ 89 system bus target 13 ................................................ 90 system bus target 2 .................................................. 79 system bus target 3 .................................................. 80 system bus target 4 .................................................. 81 system bus target 5 .................................................. 82 system bus target 6 .................................................. 83 system bus target 7 .................................................. 84 system bus target 8 .................................................. 85 system bus target 9 .................................................. 86 timer1 ...................................................................... 284 timer1-timer9 .......................................................... 289 uart1-6................................................................... 362 usb .................................................. ................ 199, 205 watchdog timer ............................................ ........... 302 registers [ pin name ]r (peripheral pin select input) ................ 281 adcancon (adc analog warm-up control register) . 480 adcbase (adc base) ............................................ 473 adccmp1con (adc digital comparator 1 control register) ........................................................... 467 adccmpenx (adc digital comparator x enable reg- ister (x = 1 through 6))..................................... 460
? 2015-2016 microchip technology inc. ds60001320d-page 729 pic32mz embedded connectivity with floating point unit (ef) family adccmpx (adc digital comparator x limit value reg- ister (x = 1 through 6))..................................... 461 adccmpxcon (adc digital comparator x control register (x = 1 through 6)) .............................. 469 adccon1 (adc control register 1) ....................... 437 adccon2 (adc control register 2) ....................... 440 adccon3 (adc control register 3) ....................... 442 adccss1 (adc common scan select register 1). 457 adccss2 (adc common scan select register 2). 458 adcdatax (adc output data register (x = 0 through 44)) ................................................................... 474 adcdstat1 (adc data ready status register 1) . 459 adcdstat2 (adc data ready status register 2) . 459 adceien1 (adc early interrupt enable register 1) 477 adceien2 (adc early interrupt enable register 2) 477 adceistat2 (adc early interrupt status register 2)... 479 adcfltrx (adc digital filter x register (x = 1 through 6)) ............................................... ......... 462 adcgirqen1 (adc interrupt enable register 1) ... 456 adcimcon1 (adc input mode control register 1) 447 adcimcon2 (adc input mode control register 2) 450 adcimcon3 (adc input mode control register 3) 453 adcirqen2 (adc interrupt enable register 2) ...... 456 adcsyscfg1 (adc system configuration register 1) 483 adcsyscfg2 (adc system configuration register 2) 483 adctrg1 (adc trigger source 1 register)............ 464 adctrg2 (adc trigger source 2 register)............ 465 adctrg3 (adc trigger source 3 register)............ 466 adctrgmode (adc triggering mode for dedicated adc) ................................................................. 445 adctrgsns (adc trigger level/edge sensitivity) 475 adcxcfg (adcx configuration register x (x = 1 through 6)) ............................................... ......... 482 adcxtime (dedicated adcx timing register x (x = 0 through 4)) ............................................... ......... 476 alrmtime (alarm time value) ............................... 399 bfxseq3/abfxseq3 (boot flash x sequence word 3 register .............................................................. 70 cebdaddr (crypto engine buffer descriptor)........ 405 cebdpaddr (crypto engine buffer descriptor proces- sor).................................................................... 405 cecon (crypto engine control) .............................. 404 cehdlen (crypto engine header length) .............. 411 ceinten (crypto engine interrupt enable) ............. 409 ceintsrc (crypto engine interrupt source)........... 408 cepollcon (crypto engine poll control) .............. 410 cestat (crypto engine status) .............................. 406 cetrllen (crypto engine trailer length) .............. 411 cever (crypto engine revision, version, and id).. 403 cfgebia (external bus interface address pin configu- ration)................................................................ 597 cfgebic (external bus interface control pin configura- tion) ................................................................... 598 cfgpg (permission group configuration)............... 600 cicfg (can baud rate configuration).................... 492 cicon (can module control) .................................. 490 cififoba (can message buffer base address) ..... 517 cififocin (can module message index register n (n = 0-31)) ............................................................. 522 cififoconn (can fifo control register n (n = 0- 31)) ................................................................... 518 cififointn (can fifo interrupt register n (n = 0- 31)) ................................................................... 520 cififouan (can fifo user address register n (n = 0-31)) ................................................................ 522 cifltcon0 (can filter control register 0)............ 500 cifltcon1 (can filter control register 1)............ 502 cifltcon2 (can filter control register 2)............ 504 cifltcon3 (can filter control register 3)............ 506 cifltcon4 (can filter control register 4)............ 508 cifltcon5 (can filter control register 5)............ 510 cifltcon6 (can filter control register 6)............ 512 cifltcon7 (can filter control register 7)............ 514 cifstat (can fifo status) ................................... 497 cirxfn (can acceptance filter n register 7 (n = 0- 31)) ................................................................... 516 cirxmn (can acceptance filter mask n register (n = 0-3)) .................................................................. 499 cirxovf (can receive fifo overflow status) ..... 498 citmr (can timer) ................................................. 498 citrec (can transmit/receive error count)......... 497 civec (can interrupt code).................................... 496 cmstat (comparator control register) ................. 570 cmxcon (comparator control) ............................... 569 cnconx (change notice control for portx)......... 282 config (configuration register - cp0 register 16, se- lect 0).................................................................. 51 config1 (configuration register 1 - cp0 register 16, select 1) ............................................................. 52 config3 (configuration register 3 - cp0 register 16, select 3) ............................................................. 53 config5 (configuration register 5 - cp0 register 16, select 5) ............................................................. 54 config7 (configuration register 7 - cp0 register 16, select 7) ............................................................. 54 cvrcon (comparator voltage reference control) 573 dchxcon (dma channel x control)....................... 186 dchxcptr (dma channel x cell pointer) .............. 194 dchxcsiz (dma channel x cell-size).................... 194 dchxdat (dma channel x pattern data) ............... 195 dchxdptr (channel x destination pointer) ........... 193 dchxdsa (dma channel x destination ? start address)................................................... 191 dchxdsiz (dma channel x destination size) ........ 192 dchxecon (dma channel x event control) .......... 188 dchxint (dma channel x interrupt control)........... 189 dchxsptr (dma channel x source pointer) ......... 193 dchxssa (dma channel x source start address) . 191 dchxssiz (dma channel x source size) ............... 192 dcrccon (dma crc control) .............................. 183 dcrcdata (dma crc data)................................. 185 dcrcxor (dma crcxor enable) ....................... 185 devcfg0/adevcfg0 (device configuration word 0). 587 devcfg1/adevcfg1 (device configuration word 1). 589 devcfg2/adevcfg2 (device configuration word 2). 592 devcfg3/adevcfg3 (device configuration word 3). 594 devcp0/adevcp0 (device code-protect 0).......... 586 devid (device and revision id).............................. 601 devsign0/adevsign0 (device signature word 0) .... 586 dmaaddr (dma address)...................................... 182 dmacon (dma controller control) ......................... 181 dmastat (dma status).......................................... 182
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 730 ? 2015-2016 microchip technology inc. dmstat (deadman timer status) ........................... 297 dmtclr (deadman timer clear) ............................ 296 dmtcnt (deadman timer count) ........................... 298 dmtcon (deadman timer control)......................... 295 dmtpreclr (deadman timer preclear) ................ 295 dmtpsintv (post status configure dmt interval sta- tus) .................................................................... 299 ebicsx (external bus interface chip select) ........... 385 ebiftrpdx (external bus interface flash timing) .. 388 ebimskx (external bus interface address mask) .... 386 ebismcon (external bus interface static memory con- trol).................................................................... 389 ebismtx (external bus interface static memory timing) 387 emac1cfg1 (ethernet controller mac configuration 1) 550 emac1cfg2 (ethernet controller mac configuration 2) 551 emac1clrt (ethernet controller mac collision win- dow/retry limit) ................................................ 555 emac1ipgr (ethernet controller mac non-back-to- back interpacket gap) ...................................... 554 emac1ipgt (ethernet controller mac back-to-back in- terpacket gap) .................................................. 553 emac1madr (ethernet controller mac mii manage- ment address)................................................... 561 emac1maxf (ethernet controller mac maximum frame length) ............................................... ... 556 emac1mcfg (ethernet controller mac mii manage- ment configuration) .......................................... 559 emac1mcmd (ethernet controller mac mii manage- ment command) .............................................. . 560 emac1mind (ethernet controller mac mii manage- ment indicators) ................................................ 563 emac1mrdd (ethernet controller mac mii manage- ment read data).............................................. . 562 emac1mwtd (ethernet controller mac mii manage- ment write data)............................................... 562 emac1sa0 (ethernet controller mac station address 0)....................................................................... 564 emac1sa1 (ethernet controller mac station address 1)....................................................................... 565 emac1sa2 (ethernet controller mac station address 2)....................................................................... 566 emac1supp (ethernet controller mac phy support) . 557 emac1test (ethernet controller mac test) .......... 558 ethalgnerr (ethernet controller alignment errors statistics) .......................................................... 549 ethcon1 (ethernet controller control 1)................ 528 ethcon2 (ethernet controller control 2)................ 530 ethfcserr (ethernet controller frame check se- quence error statistics)..................................... 548 ethfrmrxok (ethernet controller frames received ok statistics) .................................................... 547 ethfrmtxok (ethernet controller frames transmit- ted ok statistics) .............................................. 544 ethht0 (ethernet controller hash table 0) ............ 532 ethht1 (ethernet controller hash table 1) ............ 532 ethien (ethernet controller interrupt enable)......... 538 ethirq (ethernet controller interrupt request) ...... 539 ethmcolfrm (ethernet controller multiple collision frames statistics) ............................................. 546 ethpm0 (ethernet controller pattern match offset) 534 ethpmcs (ethernet controller pattern match check- sum).................................................................. 534 ethpmm0 (ethernet controller pattern match mask 0). 533 ethpmm1 (ethernet controller pattern match mask 1). 533 ethrxfc (ethernet controller receive filter configura- tion)................................................................... 535 ethrxovflow (ethernet controller receive overflow statistics) .......................................................... 543 ethrxst (ethernet controller rx packet descriptor start address)................................................... 531 ethrxwm (ethernet controller receive watermarks) . 537 ethscolfrm (ethernet controller single collision frames statistics)............................................. 545 ethstat (ethernet controller status)..................... 541 ethtxst (ethernet controller tx packet descriptor start address)................................................... 531 fccr (floating point condition codes register - cp1 register 25) ........................................................ 56 fcsr (floating point control and status register - cp1 register 31) ........................................................ 59 fenr (floating point exceptions and modes enable register - cp1 register 28) ............................... 58 fexr (floating point exceptions status register - cp1 register 26) ........................................................ 57 fir (floating point implementation register - cp1 reg- ister 0)................................................................. 55 i2cxcon (i2c control)............................................. 357 i2cxstat (i2c status)............................................. 359 icxcon (input capture x control)............................ 308 iecx (interrupt enable control) ................................ 149 ifsx (interrupt flag status) ...................................... 149 intcon (interrupt control)....................................... 145 intstat (interrupt status)....................................... 148 ipcx (interrupt priority control) ................................ 150 iptmr (interrupt proximity timer)............................ 148 nvmaddr (flash address) ..................................... 104 nvmbwp (flash boot (page) write-protect)............ 107 nvmcon (programming control) .................... 101, 103 nvmdatax (flash data (x = 0-3)) ......................... 105 nvmkey (programming unlock).............................. 104 nvmpwp (program flash write-protect)................. 106 nvmsrcaddr (source data address) .................. 105 ocxcon (output compare x control) ..................... 313 osccon (oscillator control) ................................... 158 osctun (frc tuning)............................................ 160 pmaddr (parallel port address) ............................. 375 pmaen (parallel port pin enable)............................ 377 pmcon (parallel port control)................................. 371 pmdin (parallel port input data)...................... 376, 381 pmdout (parallel port output data)....................... 376 pmmode (parallel port mode)................................. 373 pmraddr (parallel port read address)................. 380 pmstat (parallel port status (slave modes only).. 378 pmwaddr (parallel port write address) ................ 379 precon (prefetch module control) ........................ 171 prestat (prefetch module status) ........................ 172 priss (priority shadow select) ............................... 146 pscnt (post status configure dmt count status). 298 pwrcon (power control) ....................................... 114 refoxcon (reference oscillator control (x = 1-4)) ... 163 refoxtrim (reference oscilla tor trim (x = 1-4)). 164 rnmicon (non-maskable interrupt control) ........... 113
? 2015-2016 microchip technology inc. ds60001320d-page 731 pic32mz embedded connectivity with floating point unit (ef) family rpnr (peripheral pin select output)........................ 281 rswrst (software reset) ...................................... 112 rtcalrm (rtc alarm control)............................ 395 rtccon (rtcc control)......................................... 393 rtcdate (real-time clock date value) ................ 398 rtctime (real-time clock time value)................. 397 sbflag (system bus status flag) ............................ 91 sbtxeclrm (system bus target x multiple error clear (x = 0-13)........................................................... 95 sbtxeclrs (system bus target x single error single (x = 0-13)........................................................... 95 sbtxecon (system bus target x error control (x = 0- 13)....................................................................... 94 sbtxelog1 (system bus target x error log 1 (x = 0- 13)....................................................................... 92 sbtxelog2 (system bus target x error log 2 (x = 0- 13)....................................................................... 94 sbtxrdy (system bus target x region y read per- missions (x = 0-13); (y = 0-8)........................... 97 sbtxregy (system bus target x region y (x = 0- 13); (y = 0-8)...................................................... 96 sbtxwry (system bus target x region y write per- missions (x = 0-13); (y = 0-8)........................... 98 spixcon (spi control)............................................. 318 spixcon2 (spi control 2)........................................ 321 spixstat (spi status)............................................. 322 spllcon (system pll control).............................. 161 sqi1xcon1 (sqi xip control 1) ............................. 328 sqi1xcon2 (sqi xip control register 2) ............... 330 t1con (type a timer control) ................................ 285 txcon (type b timer control) ................................ 291 usbcsr0 (usb control status 0) ........................... 206 usbcsr1 (usb control status 1) ........................... 208 usbcsr2 (usb control status 2) ........................... 209 usbcsr3 (usb control status 3) ........................... 211 usbcsrcon (usb clock/reset control) ............... 245 usbdmaint (usb dma interrupt)........................... 236 usbdmaxa (usb dma channel x memory address).. 238 usbdmaxc (usb dma channel x control) ........... 237 usbdmaxn (usb dma channel x count) ............. 238 usbdpbfd (usb double packet buffer disable).... 239 usbeofrst (usb end-of-frame/soft reset control).. 233 usbexrpc (usb endpoint x request packet count (host mode only)) ........................................... . 239 usbexrxa (usb endpoint x receive address) .... 235 usbextxa (usb endpoint x transmit address) .... 234 usbfifoa (usb fifo address).............................. 230 usbhwver (usb hardware version)..................... 231 usbie0csr0 (usb indexed endpoint control status 0 (endpoint 0)) ..................................................... 213 usbie0csr2 (usb indexed endpoint control status 2 (endpoint 0)) ..................................................... 215 usbie0csr3 (usb indexed endpoint control status 3 (endpoint 0)) ..................................................... 216 usbiencsr0 (usb indexed endpoint control status 0 (endpoint 1-7)) .................................................. 217 usbiencsr1 (usb indexed endpoint control status 1 (endpoint 1-7)) .................................................. 220 usbiencsr2 (usb indexed endpoint control status 2 (endpoint 1-7))............................................... ... 223 usbiencsr3 (usb indexed endpoint control status 3 (endpoint 1-7))............................................... ... 224 usbinfo (usb information).................................... 232 usblpmr1 (usb link power management control 1) . 241 usblpmr2 (usb link power management control 2) . 243 usbtmcon1 (usb timing control 1)..................... 240 usbtmcon2 (usb timing control 2)..................... 240 wdtcon (watchdog timer control) ....................... 303 resets .............................................................................. 109 revision history................................................................ 721 s serial peripheral interface (spi) and inter-ic sound (i2s)315 serial quad interface (sqi) ..................................... ......... 325 software simulator (mplab x sim) ................................. 609 special features............................................................... 581 t timer1 module.............................................. .................... 283 timer2/3, timer4/5, timer6/7, and timer8/9 modules ..... 287 timing diagrams can i/o .................................................................... 649 ejtag ...................................................................... 662 external clock .......................................................... 625 i/o characteristics .................................................... 628 i2cx bus data (master mode) .................................. 645 i2cx bus data (slave mode) .................................. .. 647 i2cx bus start/stop bits (master mode)................... 645 i2cx bus start/stop bits (slave mode)..................... 647 input capture (capx) ............................................... 634 ocx/pwm................................................................. 635 output compare (ocx) ............................................ 635 parallel master port read ........................................ 655 parallel master port write......................................... 656 parallel slave port .................................................... 654 spix master mode (cke = 0) ................................... 636 spix master mode (cke = 1) ................................... 638 spix slave mode (cke = 0) ..................................... 640 spix slave mode (cke = 1) ..................................... 641 timer1-timer9 external clock.................................. 633 uart reception....................................................... 368 uart transmission (8-bit or 9-bit data) .................. 368 timing requirements clko and i/o ............................................... ............ 629 timing specifications can i/o requirements............................................ . 649 i2cx bus data requirements (master mode)........... 645 i2cx bus data requirements (slave mode)............. 647 input capture requirements .................................... 634 output compare/pwm requirements...................... 635 simple ocx/pwm mode requirements ................... 635 spix master mode (cke = 0) requirements............ 637 spix master mode (cke = 1) requirements............ 639 spix slave mode (cke = 1) requirements.............. 641 spix slave mode requirements (cke = 0).............. 640
pic32mz embedded connectivity with floating point unit (ef) family ds60001320d-page 732 ? 2015-2016 microchip technology inc. u uart ................................................................................ 361 usb interface diagram ..................................................... 198 v voltage regulator (on-chip)............................................. 603 w www address.................................................................. 733 www, on-line support..................................... ................. 12
? 2015-2016 microchip technology inc. ds60001320d-page 733 pic32mz embedded connectivity with floating point unit (ef) family the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
? 2015-2016 microchip technology inc. ds60001320d-page 734 pic32mz embedded connectivity with floating point unit (ef) family product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . architecture mz = mips32 ? m-class mpu core flash memory size 0512 = 512 kb 1024 = 1024 kb 2048 = 2048 kb family ef = embedded connectivity microcontroller family with floating po int unit key feature e = pic32 ef family features (no can, no crypto) f = pic32 ef family features (can, no crypto) g = pic32 ef family features (no can, no crypto) h = pic32 ef family features (can, no crypto) k = pic32 ef family features (crypto and can) m = pic32 ef family features (crypto and can) pin count 064 = 64-pin 100 = 100-pin 124 = 124-pin 144 = 144-pin speed blank = up to 200 mhz 250 = up to 252 mhz temperature range i = -40c to +85c (industrial) e = -40c to +125c (extended) package mr = 64-lead (9x9x0.9 mm) qfn (plastic quad flatpack) pt = 64-lead (10x10x1 mm) tqfp (thin quad flatpack) pt = 100-lead (12x12x1 mm) tqfp (thin quad flatpack) pf = 100-lead (14x14x1 mm) tqfp (thin quad flatpack) tl = 124-lead (9x9x0.9 mm) vtla (very thin leadless array) ph = 144-lead (16x16x1 mm) tqfp (thin quad flatpack) pl = 144-lead (20x20x1.40 mm) lqfp (low profile quad flatpack) pattern three-digit qtp, sqtp, code or special requirements (blank otherwise) es = engineering sample example: pic32mz2048efh144-i/pt: ? embedded connectivity pic32, ? mips32 ? m-class mpu core, ? 2048 kb program memory, ? 144-pin, with floating point unit, ? industrial temperature, tqfp package. microchip brand architecture flash memory family key feature set pic32 mz xxxx ef e xxx a t - 250 i / pt - xxx flash memory size tape and reel flag (if applicable) pattern package temperature range pin count family additional feature set speed
? 2015-2016 microchip technology inc. ds60001320d-page 735 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of micr ochip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered tradem arks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2015-2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0765-2 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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